[coreboot-gerrit] Patch set updated for coreboot: imgtec/pistachio: add SOC_REGISTERS memory region

[Ionela Voinescu (ionela.voinescu@imgtec.com)]

Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12768

-gerrit

commit 78cd04edcc1ee9e29416bf2be5bf543a4559c4a0
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Fri Jul 24 14:29:06 2015 +0100

    imgtec/pistachio: add SOC_REGISTERS memory region
    
    When used with a U-boot payload it will need this region
    identity mapped also, so we're defining it in preparation
    for that functionality.
    
    Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/arch/mips/include/arch/memlayout.h            | 2 ++
 src/include/symbols.h                             | 4 ++++
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h
index 1fc7c74..fe05bd8 100644
--- a/src/arch/mips/include/arch/memlayout.h
+++ b/src/arch/mips/include/arch/memlayout.h
@@ -26,4 +26,6 @@
 
 #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
 
+#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4)
+
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/include/symbols.h b/src/include/symbols.h
index aa055ec..662f44e 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -72,6 +72,10 @@ extern u8 _dma_coherent[];
 extern u8 _edma_coherent[];
 #define _dma_coherent_size (_edma_coherent - _dma_coherent)
 
+extern u8 _soc_registers[];
+extern u8 _esoc_registers[];
+#define _soc_registers_size (_esoc_registers - _soc_registers)
+
 extern u8 _framebuffer[];
 extern u8 _eframebuffer[];
 #define _framebuffer_size (_eframebuffer - _framebuffer)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index edf9c41..a0b48b2 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,6 +29,8 @@ SECTIONS
 	POSTRAM_CBFS_CACHE(0x00200000, 512K)
 	RAMSTAGE(0x00280000, 128K)
 
+	/* 0x18100000 -> 0x18540000 */
+	SOC_REGISTERS(0x18100000, 0x440000)
 	/*
 	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock
 	 * and then through the identity mapping in ROM stage.