[coreboot-gerrit] Patch set updated for coreboot: lenovo/x200: Revise onboard IRQ routing

[Nico Huber (nico.h@gmx.de)]

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12813

-gerrit

commit 0688122cff40e62cad04bed970b27625aa9a7325
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Dec 29 23:35:37 2015 +0100

    lenovo/x200: Revise onboard IRQ routing
    
    All southbridge interrupt pin and routing registers (D*IP and D*IR)
    are left at their default values (see ICH9 datasheet) and this file
    just has to reflect them.
    
    Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
index 4a9ede8..aefdf94 100644
--- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
+++ b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
@@ -28,6 +28,8 @@ Method(_PRT)
 			Package() { 0x0001ffff, 0, 0, 16 },
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, 0, 16 },
+			// Onboard GbE
+			Package() { 0x0019ffff, 0, 0, 16 },
 			// USB and EHCI			0:1a.x
 			Package() { 0x001affff, 0, 0, 16 },
 			Package() { 0x001affff, 1, 0, 17 },
@@ -36,16 +38,14 @@ Method(_PRT)
 			Package() { 0x001bffff, 0, 0, 16 },
 			// PCIe Root Ports		0:1c.x
 			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
 			// USB and EHCI			0:1d.x
 			Package() { 0x001dffff, 0, 0, 16 },
 			Package() { 0x001dffff, 1, 0, 17 },
 			Package() { 0x001dffff, 2, 0, 18 },
-			// FIXME
-			// CardBus/IEEE1394		0:1e.2, 0:1e.3
-			// Package() { 0x001effff, 0, 0, 22 },
-			// Package() { 0x001effff, 1, 0, 20 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, 0, 16 },
+			// LPC bridge sub devices	0:1f.x
 			Package() { 0x001fffff, 1, 0, 17 },
 			Package() { 0x001fffff, 2, 0, 18 }
 		})
@@ -55,6 +55,8 @@ Method(_PRT)
 			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard GbE
+			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// USB and EHCI			0:1a.x
 			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
@@ -63,16 +65,14 @@ Method(_PRT)
 			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// PCIe Root Ports		0:1c.x
 			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
 			// USB and EHCI			0:1d.x
 			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
 			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			// FIXME
-			// CardBus/IEEE1394		0:1e.2, 0:1e.3
-			// Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// LPC bridge sub devices	0:1f.x
 			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
 			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
 		})