[coreboot-gerrit] New patch to review for coreboot: 7e7e110 pcengines/apu1: Implement board GPIOs
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Mon Feb 2 09:21:30 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8326
-gerrit
commit 7e7e110043c78f9f0393c75263d143bcd62b7aea
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Nov 11 17:22:23 2014 +0200
pcengines/apu1: Implement board GPIOs
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/pcengines/apu1/BiosCallOuts.c | 3 +-
src/mainboard/pcengines/apu1/Makefile.inc | 2 +
src/mainboard/pcengines/apu1/gpio_ftns.c | 68 +++++++++++++++++++++++++++++
src/mainboard/pcengines/apu1/gpio_ftns.h | 47 ++++++++++++++++++++
src/mainboard/pcengines/apu1/mainboard.c | 19 ++++++++
src/mainboard/pcengines/apu1/romstage.c | 41 +++++++++++++++++
6 files changed, 179 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
index d97fe22..0bd74fe 100644
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c
@@ -24,6 +24,7 @@
#include "heapManager.h"
#include "SB800.h"
#include <stdlib.h>
+#include "gpio_ftns.h"
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
@@ -59,7 +60,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- u8 index = 0;
+ u8 index = get_spd_offset();
if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
index 7fbed57..b19ca88 100644
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -29,10 +29,12 @@ endif
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
+romstage-y += gpio_ftns.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
+ramstage-y += gpio_ftns.c
## DIMM SPD for on-board memory
SPD_BIN = $(obj)/spd.bin
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
new file mode 100644
index 0000000..b683543
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include "SBPLATFORM.h"
+#include <southbridge/amd/cimx/cimx_util.h>
+#include "gpio_ftns.h"
+
+u32 find_gpio_base(void)
+{
+ u8 pm_index, pm_data;
+ u32 base_addr = 0;
+
+ /* Find the ACPImmioAddr base address */
+ for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) {
+ outb( pm_index, PM_INDEX );
+ pm_data = inb( PM_DATA );
+ base_addr <<= 8;
+ base_addr |= (u32)pm_data;
+ }
+ base_addr &= 0xFFFFF000;
+ return (base_addr);
+}
+
+void configure_gpio(u32 base_addr, u32 gpio, u8 iomux_ftn, u8 setting)
+{
+ u8 bdata;
+ u8 *memptr;
+
+ memptr = (u8 *)(base_addr + IOMUX_OFFSET + gpio);
+ *memptr = iomux_ftn;
+
+ memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ bdata = *memptr;
+ bdata &= 0x07;
+ bdata |= setting; /* set direction and data value */
+ *memptr = bdata;
+}
+
+u8 read_gpio(u32 base_addr, u32 gpio)
+{
+ u8 *memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ return (*memptr & GPIO_DATA_IN) ? 1 : 0;
+}
+
+int get_spd_offset(void)
+{
+ u32 base_addr = find_gpio_base();
+ u8 spd_offset = read_gpio(base_addr, GPIO_16);
+ return spd_offset;
+}
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h
new file mode 100644
index 0000000..11d5ea1
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef GPIO_FTNS_H
+#define GPIO_FTNS_H
+
+u32 find_gpio_base(void);
+void configure_gpio(u32 base_addr, u32 gpio, u8 iomux_ftn, u8 setting);
+u8 read_gpio(u32 base_addr, u32 gpio);
+int get_spd_offset(void);
+
+#define IOMUX_OFFSET 0xD00
+#define GPIO_OFFSET 0x100
+#define GPIO_10 10 // PE3 Reset
+#define GPIO_11 11 // PE4 Reset
+#define GPIO_15 15 // board rev strap ms bit
+#define GPIO_16 16 // board rev strap ls bit
+#define GPIO_17 17 // TP13
+#define GPIO_18 18 // TP10
+#define GPIO_187 187 // MODESW
+#define GPIO_189 189 // LED1#
+#define GPIO_190 190 // LED2#
+#define GPIO_191 191 // LED3#
+#define GPIO_FTN_1 0x01
+#define GPIO_OUTPUT 0x08
+#define GPIO_INPUT 0x28
+#define GPIO_DATA_IN 0x80
+#define GPIO_DATA_LOW 0x00
+#define GPIO_DATA_HIGH 0x40
+
+#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index cf0d823..01a0bd2 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -33,6 +33,7 @@
#include "SBPLATFORM.h"
#include <southbridge/amd/cimx/sb800/pci_devs.h>
#include <northbridge/amd/agesa/family14/pci_devs.h>
+#include "gpio_ftns.h"
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -161,6 +162,24 @@ static void mainboard_enable(device_t dev)
pirq_setup();
}
+static void mainboard_final(void *chip_info)
+{
+ u32 mmio_base;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n");
+
+ /*
+ * LED1/D7/GPIO_189 should be 0
+ * LED2/D6/GPIO_190 should be 1
+ * LED3/D5/GPIO_191 should be 1
+ */
+ mmio_base = find_gpio_base();
+ configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+}
+
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
+ .final = mainboard_final,
};
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index c555536..e9b9400 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -2,6 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
+ * Copyright (C) 2014 Kyösti Mälkki <kyosti.malkki at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,6 +34,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
+#include <southbridge/amd/cimx/cimx_util.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/cache.h>
#include <sb_cimx.h>
@@ -41,10 +44,13 @@
#include <cpu/amd/agesa/s3_resume.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
+#include "gpio_ftns.h"
#define SIO_PORT 0x2e
#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+static void early_lpc_init(void);
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
@@ -64,6 +70,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
+ early_lpc_init();
+
post_code(0x31);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -112,3 +120,36 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x54); /* Should never see this post code. */
}
+
+static void early_lpc_init(void)
+{
+ u32 mmio_base;
+
+ /* PC Engines requires system boot when power is applied. This feature is
+ * controlled in PM_REG 5Bh register. "Always Power On" works by writing a
+ * value of 05h.
+ */
+ u8 bdata = pm_ioread(SB_PMIOA_REG5B);
+ bdata &= 0xf8; //clear bits 0-2
+ bdata |= 0x05; //set bits 0,2
+ pm_iowrite(SB_PMIOA_REG5B, bdata);
+
+ /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
+ bdata = pm_ioread(SB_PMIOA_REGEA);
+ bdata &= 0xfe; //clear bit 0
+ bdata |= 0x01; //set bit 0
+ pm_iowrite(SB_PMIOA_REGEA, bdata);
+
+ //configure required GPIOs
+ mmio_base = find_gpio_base();
+ configure_gpio(mmio_base, GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ configure_gpio(mmio_base, GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ configure_gpio(mmio_base, GPIO_15, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_16, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_17, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_18, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_187, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+}
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