[coreboot-gerrit] New patch to review for coreboot: 54639cd intel/fsp_rangeley: Coding style, fix '#define' indentation inconsistent

[York Yang (york.yang@intel.com)]

York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8333

-gerrit

commit 54639cd31ebdcc1d30112dc221db35fcd2bf4195
Author: York Yang <york.yang at intel.com>
Date:   Tue Feb 3 14:14:42 2015 -0700

    intel/fsp_rangeley: Coding style, fix '#define' indentation inconsistent
    
    The indentations of #define are not consistent in chip.h. Update to make
    all #define indentations being aligned.
    
    Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
    Signed-off-by: York Yang <york.yang at intel.com>
---
 src/northbridge/intel/fsp_rangeley/chip.h | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
old mode 100644
new mode 100755
index d3828c7..a8d0a1f
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -52,21 +52,22 @@ struct northbridge_intel_fsp_rangeley_config {
 	/* Enable the Rank Margin Tool, needs PrintDebugMessages */
 	uint8_t MrcRmtSupport;
 
-#define BIFURCATION_4_4_4_4 0
-#define BIFURCATION_4_4_8   1
-#define BIFURCATION_8_4_4   2
-#define BIFURCATION_8_8     3
-#define BIFURCATION_16      4
+	/* PCIe port bifurcation control */
 	uint8_t Bifurcation;
+	#define BIFURCATION_4_4_4_4             0
+	#define BIFURCATION_4_4_8               1
+	#define BIFURCATION_8_4_4               2
+	#define BIFURCATION_8_8                 3
+	#define BIFURCATION_16                  4
 
 	/* PCIe port de-emphasis control */
-	#define  DE_EMPHASIS_DEFAULT            0
-	#define  DE_EMPHASIS_MINUS_6_0_DB       1
-	#define  DE_EMPHASIS_MINUS_3_5_DB       2
-	uint8_t  PcdPcieRootPort1DeEmphasis;
-	uint8_t  PcdPcieRootPort2DeEmphasis;
-	uint8_t  PcdPcieRootPort3DeEmphasis;
-	uint8_t  PcdPcieRootPort4DeEmphasis;
+	uint8_t PcdPcieRootPort1DeEmphasis;
+	uint8_t PcdPcieRootPort2DeEmphasis;
+	uint8_t PcdPcieRootPort3DeEmphasis;
+	uint8_t PcdPcieRootPort4DeEmphasis;
+	#define DE_EMPHASIS_DEFAULT             0
+	#define DE_EMPHASIS_MINUS_6_0_DB        1
+	#define DE_EMPHASIS_MINUS_3_5_DB        2
 };
 
 #endif