[coreboot-gerrit] Patch set updated for coreboot: 9128adc AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Feb 4 02:31:06 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8329
-gerrit
commit 9128adcf936a3569e4a7647a04f2a8e6284d611a
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jan 27 12:18:17 2015 +0200
AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
A set of pins can be configured for GPIO or (parallel) PCI bridge use.
When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.
When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.
Fix devicetree entry for asrock/e350m1 and gizmosphere/gizmo, these boards
do not implement slots or integrated PCI devices.
Drop related dead code.
Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/advansus/a785e-i/mainboard.c | 4 --
src/mainboard/asrock/e350m1/devicetree.cb | 2 +-
src/mainboard/asus/m5a88-v/mainboard.c | 4 --
src/mainboard/avalue/eax-785e/mainboard.c | 4 --
src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 +-
src/southbridge/amd/cimx/sb800/late.c | 54 +++++----------------------
6 files changed, 11 insertions(+), 59 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index 9b6450d..90d3342 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -37,10 +37,6 @@ void enable_int_gfx(void)
{
volatile u8 *gpio_reg;
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
/* make sure the Acpi MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 0690664..7f44869 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -94,7 +94,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pnp 2e.f off end # GPIO_PP_OD
end
end #LPC
- device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+ device pci 14.4 off end # PCIB 0x4384
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB: NIC
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 8ee338e..9be0ce9 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -37,10 +37,6 @@ void enable_int_gfx(void)
{
volatile u8 *gpio_reg;
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
/* make sure the MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 6ce3469..0f5f744 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -37,10 +37,6 @@ void enable_int_gfx(void)
{
volatile u8 *gpio_reg;
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
/* make sure the Acpi MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb
index 8cd4cd3..baa10b3 100644
--- a/src/mainboard/gizmosphere/gizmo/devicetree.cb
+++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb
@@ -48,7 +48,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on end # LPC 0x439d
- device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
+ device pci 14.4 off end # PCIB 0x4384
device pci 14.5 off end # USB 2
device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 1eb865e..0c7f4d1 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -260,51 +260,6 @@ static const struct pci_driver gec_driver __pci_driver = {
};
/**
- * @brief Enable PCI Bridge
- *
- * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
- * 'PCIDisable' set to 0 to enable P2P bridge.
- * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
- * to function as GPIO {GPIO 35:0}.
- */
-static void pci_init(device_t dev)
-{
- /* PCI Bridge SHOULD be enabled by default according to SB800 rrg,
- * but actually was disabled in some platform, so I have to enabled it.
- */
- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
-}
-
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_PCI,
-};
-
-
-struct device_operations bridge_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0,
- .scan_bus = pci_scan_bridge,
- .enable = 0,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
-};
-
-/**
* South Bridge CIMx ramstage entry point wrapper.
*/
void sb_Before_Pci_Init(void)
@@ -452,6 +407,15 @@ static void sb800_enable(device_t dev)
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
+ /* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
+ * 'PCIDisable' set to 0 to enable P2P bridge.
+ * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
+ * to function as GPIO {GPIO 35:0}.
+ */
+ if (dev->enabled)
+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
+ else
+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);
break;
case (0x14 << 3) | 6: /* 0:14:6 GEC */
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