[coreboot-gerrit] New patch to review for coreboot: b1cb045 AMD HyperTransport: Refactor link optimisation
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Feb 4 09:12:30 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8341
-gerrit
commit b1cb045b8c82b32160812e853d46a5b4879948ef
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 3 12:18:02 2015 +0200
AMD HyperTransport: Refactor link optimisation
Change-Id: Iddcc49b87c152db20d99ea233aec7e5098732846
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/device/hypertransport.c | 104 ++++++++++++++++++++------------------------
1 file changed, 48 insertions(+), 56 deletions(-)
diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index 88a5fc6..b4c070f 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -30,16 +30,19 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
+#include <cpu/amd/model_fxx_rev.h>
/*
* The hypertransport link is already optimized in pre-RAM code so don't do
* it again.
*/
-#define OPT_HT_LINK 0
+#define RUN_HT_OPTIMIZE_LINK 0
-#if OPT_HT_LINK == 1
-#include <cpu/amd/model_fxx_rev.h>
-#endif
+struct ht_link {
+ struct device *dev;
+ unsigned pos;
+ unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
+};
static device_t ht_scan_get_devs(device_t *old_devices)
{
@@ -80,7 +83,6 @@ static device_t ht_scan_get_devs(device_t *old_devices)
return first;
}
-#if OPT_HT_LINK == 1
static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
{
/* Handle bugs in valid hypertransport frequency reporting. */
@@ -103,32 +105,19 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
/* AMD K8 unsupported 1GHz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
-#if CONFIG_K8_HT_FREQ_1G_SUPPORT
+ if (!IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT))
+ freq_cap &= ~(1 << HT_FREQ_1000Mhz);
-#if !CONFIG_K8_REV_F_SUPPORT
/* Only e0 later support 1GHz HT. */
- if (is_cpu_pre_e0())
+ if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) && is_cpu_pre_e0())
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
-#endif
-
-#else
- freq_cap &= ~(1 << HT_FREQ_1000Mhz);
-#endif
}
return freq_cap;
}
-#endif
-
-struct ht_link {
- struct device *dev;
- unsigned pos;
- unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
-};
-static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
+static int ht_optimize_link()
{
-#if OPT_HT_LINK == 1
static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
static const u8 pow2_to_link_width[] = { 7, 4, 5, 0, 1, 3 };
unsigned present_width_cap, upstream_width_cap;
@@ -137,35 +126,8 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
unsigned ln_present_width_out, ln_upstream_width_out;
unsigned freq, old_freq;
unsigned present_width, upstream_width, old_width;
-#endif
- struct ht_link cur[1];
- int reset_needed;
- int linkb_to_host;
-
- /* Set the hypertransport link width and frequency. */
- reset_needed = 0;
- /*
- * See which side of the device our previous write to set the unitid
- * came from.
- */
- cur->dev = dev;
- cur->pos = pos;
- linkb_to_host =
- (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
+ int reset_needed = 0;
- if (!linkb_to_host) {
- cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
- cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
- cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
- cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
- } else {
- cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
- cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
- cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
- cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
- }
-
-#if OPT_HT_LINK == 1
/* Read the capabilities. */
present_freq_cap =
ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
@@ -263,7 +225,41 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
dev_path(prev->dev), upstream_width, new_width);
}
}
-#endif
+
+ return reset_needed;
+}
+
+static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
+{
+ struct ht_link cur[1];
+ int reset_needed = 0;
+ int linkb_to_host;
+
+ /* Set the hypertransport link width and frequency. */
+
+ /*
+ * See which side of the device our previous write to set the unitid
+ * came from.
+ */
+ cur->dev = dev;
+ cur->pos = pos;
+ linkb_to_host =
+ (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
+
+ if (!linkb_to_host) {
+ cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
+ cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
+ cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
+ cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
+ } else {
+ cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
+ cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
+ cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
+ cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
+ }
+
+ if (RUN_HT_OPTIMIZE_LINK)
+ reset_needed = ht_optimize_link(cur, prev);
/*
* Remember the current link as the previous link, but look at the
@@ -582,12 +578,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn,
end_of_chain:
-#if OPT_HT_LINK == 1
if (bus->reset_needed)
- printk(BIOS_INFO, "HyperT reset needed\n");
- else
- printk(BIOS_DEBUG, "HyperT reset not needed\n");
-#endif
+ printk(BIOS_INFO, "HyperTransport reset needed\n");
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid && (ht_dev_num > 1)
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