[coreboot-gerrit] Patch set updated for coreboot: 9b283e3 cpu/intel: >= nehalem: add comments to msr finalize's
Alexander Couzens (lynxis@fe80.eu)
gerrit at coreboot.org
Thu Feb 5 01:30:56 CET 2015
Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8294
-gerrit
commit 9b283e394aac93e237324d703dde1b9150b51691
Author: Alexander Couzens <lynxis at fe80.eu>
Date: Wed Jan 28 01:51:04 2015 +0100
cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.
Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
src/cpu/intel/fsp_model_206ax/finalize.c | 9 +++++++++
src/cpu/intel/haswell/finalize.c | 9 +++++++++
src/cpu/intel/model_2065x/finalize.c | 10 +++++++++-
src/cpu/intel/model_206ax/finalize.c | 9 +++++++++
4 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 4ed5d1e..534b157 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -24,6 +24,11 @@
#include <cpu/x86/msr.h>
#include "model_206ax.h"
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
static void msr_set_bit(unsigned reg, unsigned bit)
{
msr_t msr = rdmsr(reg);
@@ -43,6 +48,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_206ax_finalize_smm(void)
{
+ /* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
@@ -67,6 +73,9 @@ void intel_model_206ax_finalize_smm(void)
msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
#endif
+ /* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+ /* Lock memory configuration to protect SMM */
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index 1731322..b87e8c2 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -24,6 +24,11 @@
#include <cpu/x86/msr.h>
#include "haswell.h"
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
#if 0
static void msr_set_bit(unsigned reg, unsigned bit)
{
@@ -46,6 +51,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_cpu_haswell_finalize_smm(void)
{
#if 0
+ /* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
@@ -70,7 +76,10 @@ void intel_cpu_haswell_finalize_smm(void)
msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
#endif
+ /* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+ /* Lock memory configuration to protect SMM */
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
#endif
}
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index b37a84c..1835dce 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -25,6 +25,11 @@
#include <cpu/intel/speedstep.h>
#include "model_2065x.h"
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
static void msr_set_bit(unsigned reg, unsigned bit)
{
msr_t msr = rdmsr(reg);
@@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_2065x_finalize_smm(void)
{
+ /* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
@@ -67,7 +73,9 @@ void intel_model_2065x_finalize_smm(void)
msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
#endif
-
+ /* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+ /* Lock memory configuration to protect SMM */
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 2c215a4..0c1fe75 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -25,6 +25,11 @@
#include <cpu/intel/speedstep.h>
#include "model_206ax.h"
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
static void msr_set_bit(unsigned reg, unsigned bit)
{
msr_t msr = rdmsr(reg);
@@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_206ax_finalize_smm(void)
{
+ /* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
@@ -68,6 +74,9 @@ void intel_model_206ax_finalize_smm(void)
msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
#endif
+ /* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+ /* Lock memory configuration to protect SMM */
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
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