[coreboot-gerrit] New patch to review for coreboot: 71ea297 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8376

-gerrit

commit 71ea29718d15452ad42b97d36ca9f26782abc657
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Feb 6 16:07:53 2015 -0600

    amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
    
    Coverity caught a mistake that led to an invalid 0 latency in
    the automatically generated PowerNow! ACPI _PSS objects.
    
    Fixed remaining Coverity warnings.
    
    Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/cpu/amd/model_10xxx/powernow_acpi.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
index e4e0289..f12d483 100644
--- a/src/cpu/amd/model_10xxx/powernow_acpi.c
+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
@@ -76,11 +76,11 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u32 *v;
 	struct cpuid_result cpuid1;
 
-	u16 Pstate_feq[10];
-	u32 Pstate_power[10];
-	u32 Pstate_latency[10];
-	u32 Pstate_control[10];
-	u32 Pstate_status[10];
+	u16 Pstate_feq[10] = {0};
+	u32 Pstate_power[10] = {0};
+	u32 Pstate_latency[10] = {0};
+	u32 Pstate_control[10] = {0};
+	u32 Pstate_status[10] = {0};
 	u8 Pstate_num;
 	u8 cmp_cap;
 	u8 index;
@@ -204,6 +204,9 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 			case 0x3:
 				expanded_cpuidv = 1000;
 				break;
+			default:
+				/* Should never reach this statement, but avoid a crash if we do */
+				expanded_cpuidv = 1;
 		}
 		core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
 
@@ -212,7 +215,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		power_step_up = (dtemp & 0xf000000) >> 24;
 		power_step_down = (dtemp & 0xf00000) >> 20;
 		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
-		pll_lock_time = (pll_lock_time & 0x3800) >> 11;
+		pll_lock_time = (dtemp & 0x3800) >> 11;
 		if (all_enabled_cores_have_same_cpufid)
 			core_latency = ((12 * power_step_down) + power_step_up) / 1000;
 		else