[coreboot-gerrit] New patch to review for coreboot: f10f14f T124: perform ram_repair when CPU rail is powered on in warmboot

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8416

-gerrit

commit f10f14f1ff019da585a8c688d839eb39473e844d
Author: Yen Lin <yelin at nvidia.com>
Date:   Thu Jul 10 14:11:16 2014 -0700

    T124: perform ram_repair when CPU rail is powered on in warmboot
    
    This patch is to perform software triggered RAM re-repair in
    the warm boot path.
    
    BUG=chrome-os-partner:30430
    BRANCH=nyan
    TEST=run suspend_stress_test on nyan.
    
    Original-Signed-off-by: Yen Lin<yelin at nvidia.com>
    Original-Change-Id: I540f8afbffa323d1e378cb6ba6a20be4afd08339
    Original-Reviewed-on: https://chromium-review.googlesource.com/207422
    Original-Tested-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Commit-Queue: Yen Lin <yelin at nvidia.com>
    (cherry picked from commit f06c413c42819f8f75d9b0fecde02b82583f1d2a)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I151ce943ce8623e46cc55f890bbd6fc641cc2b98
---
 src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 29 ++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 9b1a4b5..0a3cb48 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -193,6 +193,14 @@ enum {
 	FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0
 };
 
+static uint32_t *flow_ctlr_ram_repair_ptr =
+	(void *)(FLOW_CTLR_BASE + 0x40);
+static uint32_t *flow_ctlr_ram_repair_cluster1_ptr =
+	(void *)(FLOW_CTLR_BASE + 0x58);
+enum {
+	RAM_REPAIR_REQ = 0x1 << 0,
+	RAM_REPAIR_STS = 0x1 << 1,
+};
 
 
 /* Power management controller registers. */
@@ -483,6 +491,24 @@ static void clear_cpu_resets(void)
 
 
 
+/* RAM repair */
+
+void ram_repair(void)
+{
+	// Request Cluster0 RAM repair.
+	setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_ptr);
+	// Poll for Cluster0 RAM repair status.
+	while (!(read32(flow_ctlr_ram_repair_ptr) & RAM_REPAIR_STS))
+		;
+
+	// Request Cluster1 RAM repair.
+	setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_cluster1_ptr);
+	// Poll for Cluster1 RAM repair status.
+	while (!(read32(flow_ctlr_ram_repair_cluster1_ptr) & RAM_REPAIR_STS))
+		;
+}
+
+
 /* Power. */
 
 static void power_on_partition(unsigned id)
@@ -589,6 +615,9 @@ void lp0_resume(void)
 
 	power_on_main_cpu();
 
+	// Perform ram repair after cpu is powered on.
+	ram_repair();
+
 	clear_cpu_resets();
 
 	// Halt the AVP.