[coreboot-gerrit] Patch set updated for coreboot: fb810e3 Baytrail_fsp: Add new microcode for Baytrail M

[Werner Zeh (werner.zeh@siemens.com)]

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399

-gerrit

commit fb810e32e1bf87f7c99122ad6444d5bd93a69505
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Tue Feb 10 10:16:12 2015 +0100

    Baytrail_fsp: Add new microcode for Baytrail M
    
    Add a new microcode for Baytrail M D0 stepping used
    in cpu N2807 silicon.
    In addition, a selection of the used CPU type has
    beed added (I or M/D) which allows to use only the
    realy needed microcode for a given CPU type.
    
    Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/soc/intel/fsp_baytrail/Kconfig                    |  9 +++++++++
 src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 11 ++++++++---
 src/soc/intel/fsp_baytrail/microcode/microcode_size.h |  6 +++++-
 3 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 639071a..a7f3f77 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -51,6 +51,15 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD
 	select ROMSTAGE_RTC_INIT
 
+choice
+	prompt "Baytrail CPU type"
+	default SOC_INTEL_FSP_BAYTRAIL_I
+config SOC_INTEL_FSP_BAYTRAIL_I
+	bool "I"
+config SOC_INTEL_FSP_BAYTRAIL_MD
+	bool "M/D"
+endchoice
+
 config BOOTBLOCK_CPU_INIT
 	string
 	default "soc/intel/fsp_baytrail/bootblock/bootblock.c"
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
index 709ff92..fc5ab08 100644
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
@@ -19,10 +19,15 @@
 
 unsigned microcode[] = {
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I)
 /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-#include "M0230672228.h"  // M0230672: Baytrail "Super SKU" B0/B1
-#include "M0130673322.h"  // M0130673: Baytrail I B2 / B3
-#include "M0130679901.h"  // M0130679: Baytrail I D0
+	#include "M0230672228.h"  // M0230672: Baytrail "Super SKU" B0/B1
+	#include "M0130673322.h"  // M0130673: Baytrail I B2 / B3
+	#include "M0130679901.h"  // M0130679: Baytrail I D0
+#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
+	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
+	#include "M0C30678829.h"  // M0C30678: Baytrail M D Stepping
+#endif
 
 	/*  Dummy terminator  */
 	0x0, 0x0, 0x0, 0x0,
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
index ec55314..213fc17 100644
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
@@ -1,2 +1,6 @@
 /* Maximum size of the area that the FSP will search for the correct microcode */
-#define MICROCODE_REGION_LENGTH 0x30000
+#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I)
+	#define MICROCODE_REGION_LENGTH 0x30000
+#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
+	#define MICROCODE_REGION_LENGTH 0x10000
+#endif