[coreboot-gerrit] Patch set updated for coreboot: 92e625a AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Mon Feb 23 06:48:41 CET 2015
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8495
-gerrit
commit 92e625adb013ad74beaacfa9a430f146cedbbd15
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Nov 11 17:22:23 2014 +0200
AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
Some GPIO pins are shared with PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.
Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/amd/cimx/sb800/chip.h | 1 +
src/southbridge/amd/cimx/sb800/late.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h
index 2c2ce1e..f0ce075 100644
--- a/src/southbridge/amd/cimx/sb800/chip.h
+++ b/src/southbridge/amd/cimx/sb800/chip.h
@@ -35,6 +35,7 @@
struct southbridge_amd_cimx_sb800_config
{
u32 boot_switch_sata_ide : 1;
+ u32 disconnect_pcib : 1;
u8 gpp_configuration;
/*
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index e017936..2125027 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -401,7 +401,7 @@ static void sb800_enable(device_t dev)
* 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
* to function as GPIO {GPIO 35:0}.
*/
- if (dev->enabled)
+ if (!sb_chip->disconnect_pcib && dev->enabled)
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
else
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);
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