[coreboot-gerrit] Patch merged into coreboot/master: b5a8a13 pcengines/apu1: Fix 0:15.x PCIe root ports

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b5a8a13bde537893d1bf150b2d90156e4b855374
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jan 17 18:08:40 2015 +0200

    pcengines/apu1: Fix 0:15.x PCIe root ports
    
    Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
    to only advertise x1 lane width for PCIe link 0:15.0.
    
    Hide functions of PCIe links that have no slots connected. Our PCI
    infrastructure does not support bridge devices that are set off
    in devicetree but remain visible in the PCI hardware tree.
    
    Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: http://review.coreboot.org/8388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/8388 for details.

-gerrit