[coreboot-gerrit] New patch to review for coreboot: 140518c AMD K8 fam10: Add ht_route_link()

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8556

-gerrit

commit 140518c33c292a8e526f101a96424519b5cb6412
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Feb 23 12:05:33 2015 +0200

    AMD K8 fam10: Add ht_route_link()
    
    Change-Id: I41aeb80121f120641b65759c8502150ce89caa30
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/amdfam10/northbridge.c | 29 +++++++++++-----------
 src/northbridge/amd/amdk8/northbridge.c    | 40 ++++++++++++++++--------------
 2 files changed, 36 insertions(+), 33 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 49a28de..709bd0e 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -155,6 +155,20 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link)
 	return !!(link_type & NonCoherent);
 }
 
+static void ht_route_link(struct bus *link)
+{
+	u32 busses;
+
+	/* Configure the bus numbers for this bridge: the configuration
+	 * transactions will not be propagated by the bridge if it is
+	 * not correctly configured
+	 */
+	busses = pci_read_config32(link->dev, link->cap + 0x14);
+	busses &= 0xffff00ff;
+	busses |= ((u32)(link->secondary) << 8);
+	pci_write_config32(link->dev, link->cap + 0x14, busses);
+}
+
 static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink,
 				u32 max)
 {
@@ -166,7 +180,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
 		u32 max_bus;
 		u32 min_bus;
-		u32 busses;
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
 		u32 busn = max&0xff;
 #endif
@@ -215,19 +228,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		link->secondary = min_bus;
 		link->subordinate = max_bus;
 
-		/* Read the existing primary/secondary/subordinate bus
-		 * number configuration.
-		 */
-		busses = pci_read_config32(dev, link->cap + 0x14);
-
-		/* Configure the bus numbers for this bridge: the configuration
-		 * transactions will not be propagates by the bridge if it is
-		 * not correctly configured
-		 */
-		busses &= 0xffff00ff;
-		busses |= ((u32)(link->secondary) << 8);
-		pci_write_config32(dev, link->cap + 0x14, busses);
-
+		ht_route_link(link);
 
 		/* set the config map space */
 
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index a17aa65..208970e 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -96,6 +96,22 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link)
 	return !!(link_type & NonCoherent);
 }
 
+static void ht_route_link(struct bus *link)
+{
+	u32 busses;
+
+	/* Configure the bus numbers for this bridge: the configuration
+	 * transactions will not be propagated by the bridge if it is
+	 * not correctly configured
+	 */
+	busses = pci_read_config32(link->dev, link->cap + 0x14);
+	busses &= 0xff000000;
+	busses |= (((unsigned int)(dev->bus->secondary) << 0) |
+		((unsigned int)(link->secondary) << 8) |
+		((unsigned int)(link->subordinate) << 16));
+	pci_write_config32(link->dev, link->cap + 0x14, busses);
+}
+
 static u32 amdk8_nodeid(device_t dev)
 {
 	return (dev->path.pci.devfn >> 3) - 0x18;
@@ -105,7 +121,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
 				u32 max)
 {
 		int i;
-		u32 busses, config_busses;
+		u32 config_busses;
 		u32 free_reg, config_reg;
 		u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
 		u32 max_bus;
@@ -172,22 +188,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
 		link->secondary = min_bus;
 		link->subordinate = max_bus;
 
-		/* Read the existing primary/secondary/subordinate bus
-		 * number configuration.
-		 */
-		busses = pci_read_config32(dev, link->cap + 0x14);
-		config_busses = f1_read_config32(config_reg);
-
-		/* Configure the bus numbers for this bridge: the configuration
-		 * transactions will not be propagates by the bridge if it is
-		 * not correctly configured
-		 */
-		busses &= 0xff000000;
-		busses |= (((unsigned int)(dev->bus->secondary) << 0) |
-			((unsigned int)(link->secondary) << 8) |
-			((unsigned int)(link->subordinate) << 16));
-		pci_write_config32(dev, link->cap + 0x14, busses);
+		ht_route_link(link);
 
+		config_busses = f1_read_config32(config_reg);
 		config_busses &= 0x000fc88;
 		config_busses |=
 			(3 << 0) |  /* rw enable, no device compare */
@@ -215,9 +218,8 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
 		 * subordinate bus number to it's real value
 		 */
 		link->subordinate = max;
-		busses = (busses & 0xff00ffff) |
-			((unsigned int) (link->subordinate) << 16);
-		pci_write_config32(dev, link->cap + 0x14, busses);
+
+		ht_route_link(link);
 
 		config_busses = (config_busses & 0x00ffffff) |
 			(link->subordinate << 24);