[coreboot-gerrit] Patch merged into coreboot/master: 4d2d6ca soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 4d2d6ca79a03f60f28c8f8bc7591483260a15c1b
Author: Deepa Dinamani <deepad at codeaurora.org>
Date:   Tue May 13 13:49:42 2014 -0700

    soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
    
    Define a base address for page table entries. Place it 64KB below the
    bootblock loading address.
    
    BUG=chrome-os-partner:28467
    TEST=verified that the page tables are being populated at this
         address. Also observed that the SPI driver takes 900 ns to
         process a byte as opposed to 1.5 us in case caching is not
         enabled.
    
    Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
    Original-Signed-off-by: Deepa Dinamani <deepad at codeaurora.org>
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/200332
    (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
    Reviewed-on: http://review.coreboot.org/8009
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/8009 for details.

-gerrit