[coreboot-gerrit] Patch merged into coreboot/master: 1e3679d tegra124: configure DP with correct pixel clock

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1e3679ddd0fd03fdc00b50a45fc652a539b9c9a7
Author: Vince Hsu <vinceh at nvidia.com>
Date:   Wed Jun 11 17:14:05 2014 +0800

    tegra124: configure DP with correct pixel clock
    
    For some panels, the plld can't provide the pixel clock that
    the panels wants, so we give it a good enough one. And we
    should calculate the dp/dc settings by the real pixel clock.
    
    BRANCH=nyan
    BUG=chrome-os-partner:29489
    TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
    No screen flicker is observed. No sor dp fifo underflow found.
    
    Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
    Original-Signed-off-by: Vince Hsu <vinceh at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/203358
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac
    Reviewed-on: http://review.coreboot.org/8044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/8044 for details.

-gerrit