[coreboot-gerrit] New patch to review for coreboot: 05066db superio/smsc/lpc47n207: Remove poorly implemented SIO support
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Jan 5 11:25:08 CET 2015
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8102
-gerrit
commit 05066db0da9f7474a9e327dce024487c82627431
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Jan 5 21:21:16 2015 +1100
superio/smsc/lpc47n207: Remove poorly implemented SIO support
We remove the final superio .c includes here. The 'lpc47n207'
was never properly hooked into the build system and the
corresponding boards do not actually contain this superio necessarily.
The support was for add-on lpc debug cards however we have better ways
to handle this now.
Change-Id: I9e2bc4677fe2198123a0f4c3e0ad8928cae97296
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/samsung/lumpy/romstage.c | 15 -----
src/mainboard/samsung/stumpy/romstage.c | 15 -----
src/superio/smsc/lpc47n207/early_serial.c | 97 -------------------------------
src/superio/smsc/lpc47n207/lpc47n207.h | 25 --------
4 files changed, 152 deletions(-)
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 93cc068..85553fd 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -43,10 +43,6 @@
#include <halt.h>
#include "option_table.h"
#include "gpio.h"
-#if CONFIG_DRIVERS_UART_8250IO
-#include <superio/smsc/lpc47n207/lpc47n207.h>
-#include "superio/smsc/lpc47n207/early_serial.c"
-#endif
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -56,20 +52,9 @@ static void pch_enable_lpc(void)
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-#if CONFIG_DRIVERS_UART_8250IO
- /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
- pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
- KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
-
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
- try_enabling_LPC47N207_uart();
-#else
/* Enable SuperIO + EC + KBC */
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN);
-#endif
}
static void rcba_config(void)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index abaf48e..bbbefc3 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -43,10 +43,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
-#if CONFIG_DRIVERS_UART_8250IO
-#include <superio/smsc/lpc47n207/lpc47n207.h>
-#include "superio/smsc/lpc47n207/early_serial.c"
-#endif
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -69,19 +65,8 @@ static void pch_enable_lpc(void)
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-#if CONFIG_DRIVERS_UART_8250IO
- /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/
- pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
- CNF2_LPC_EN | COMA_LPC_EN);
-
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
- try_enabling_LPC47N207_uart();
-#else
/* Enable SuperIO + PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
-#endif
}
static void rcba_config(void)
diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c
deleted file mode 100644
index e2ae49d..0000000
--- a/src/superio/smsc/lpc47n207/early_serial.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * This code tries to discover the SMSC LPC47N207 superio chip which can be
- * connected over an LPC dongle. The chip could be bootstrap mapped to one of
- * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e.
- *
- * Initializing the UART requires accesses to a few control registers. This
- * structure includes the register offset and the value to write (along with
- * the mask).
- */
-typedef struct {
- u8 conf_reg;
- u8 value;
- u8 mask;
-} uart_conf;
-
-/* All regs/values to write to initialize the LPC47N207 UART */
-static const uart_conf uart_conf_data [] = {
- {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */
- {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */
- {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */
-};
-
-void try_enabling_LPC47N207_uart(void)
-{
- u8 reg_value;
- const uart_conf* conf_item;
- u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
- u16 lpc_port;
- int i, j;
-
-#define CONFIG_ENABLE 0x55
-#define CONFIG_DISABLE 0xaa
-
- for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) {
- lpc_port = lpc_ports[j];
-
- /* enable CONFIG mode */
- outb(CONFIG_ENABLE, lpc_port);
- reg_value=inb(lpc_port);
- if (reg_value != CONFIG_ENABLE) {
- continue; /* There is no LPC device at this address */
- }
-
- do {
- /*
- * Registers 12 and 13 hold config address, look for a
- * match.
- */
- outb(0x12, lpc_port);
- reg_value=inb(lpc_port + 1);
- if (reg_value != (lpc_port & 0xff))
- break;
-
- outb(0x13, lpc_port);
- reg_value=inb(lpc_port + 1);
- if (reg_value != (lpc_port >> 8))
- break;
-
- /* This must be the SMSC LPC 47N207, enable the UART. */
- for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) {
- u8 reg, value, mask;
-
- conf_item = uart_conf_data + i;
-
- reg = conf_item->conf_reg;
- value = conf_item->value;
- mask = conf_item->mask;
-
- outb(reg, lpc_port);
- reg_value = inb(lpc_port + 1);
- reg_value &= ~mask;
- reg_value |= (value & mask);
- outb(reg_value, lpc_port + 1);
- }
- } while (0);
- outb(CONFIG_DISABLE, lpc_port);
- }
-}
diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h
deleted file mode 100644
index 69689a4..0000000
--- a/src/superio/smsc/lpc47n207/lpc47n207.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H
-#define SUPERIO_SMSC_LPC47N207_LPC47N207_H
-
-extern void try_enabling_LPC47N207_uart(void);
-
-#endif
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