[coreboot-gerrit] New patch to review for coreboot: 39a765a src: Remove useless comment
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Jan 12 21:54:04 CET 2015
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8205
-gerrit
commit 39a765aa3d780c88aac10a380836a9e9b1e04101
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Jan 13 07:51:42 2015 +1100
src: Remove useless comment
Change-Id: I544a975969eee50b6f1bbe682e4c167a40f172fa
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
.../amd/agesa/f10/Include/GeneralServices.h | 2 +-
.../amd/agesa/f10/Include/GnbInterfaceStub.h | 14 +--
.../amd/agesa/f10/Include/OptionMemoryInstall.h | 2 +-
.../amd/agesa/f10/Legacy/Proc/Dispatcher.c | 4 +-
.../amd/agesa/f10/Legacy/Proc/agesaCallouts.c | 24 ++--
.../amd/agesa/f10/Legacy/Proc/hobTransfer.c | 4 +-
src/vendorcode/amd/agesa/f10/Lib/amdlib.c | 46 ++++----
.../f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 6 +-
.../f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 4 +-
.../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 2 +-
.../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 2 +-
.../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 2 +-
.../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 2 +-
.../f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 6 +-
.../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 12 +-
.../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 2 +-
.../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c | 14 +--
.../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 8 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 10 +-
.../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 2 +-
.../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 2 +-
.../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 14 +--
.../agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c | 4 +-
.../f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 2 +-
.../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 2 +-
.../amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c | 8 +-
.../f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 6 +-
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 8 +-
.../f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 6 +-
.../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 4 +-
.../f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 8 +-
.../agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c | 2 +-
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 2 +-
.../f10/Proc/CPU/Family/0x10/cpuF10Utilities.c | 48 ++++----
.../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 2 +-
.../agesa/f10/Proc/CPU/Feature/PreserveMailbox.c | 4 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c | 6 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h | 4 +-
.../f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 4 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 8 +-
.../agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c | 16 +--
.../f10/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c | 8 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h | 18 +--
.../amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c | 4 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h | 4 +-
.../agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c | 6 +-
.../agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f10/Proc/CPU/Feature/cpuPstateTables.h | 2 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c | 56 ++++-----
src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h | 28 ++---
.../amd/agesa/f10/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c | 4 +-
src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c | 4 +-
.../amd/agesa/f10/Proc/CPU/cpuEarlyInit.c | 10 +-
.../amd/agesa/f10/Proc/CPU/cpuEventLog.c | 12 +-
.../amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f10/Proc/CPU/cpuGeneralServices.c | 50 ++++----
.../amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c | 2 +-
.../amd/agesa/f10/Proc/CPU/cpuLateInit.c | 10 +-
.../amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f10/Proc/CPU/cpuPostInit.c | 16 +--
.../amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c | 12 +-
.../agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c | 10 +-
.../amd/agesa/f10/Proc/CPU/cpuWarmReset.c | 6 +-
.../amd/agesa/f10/Proc/CPU/heapManager.c | 10 +-
.../amd/agesa/f10/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f10/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f10/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f10/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f10/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f10/Proc/Common/AmdInitRecovery.c | 4 +-
.../amd/agesa/f10/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f10/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f10/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f10/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f10/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f10/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f10/Proc/Common/CommonReturns.c | 16 +--
.../amd/agesa/f10/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f10/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f10/Proc/Common/S3SaveState.c | 18 +--
.../agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c | 2 +-
.../agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c | 2 +-
.../f10/Proc/HT/Fam10/htNbOptimizationFam10.c | 4 +-
.../amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c | 8 +-
.../agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c | 16 +--
.../f10/Proc/HT/Features/htFeatDynamicDiscovery.c | 20 ++--
.../amd/agesa/f10/Proc/HT/Features/htFeatGanging.c | 2 +-
.../agesa/f10/Proc/HT/Features/htFeatNoncoherent.c | 2 +-
.../f10/Proc/HT/Features/htFeatOptimization.c | 18 +--
.../amd/agesa/f10/Proc/HT/Features/htFeatRouting.c | 12 +-
.../agesa/f10/Proc/HT/Features/htFeatSublinks.c | 2 +-
.../Proc/HT/Features/htFeatTrafficDistribution.c | 2 +-
.../amd/agesa/f10/Proc/HT/Features/htIds.c | 2 +-
.../amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c | 22 ++--
.../agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c | 4 +-
.../agesa/f10/Proc/HT/NbCommon/htNbOptimization.c | 8 +-
.../amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c | 12 +-
src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f10/Proc/HT/htGraph/htGraph.c | 12 +-
src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f10/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f10/Proc/HT/htInterfaceGeneral.c | 16 +--
.../amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f10/Proc/IDS/Control/IdsLib.c | 2 +-
.../amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c | 8 +-
.../amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c | 4 +-
.../f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 2 +-
.../agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 8 +-
.../agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c | 4 +-
.../f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c | 2 +-
.../f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 2 +-
.../f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c | 20 ++--
.../amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/merrhdl.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c | 14 +--
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmMemClr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c | 10 +-
.../amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c | 2 +-
.../agesa/f10/Proc/Mem/Main/mmParallelTraining.c | 2 +-
.../agesa/f10/Proc/Mem/Main/mmStandardTraining.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Main/mmflow.c | 4 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c | 28 ++---
.../amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c | 12 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c | 8 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c | 8 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c | 10 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c | 16 +--
.../amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c | 14 +--
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c | 8 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c | 6 +-
.../amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c | 8 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c | 10 +-
.../amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c | 10 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c | 18 +--
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c | 18 +--
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c | 70 +++++------
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c | 20 ++--
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c | 8 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c | 28 ++---
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c | 38 +++---
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c | 16 +--
.../amd/agesa/f10/Proc/Mem/NB/mntrain2.c | 2 +-
.../amd/agesa/f10/Proc/Mem/NB/mntrain3.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c | 6 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c | 8 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c | 26 ++---
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c | 6 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c | 8 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c | 12 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c | 10 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c | 40 +++----
.../amd/agesa/f10/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Tech/mtthrc.c | 10 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c | 4 +-
.../amd/agesa/f10/Proc/Mem/Tech/mttsrc.c | 4 +-
src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h | 2 +-
.../amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c | 2 +-
.../agesa/f10/Proc/Recovery/HT/htInitRecovery.c | 4 +-
.../amd/agesa/f10/Proc/Recovery/HT/htInitReset.c | 6 +-
.../agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c | 16 +--
.../agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c | 14 +--
.../agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c | 14 +--
.../agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 2 +-
.../agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c | 16 +--
.../agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c | 14 +--
.../amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c | 8 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c | 18 +--
.../amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c | 10 +-
.../amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c | 2 +-
.../agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c | 2 +-
.../f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 6 +-
.../f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 10 +-
.../f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c | 4 +-
.../f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 8 +-
.../amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c | 16 +--
.../amd/agesa/f10/Proc/Recovery/Mem/mrdef.c | 4 +-
.../amd/agesa/f10/Proc/Recovery/Mem/mrinit.c | 2 +-
.../amd/agesa/f10/Proc/Recovery/Mem/mrm.c | 4 +-
.../amd/agesa/f10/Proc/Recovery/Mem/mruc.c | 12 +-
src/vendorcode/amd/agesa/f12/AMD.h | 2 +-
.../amd/agesa/f12/Include/GeneralServices.h | 2 +-
.../amd/agesa/f12/Include/GnbInterfaceStub.h | 20 ++--
.../amd/agesa/f12/Include/OptionMemoryInstall.h | 2 +-
.../amd/agesa/f12/Legacy/Proc/Dispatcher.c | 4 +-
.../amd/agesa/f12/Legacy/Proc/agesaCallouts.c | 28 ++---
.../amd/agesa/f12/Legacy/Proc/hobTransfer.c | 4 +-
src/vendorcode/amd/agesa/f12/Lib/amdlib.c | 46 ++++----
.../f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c | 2 +-
.../agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c | 10 +-
.../f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c | 4 +-
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c | 4 +-
.../f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 6 +-
.../f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 4 +-
.../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 2 +-
.../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 2 +-
.../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 2 +-
.../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 2 +-
.../f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 6 +-
.../f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c | 6 +-
.../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 14 +--
.../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 2 +-
.../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c | 16 +--
.../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 8 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 12 +-
.../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 2 +-
.../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 2 +-
.../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c | 12 +-
.../Family/0x10/RevE/PH/F10PhEquivalenceTable.c | 2 +-
.../0x10/RevE/PH/F10PhMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 14 +--
.../agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c | 4 +-
.../f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 2 +-
.../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 2 +-
.../amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Cpb.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c | 12 +-
.../f12/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 6 +-
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 8 +-
.../f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 6 +-
.../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 4 +-
.../f12/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 8 +-
.../agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c | 16 +--
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 2 +-
.../f12/Proc/CPU/Family/0x10/cpuF10Utilities.c | 34 +++---
.../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 2 +-
.../agesa/f12/Proc/CPU/Family/0x12/F12C6State.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c | 4 +-
.../agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c | 8 +-
.../CPU/Family/0x12/LN/F12LnEquivalenceTable.c | 2 +-
.../CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x12/cpuCommonF12Utilities.c | 14 +--
.../agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c | 4 +-
.../f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c | 2 +-
.../amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c | 10 +-
.../Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c | 2 +-
.../f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c | 6 +-
.../CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c | 4 +-
.../f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c | 4 +-
.../agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c | 12 +-
.../Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c | 2 +-
.../f12/Proc/CPU/Family/0x12/cpuF12Utilities.c | 22 ++--
.../CPU/Family/0x12/cpuF12WheaInitDataTables.c | 2 +-
.../agesa/f12/Proc/CPU/Feature/PreserveMailbox.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c | 8 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h | 8 +-
.../f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 6 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c | 12 +-
.../agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c | 22 ++--
.../f12/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c | 6 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h | 10 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c | 8 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h | 26 ++---
.../agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c | 6 +-
.../agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h | 4 +-
.../agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c | 6 +-
.../agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f12/Proc/CPU/Feature/cpuPstateTables.h | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h | 4 +-
.../amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c | 62 +++++-----
src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h | 28 ++---
.../amd/agesa/f12/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c | 4 +-
src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c | 4 +-
.../amd/agesa/f12/Proc/CPU/cpuEarlyInit.c | 12 +-
.../amd/agesa/f12/Proc/CPU/cpuEventLog.c | 12 +-
.../amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f12/Proc/CPU/cpuGeneralServices.c | 56 ++++-----
.../amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c | 2 +-
.../amd/agesa/f12/Proc/CPU/cpuLateInit.c | 10 +-
.../amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f12/Proc/CPU/cpuPostInit.c | 16 +--
.../amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c | 12 +-
.../agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c | 10 +-
.../amd/agesa/f12/Proc/CPU/cpuWarmReset.c | 8 +-
.../amd/agesa/f12/Proc/CPU/heapManager.c | 16 +--
.../amd/agesa/f12/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f12/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f12/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f12/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f12/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f12/Proc/Common/AmdInitRecovery.c | 4 +-
.../amd/agesa/f12/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f12/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f12/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f12/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f12/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f12/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f12/Proc/Common/CommonReturns.c | 20 ++--
.../amd/agesa/f12/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f12/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f12/Proc/Common/S3SaveState.c | 24 ++--
.../amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Common/FchLib.c | 18 +--
.../amd/agesa/f12/Proc/Fch/Common/FchPeLib.c | 4 +-
.../amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c | 10 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c | 4 +-
.../amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c | 4 +-
.../f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c | 12 +-
.../amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c | 32 +++---
.../amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c | 2 +-
.../f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c | 22 ++--
src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c | 16 +--
.../amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c | 10 +-
.../amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c | 8 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c | 4 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c | 4 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtLate.c | 2 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtMid.c | 2 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtPost.c | 4 +-
.../amd/agesa/f12/Proc/GNB/GnbInitAtReset.c | 2 +-
.../Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c | 6 +-
.../f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 36 +++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 4 +-
.../f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 4 +-
.../f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 26 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c | 8 +-
.../f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c | 4 +-
.../Modules/GnbFamTranslation/GnbPcieTranslation.c | 26 ++---
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 6 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 4 +-
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 4 +-
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 14 +--
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 26 ++---
.../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c | 4 +-
.../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c | 4 +-
.../f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c | 6 +-
.../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c | 18 +--
.../f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 10 +-
.../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 14 +--
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 38 +++---
.../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 14 +--
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 20 ++--
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c | 18 +--
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 2 +-
.../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c | 4 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c | 8 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 22 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 10 +-
.../Modules/GnbPcieInitLibV1/PciePortServices.c | 22 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c | 8 +-
.../Modules/GnbPcieInitLibV1/PcieSiliconServices.c | 8 +-
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 2 +-
.../GnbPcieInitLibV1/PcieTopologyServices.c | 26 ++---
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 24 ++--
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 16 +--
.../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 46 ++++----
.../Modules/GnbPcieTrainingV1/PcieWorkarounds.c | 16 +--
.../Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c | 2 +-
.../agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c | 8 +-
.../f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c | 6 +-
.../agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c | 4 +-
.../f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c | 14 +--
.../f12/Proc/GNB/Nb/Family/LN/F12NbServices.c | 8 +-
.../amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c | 2 +-
.../agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c | 10 +-
.../amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c | 2 +-
src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c | 2 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c | 6 +-
.../amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c | 32 +++---
.../f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c | 2 +-
.../Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c | 8 +-
.../GNB/PCIe/Family/LN/F12PcieComplexServices.c | 8 +-
.../Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c | 22 ++--
.../Proc/GNB/PCIe/Family/LN/F12PciePifServices.c | 4 +-
.../GNB/PCIe/Family/LN/F12PcieWrapperServices.c | 32 +++---
.../f12/Proc/GNB/PCIe/Feature/PciePowerGate.c | 14 +--
.../amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c | 14 +--
.../agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c | 2 +-
.../agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c | 2 +-
.../amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c | 8 +-
.../amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c | 6 +-
.../amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c | 14 +--
.../amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c | 6 +-
.../agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c | 2 +-
.../agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c | 2 +-
.../f12/Proc/HT/Fam10/htNbOptimizationFam10.c | 4 +-
.../amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c | 8 +-
.../agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c | 16 +--
.../agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c | 4 +-
.../f12/Proc/HT/Features/htFeatDynamicDiscovery.c | 20 ++--
.../amd/agesa/f12/Proc/HT/Features/htFeatGanging.c | 2 +-
.../agesa/f12/Proc/HT/Features/htFeatNoncoherent.c | 2 +-
.../f12/Proc/HT/Features/htFeatOptimization.c | 18 +--
.../amd/agesa/f12/Proc/HT/Features/htFeatRouting.c | 12 +-
.../agesa/f12/Proc/HT/Features/htFeatSublinks.c | 2 +-
.../Proc/HT/Features/htFeatTrafficDistribution.c | 2 +-
.../amd/agesa/f12/Proc/HT/Features/htIds.c | 2 +-
.../amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c | 22 ++--
.../agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c | 4 +-
.../agesa/f12/Proc/HT/NbCommon/htNbOptimization.c | 8 +-
.../amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c | 12 +-
src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f12/Proc/HT/htGraph/htGraph.c | 12 +-
src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f12/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f12/Proc/HT/htInterfaceGeneral.c | 16 +--
.../amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c | 2 +-
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src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c | 16 +--
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c | 52 ++++-----
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c | 124 ++++++++++----------
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c | 46 ++++----
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src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c | 38 +++---
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c | 56 ++++-----
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c | 22 ++--
.../amd/agesa/f12/Proc/Mem/NB/mntrain2.c | 2 +-
.../amd/agesa/f12/Proc/Mem/NB/mntrain3.c | 6 +-
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.../amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c | 26 ++---
.../amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
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.../amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c | 10 +-
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.../amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c | 42 +++----
.../amd/agesa/f12/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f12/Proc/Mem/Tech/mtthrc.c | 8 +-
.../amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c | 6 +-
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.../amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c | 4 +-
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.../amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.c | 14 +--
.../amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c | 8 +-
.../amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c | 50 ++++----
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.../amd/agesa/f14/Legacy/Proc/agesaCallouts.c | 26 ++---
.../amd/agesa/f14/Legacy/Proc/hobTransfer.c | 4 +-
src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 46 ++++----
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.../agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c | 16 +--
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 2 +-
.../f14/Proc/CPU/Family/0x10/cpuF10Utilities.c | 32 +++---
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.../Proc/CPU/Family/0x14/cpuCommonF14Utilities.c | 14 +--
.../agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c | 4 +-
.../f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c | 2 +-
.../amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c | 10 +-
.../f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c | 2 +-
.../f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c | 6 +-
.../CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c | 4 +-
.../f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c | 4 +-
.../agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c | 10 +-
.../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c | 2 +-
.../f14/Proc/CPU/Family/0x14/cpuF14Utilities.c | 22 ++--
.../CPU/Family/0x14/cpuF14WheaInitDataTables.c | 2 +-
.../agesa/f14/Proc/CPU/Feature/PreserveMailbox.c | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c | 8 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h | 8 +-
.../f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 6 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c | 12 +-
.../agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c | 16 +--
.../f14/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c | 8 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h | 20 ++--
.../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c | 6 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h | 10 +-
.../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c | 6 +-
.../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h | 4 +-
.../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c | 6 +-
.../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f14/Proc/CPU/Feature/cpuPstateTables.h | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h | 4 +-
.../amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c | 60 +++++-----
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h | 28 ++---
.../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c | 4 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c | 4 +-
.../amd/agesa/f14/Proc/CPU/cpuEarlyInit.c | 12 +-
.../amd/agesa/f14/Proc/CPU/cpuEventLog.c | 12 +-
.../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f14/Proc/CPU/cpuGeneralServices.c | 56 ++++-----
.../amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c | 2 +-
.../amd/agesa/f14/Proc/CPU/cpuLateInit.c | 10 +-
.../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f14/Proc/CPU/cpuPostInit.c | 16 +--
.../amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c | 12 +-
.../agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c | 10 +-
.../amd/agesa/f14/Proc/CPU/cpuWarmReset.c | 8 +-
.../amd/agesa/f14/Proc/CPU/heapManager.c | 16 +--
.../amd/agesa/f14/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f14/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f14/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f14/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f14/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f14/Proc/Common/AmdInitRecovery.c | 4 +-
.../amd/agesa/f14/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f14/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f14/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f14/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f14/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f14/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f14/Proc/Common/CommonReturns.c | 18 +--
.../amd/agesa/f14/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f14/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f14/Proc/Common/S3SaveState.c | 24 ++--
.../amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c | 4 +-
.../f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c | 12 +-
.../amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c | 32 +++---
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c | 2 +-
.../f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c | 22 ++--
src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c | 18 +--
.../amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c | 10 +-
.../amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c | 8 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c | 2 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c | 4 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtLate.c | 2 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtMid.c | 2 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtPost.c | 4 +-
.../amd/agesa/f14/Proc/GNB/GnbInitAtReset.c | 2 +-
.../Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c | 6 +-
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 28 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 4 +-
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 4 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 4 +-
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 26 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 6 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 6 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 4 +-
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 4 +-
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 14 +--
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 24 ++--
.../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c | 8 +-
.../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 10 +-
.../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 8 +-
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 20 ++--
.../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 12 +-
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 22 ++--
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c | 18 +--
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 2 +-
.../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c | 4 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c | 4 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 20 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 10 +-
.../Modules/GnbPcieInitLibV1/PciePortServices.c | 14 +--
.../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c | 8 +-
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c | 16 +--
.../Modules/GnbPcieInitLibV1/PcieSiliconServices.c | 8 +-
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 2 +-
.../GnbPcieInitLibV1/PcieTopologyServices.c | 26 ++---
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 16 +--
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 16 +--
.../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 46 ++++----
.../Modules/GnbPcieTrainingV1/PcieWorkarounds.c | 16 +--
.../f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c | 4 +-
.../Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c | 4 +-
.../f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c | 14 +--
.../f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c | 8 +-
.../agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c | 2 +-
.../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c | 10 +-
.../amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c | 2 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c | 6 +-
.../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c | 32 +++---
.../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c | 2 +-
.../GNB/PCIe/Family/0x14/F14PcieComplexConfig.c | 4 +-
.../GNB/PCIe/Family/0x14/F14PcieComplexServices.c | 8 +-
.../Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c | 10 +-
.../Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c | 4 +-
.../GNB/PCIe/Family/0x14/F14PcieWrapperServices.c | 28 ++---
.../f14/Proc/GNB/PCIe/Feature/PciePowerGate.c | 14 +--
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c | 14 +--
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c | 2 +-
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c | 2 +-
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c | 8 +-
.../amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c | 6 +-
.../amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c | 4 +-
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c | 14 +--
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c | 8 +-
.../agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c | 2 +-
.../agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c | 2 +-
.../f14/Proc/HT/Fam10/htNbOptimizationFam10.c | 4 +-
.../amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c | 8 +-
.../agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c | 16 +--
.../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c | 4 +-
.../f14/Proc/HT/Features/htFeatDynamicDiscovery.c | 20 ++--
.../amd/agesa/f14/Proc/HT/Features/htFeatGanging.c | 2 +-
.../agesa/f14/Proc/HT/Features/htFeatNoncoherent.c | 2 +-
.../f14/Proc/HT/Features/htFeatOptimization.c | 18 +--
.../amd/agesa/f14/Proc/HT/Features/htFeatRouting.c | 12 +-
.../agesa/f14/Proc/HT/Features/htFeatSublinks.c | 2 +-
.../Proc/HT/Features/htFeatTrafficDistribution.c | 2 +-
.../amd/agesa/f14/Proc/HT/Features/htIds.c | 2 +-
.../amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c | 22 ++--
.../agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c | 4 +-
.../agesa/f14/Proc/HT/NbCommon/htNbOptimization.c | 8 +-
.../amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c | 12 +-
src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f14/Proc/HT/htGraph/htGraph.c | 12 +-
src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f14/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f14/Proc/HT/htInterfaceGeneral.c | 16 +--
.../amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c | 8 +-
.../amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c | 4 +-
.../f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 2 +-
.../agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 8 +-
.../agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c | 4 +-
.../f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c | 2 +-
.../f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 2 +-
.../f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 20 ++--
.../amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c | 10 +-
.../amd/agesa/f14/Proc/Mem/Main/merrhdl.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c | 14 +--
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Main/mmMemClr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 10 +-
.../amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c | 2 +-
.../agesa/f14/Proc/Mem/Main/mmParallelTraining.c | 2 +-
.../agesa/f14/Proc/Mem/Main/mmStandardTraining.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Main/mmflow.c | 4 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c | 26 ++---
.../amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c | 8 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c | 8 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c | 10 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c | 16 +--
.../amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c | 14 +--
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c | 8 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c | 16 +--
.../amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c | 4 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c | 6 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c | 10 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c | 6 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c | 12 +-
.../amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c | 16 +--
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c | 32 +++---
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c | 94 +++++++--------
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c | 46 ++++----
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 36 +++---
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c | 44 +++----
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c | 18 +--
.../amd/agesa/f14/Proc/Mem/NB/mntrain2.c | 2 +-
.../amd/agesa/f14/Proc/Mem/NB/mntrain3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c | 6 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c | 18 +--
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c | 26 ++---
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 20 ++--
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c | 8 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c | 12 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c | 10 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c | 40 +++----
.../amd/agesa/f14/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Tech/mtthrc.c | 8 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c | 2 +-
.../amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c | 4 +-
.../amd/agesa/f14/Proc/Mem/Tech/mttsrc.c | 4 +-
src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h | 2 +-
.../amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c | 2 +-
.../agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c | 2 +-
.../agesa/f14/Proc/Recovery/HT/htInitRecovery.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/HT/htInitReset.c | 6 +-
.../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c | 16 +--
.../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c | 14 +--
.../agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c | 14 +--
.../agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c | 16 +--
.../agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c | 14 +--
.../agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c | 10 +-
.../agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c | 8 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c | 14 +--
.../amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c | 14 +--
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c | 8 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c | 44 +++----
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c | 8 +-
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c | 8 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c | 2 +-
.../agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c | 6 +-
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 6 +-
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 10 +-
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c | 4 +-
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 8 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c | 6 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c | 2 +-
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c | 12 +-
.../amd/agesa/f14/Proc/Recovery/Mem/mrdef.c | 6 +-
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.../amd/agesa/f14/Proc/Recovery/Mem/mrm.c | 4 +-
.../amd/agesa/f14/Proc/Recovery/Mem/mruc.c | 12 +-
.../amd/agesa/f15/Include/GeneralServices.h | 2 +-
.../amd/agesa/f15/Include/GnbInterfaceStub.h | 20 ++--
.../amd/agesa/f15/Include/OptionMemoryInstall.h | 2 +-
.../amd/agesa/f15/Legacy/Proc/Dispatcher.c | 4 +-
.../amd/agesa/f15/Legacy/Proc/agesaCallouts.c | 30 ++---
.../amd/agesa/f15/Legacy/Proc/hobTransfer.c | 4 +-
src/vendorcode/amd/agesa/f15/Lib/amdlib.c | 46 ++++----
.../f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c | 2 +-
.../agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c | 10 +-
.../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c | 4 +-
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c | 4 +-
.../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 6 +-
.../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 4 +-
.../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 2 +-
.../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 2 +-
.../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 2 +-
.../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 2 +-
.../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 2 +-
.../f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 6 +-
.../f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c | 6 +-
.../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 14 +--
.../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 2 +-
.../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c | 16 +--
.../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 8 +-
.../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 12 +-
.../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 2 +-
.../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 2 +-
.../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c | 12 +-
.../Family/0x10/RevE/PH/F10PhEquivalenceTable.c | 2 +-
.../0x10/RevE/PH/F10PhMicrocodePatchTables.c | 2 +-
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 14 +--
.../agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c | 4 +-
.../f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 2 +-
.../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 2 +-
.../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c | 12 +-
.../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 8 +-
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 8 +-
.../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 6 +-
.../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 4 +-
.../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 8 +-
.../agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c | 16 +--
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 2 +-
.../f15/Proc/CPU/Family/0x10/cpuF10Utilities.c | 34 +++---
.../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 2 +-
.../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c | 2 +-
.../f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c | 2 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c | 4 +-
.../agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c | 4 +-
.../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c | 18 +--
.../CPU/Family/0x15/OR/F15OrEquivalenceTable.c | 2 +-
.../Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c | 4 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c | 10 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c | 18 +--
.../Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c | 2 +-
.../CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c | 2 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c | 8 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c | 2 +-
.../Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c | 4 +-
.../Family/0x15/OR/F15OrPowerMgmtSystemTables.c | 4 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c | 4 +-
.../Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c | 2 +-
.../f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c | 30 ++---
.../CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c | 2 +-
.../CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c | 6 +-
.../f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c | 10 +-
.../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c | 8 +-
.../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c | 10 +-
.../f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c | 18 +--
.../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c | 2 +-
.../Proc/CPU/Family/0x15/cpuCommonF15Utilities.c | 6 +-
.../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c | 2 +-
.../agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c | 4 +-
.../f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c | 2 +-
.../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c | 2 +-
.../f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c | 10 +-
.../f15/Proc/CPU/Family/0x15/cpuF15Utilities.c | 24 ++--
.../CPU/Family/0x15/cpuF15WheaInitDataTables.c | 2 +-
.../agesa/f15/Proc/CPU/Feature/PreserveMailbox.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuApm.c | 6 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuApm.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c | 8 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h | 8 +-
.../f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 6 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c | 12 +-
.../agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c | 22 ++--
.../f15/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c | 6 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h | 10 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c | 8 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h | 26 ++---
.../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c | 6 +-
.../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h | 4 +-
.../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c | 6 +-
.../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c | 6 +-
.../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h | 2 +-
.../agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f15/Proc/CPU/Feature/cpuPstateTables.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h | 4 +-
.../amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c | 62 +++++-----
src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h | 28 ++---
.../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c | 4 +-
src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c | 4 +-
.../amd/agesa/f15/Proc/CPU/cpuEarlyInit.c | 12 +-
.../amd/agesa/f15/Proc/CPU/cpuEventLog.c | 12 +-
.../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f15/Proc/CPU/cpuGeneralServices.c | 54 ++++-----
.../amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c | 2 +-
.../amd/agesa/f15/Proc/CPU/cpuLateInit.c | 12 +-
.../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f15/Proc/CPU/cpuPostInit.c | 16 +--
.../amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c | 16 +--
.../agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c | 14 +--
.../amd/agesa/f15/Proc/CPU/cpuWarmReset.c | 8 +-
.../amd/agesa/f15/Proc/CPU/heapManager.c | 16 +--
.../amd/agesa/f15/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f15/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f15/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f15/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f15/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f15/Proc/Common/AmdInitRecovery.c | 4 +-
.../amd/agesa/f15/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f15/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f15/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f15/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f15/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f15/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f15/Proc/Common/CommonReturns.c | 20 ++--
.../amd/agesa/f15/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f15/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f15/Proc/Common/S3SaveState.c | 24 ++--
.../agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c | 2 +-
.../agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c | 2 +-
.../f15/Proc/HT/Fam10/htNbOptimizationFam10.c | 4 +-
.../amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c | 8 +-
.../agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c | 16 +--
.../agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c | 2 +-
.../agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c | 2 +-
.../f15/Proc/HT/Fam15/htNbOptimizationFam15.c | 2 +-
.../amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c | 8 +-
.../agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c | 18 +--
.../f15/Proc/HT/Features/htFeatDynamicDiscovery.c | 20 ++--
.../amd/agesa/f15/Proc/HT/Features/htFeatGanging.c | 2 +-
.../agesa/f15/Proc/HT/Features/htFeatNoncoherent.c | 2 +-
.../f15/Proc/HT/Features/htFeatOptimization.c | 18 +--
.../amd/agesa/f15/Proc/HT/Features/htFeatRouting.c | 12 +-
.../agesa/f15/Proc/HT/Features/htFeatSublinks.c | 2 +-
.../Proc/HT/Features/htFeatTrafficDistribution.c | 2 +-
.../amd/agesa/f15/Proc/HT/Features/htIds.c | 2 +-
.../amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c | 22 ++--
.../agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c | 4 +-
.../agesa/f15/Proc/HT/NbCommon/htNbOptimization.c | 8 +-
.../amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c | 12 +-
src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f15/Proc/HT/htGraph/htGraph.c | 12 +-
src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f15/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f15/Proc/HT/htInterfaceGeneral.c | 16 +--
.../amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c | 8 +-
.../amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c | 4 +-
.../f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 2 +-
.../agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 8 +-
.../agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c | 4 +-
.../f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c | 2 +-
.../f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 2 +-
.../f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c | 20 ++--
.../amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c | 2 +-
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.../amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c | 10 +-
.../amd/agesa/f15/Proc/Mem/Main/merrhdl.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c | 8 +-
.../amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c | 14 +--
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Main/mmMemClr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c | 10 +-
.../amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c | 2 +-
.../agesa/f15/Proc/Mem/Main/mmParallelTraining.c | 2 +-
.../agesa/f15/Proc/Mem/Main/mmStandardTraining.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmflow.c | 4 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c | 28 ++---
.../amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c | 10 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c | 14 +--
.../amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c | 4 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c | 8 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c | 8 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c | 10 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c | 16 +--
.../amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c | 4 +-
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.../amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c | 10 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c | 14 +--
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c | 4 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c | 10 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c | 14 +--
.../amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c | 4 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c | 8 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c | 6 +-
.../amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c | 8 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c | 18 +--
.../amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c | 4 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c | 4 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c | 14 +--
.../amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c | 4 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c | 34 +++---
.../amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c | 8 +-
.../amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c | 16 +--
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c | 12 +-
.../amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c | 16 +--
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c | 52 ++++-----
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c | 124 ++++++++++----------
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c | 66 +++++------
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c | 12 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c | 38 +++---
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c | 58 +++++-----
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c | 22 ++--
.../amd/agesa/f15/Proc/Mem/NB/mntrain2.c | 2 +-
.../amd/agesa/f15/Proc/Mem/NB/mntrain3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c | 6 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c | 40 +++----
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c | 26 ++---
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 26 ++---
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c | 6 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c | 8 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c | 12 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c | 10 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c | 44 +++----
.../amd/agesa/f15/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Tech/mtthrc.c | 8 +-
.../amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c | 6 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c | 4 +-
.../amd/agesa/f15/Proc/Mem/Tech/mttsrc.c | 4 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h | 2 +-
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.../agesa/f15/Proc/Recovery/HT/htInitRecovery.c | 4 +-
.../amd/agesa/f15/Proc/Recovery/HT/htInitReset.c | 6 +-
.../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c | 16 +--
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.../amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c | 14 +--
.../agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 4 +-
.../amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c | 14 +--
.../agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 4 +-
.../amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c | 16 +--
.../agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 4 +-
.../agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c | 8 +-
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.../amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c | 16 +--
.../amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c | 14 +--
.../amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c | 14 +--
.../amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c | 8 +-
.../amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c | 50 ++++----
.../amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c | 8 +-
.../amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c | 6 +-
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.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c | 2 +-
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.../f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 6 +-
.../f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 10 +-
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.../f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 8 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c | 6 +-
.../f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c | 6 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c | 2 +-
.../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c | 12 +-
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.../amd/agesa/f15/Proc/Recovery/Mem/mrm.c | 4 +-
.../amd/agesa/f15/Proc/Recovery/Mem/mruc.c | 12 +-
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.../amd/agesa/f15tn/Include/OptionMemoryInstall.h | 2 +-
.../amd/agesa/f15tn/Legacy/Proc/Dispatcher.c | 4 +-
.../amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c | 32 +++---
.../amd/agesa/f15tn/Legacy/Proc/hobTransfer.c | 4 +-
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 46 ++++----
.../f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c | 2 +-
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c | 4 +-
.../agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c | 4 +-
.../CPU/Family/0x15/TN/F15TnEquivalenceTable.c | 2 +-
.../Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c | 8 +-
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c | 10 +-
.../CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c | 2 +-
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c | 4 +-
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c | 6 +-
.../Family/0x15/TN/F15TnPowerMgmtSystemTables.c | 4 +-
.../Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c | 2 +-
.../Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c | 4 +-
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c | 36 +++---
.../CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c | 2 +-
.../CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c | 6 +-
.../f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c | 12 +-
.../f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c | 4 +-
.../Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c | 12 +-
.../Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c | 6 +-
.../f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c | 4 +-
.../f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c | 14 +--
.../Proc/CPU/Family/0x15/cpuCommonF15Utilities.c | 6 +-
.../agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c | 2 +-
.../f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c | 4 +-
.../Proc/CPU/Family/0x15/cpuF15CacheDefaults.c | 2 +-
.../agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c | 4 +-
.../agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c | 2 +-
.../f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c | 2 +-
.../f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c | 6 +-
.../f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c | 24 ++--
.../CPU/Family/0x15/cpuF15WheaInitDataTables.c | 2 +-
.../agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c | 6 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c | 8 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h | 8 +-
.../f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 6 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c | 8 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c | 16 +--
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c | 22 ++--
.../f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c | 6 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c | 6 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h | 10 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c | 8 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h | 26 ++---
.../agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c | 8 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h | 4 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c | 6 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c | 6 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h | 4 +-
.../f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c | 6 +-
.../f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h | 2 +-
.../f15tn/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h | 4 +-
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c | 34 +++---
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h | 28 ++---
src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c | 28 ++---
.../amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/cpuBrandId.c | 4 +-
.../amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/cpuEventLog.c | 12 +-
.../agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c | 54 ++++-----
.../amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c | 2 +-
.../amd/agesa/f15tn/Proc/CPU/cpuLateInit.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f15tn/Proc/CPU/cpuPostInit.c | 16 +--
.../amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c | 16 +--
.../f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c | 14 +--
.../amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c | 8 +-
.../amd/agesa/f15tn/Proc/CPU/heapManager.c | 16 +--
.../amd/agesa/f15tn/Proc/CPU/mmioMapManager.c | 2 +-
.../amd/agesa/f15tn/Proc/CPU/mmioMapManager.h | 2 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c | 4 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f15tn/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f15tn/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f15tn/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f15tn/Proc/Common/CommonReturns.c | 20 ++--
.../amd/agesa/f15tn/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f15tn/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f15tn/Proc/Common/S3SaveState.c | 24 ++--
.../amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c | 2 +-
.../amd/agesa/f15tn/Proc/Fch/Common/FchLib.c | 18 +--
.../amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c | 12 +-
.../amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c | 10 +-
.../agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../agesa/f15tn/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c | 4 +-
.../agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c | 2 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c | 4 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c | 4 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c | 2 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c | 2 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c | 6 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c | 2 +-
.../amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c | 2 +-
.../Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c | 8 +-
.../f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 28 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 4 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 4 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 26 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 6 +-
.../Modules/GnbFamTranslation/GnbPcieTranslation.c | 28 ++---
.../GNB/Modules/GnbFamTranslation/GnbTranslation.c | 4 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 2 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c | 8 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c | 2 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 2 +-
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 4 +-
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 14 +--
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 44 +++----
.../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c | 8 +-
.../Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c | 8 +-
.../Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c | 12 +-
.../Modules/GnbInitTN/GfxIntegratedInfoTableTN.c | 28 ++---
.../f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c | 26 ++---
.../Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c | 10 +-
.../Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c | 2 +-
.../GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c | 16 +--
.../Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c | 32 +++---
.../Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c | 2 +-
.../Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c | 6 +-
.../Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c | 10 +-
.../Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c | 12 +-
.../Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c | 2 +-
.../Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c | 16 +--
.../Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c | 2 +-
.../Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c | 2 +-
.../Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c | 40 +++----
.../Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c | 28 ++---
.../Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c | 2 +-
.../f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c | 22 ++--
.../Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c | 10 +-
.../Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c | 20 ++--
.../Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c | 8 +-
.../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c | 6 +-
.../f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c | 8 +-
.../Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c | 6 +-
.../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c | 18 +--
.../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c | 20 ++--
.../Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 18 +--
.../f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c | 24 ++--
.../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c | 22 ++--
.../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c | 6 +-
.../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 14 +--
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 44 +++----
.../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 14 +--
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 20 ++--
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 2 +-
.../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c | 4 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c | 8 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 22 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 10 +-
.../Modules/GnbPcieInitLibV1/PciePortServices.c | 22 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c | 8 +-
.../Modules/GnbPcieInitLibV1/PcieSiliconServices.c | 8 +-
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 2 +-
.../GnbPcieInitLibV1/PcieTopologyServices.c | 28 ++---
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 26 ++---
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 16 +--
.../Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c | 8 +-
.../Modules/GnbPcieInitLibV4/PciePortServicesV4.c | 4 +-
.../GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c | 4 +-
.../GnbPcieInitLibV4/PcieWrapperServicesV4.c | 8 +-
.../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 46 ++++----
.../Modules/GnbPcieTrainingV1/PcieWorkarounds.c | 16 +--
.../Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c | 6 +-
.../Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c | 2 +-
.../f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c | 8 +-
.../f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c | 6 +-
.../f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c | 2 +-
.../f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c | 4 +-
.../Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c | 10 +-
src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f15tn/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c | 16 +--
.../agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c | 4 +-
.../amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c | 8 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c | 4 +-
.../f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 2 +-
.../f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 8 +-
.../agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 2 +-
.../agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 2 +-
.../agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 4 +-
.../f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 2 +-
.../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 2 +-
.../Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c | 20 ++--
.../amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mdef.c | 10 +-
.../amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/minit.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c | 8 +-
.../agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c | 14 +--
.../amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c | 12 +-
.../agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c | 2 +-
.../agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c | 2 +-
.../agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmflow.c | 4 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c | 30 ++---
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c | 24 ++--
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c | 12 +-
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c | 26 ++---
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c | 24 ++--
.../amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 14 +--
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c | 16 +--
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c | 56 ++++-----
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c | 126 ++++++++++----------
.../amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c | 50 ++++----
.../amd/agesa/f15tn/Proc/Mem/NB/mnflow.c | 12 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c | 38 +++---
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c | 56 ++++-----
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c | 24 ++--
.../amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c | 6 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c | 40 +++----
.../amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 26 ++---
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c | 8 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c | 12 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c | 10 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c | 46 ++++----
.../amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c | 8 +-
.../agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mttml.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c | 4 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c | 4 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 2 +-
.../amd/agesa/f16kb/Include/GeneralServices.h | 2 +-
.../amd/agesa/f16kb/Include/OptionCrat.h | 4 +-
.../amd/agesa/f16kb/Include/OptionMemoryInstall.h | 2 +-
.../amd/agesa/f16kb/Legacy/Proc/Dispatcher.c | 4 +-
.../amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c | 34 +++---
.../amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +-
src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 46 ++++----
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c | 4 +-
.../CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c | 2 +-
.../Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c | 6 +-
.../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c | 4 +-
.../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c | 12 +-
.../CPU/Family/0x16/KB/F16KbEquivalenceTable.c | 2 +-
.../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c | 2 +-
.../Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c | 6 +-
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c | 10 +-
.../CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c | 2 +-
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c | 2 +-
.../Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c | 10 +-
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c | 6 +-
.../Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c | 8 +-
.../Family/0x16/KB/F16KbPowerMgmtSystemTables.c | 4 +-
.../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c | 4 +-
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c | 12 +-
.../f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c | 36 +++---
.../agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c | 2 +-
.../f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c | 2 +-
.../Proc/CPU/Family/0x16/cpuF16CacheDefaults.c | 2 +-
.../agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c | 2 +-
.../f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c | 2 +-
.../f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c | 18 +--
.../CPU/Family/0x16/cpuF16WheaInitDataTables.c | 2 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c | 6 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c | 8 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h | 8 +-
.../f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 6 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c | 12 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c | 8 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c | 16 +--
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c | 22 ++--
.../f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c | 8 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c | 6 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c | 6 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h | 10 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h | 30 ++---
.../agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h | 4 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h | 2 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c | 6 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h | 4 +-
.../f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h | 2 +-
.../f16kb/Proc/CPU/Feature/cpuPstateLeveling.c | 2 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c | 12 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c | 12 +-
.../agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h | 4 +-
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c | 8 +-
src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c | 38 +++---
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c | 36 +++---
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h | 28 ++---
.../amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c | 46 ++++----
src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c | 4 +-
.../amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c | 16 +--
.../amd/agesa/f16kb/Proc/CPU/cpuEventLog.c | 12 +-
.../agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c | 22 ++--
.../agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h | 2 +-
.../amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c | 54 ++++-----
.../amd/agesa/f16kb/Proc/CPU/cpuLateInit.c | 10 +-
.../amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c | 12 +-
.../amd/agesa/f16kb/Proc/CPU/cpuPostInit.c | 12 +-
.../amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c | 8 +-
.../f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c | 14 +--
.../amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c | 8 +-
.../amd/agesa/f16kb/Proc/CPU/heapManager.c | 16 +--
.../amd/agesa/f16kb/Proc/CPU/mmioMapManager.h | 2 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitEarly.c | 8 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitEnv.c | 2 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitLate.c | 4 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitMid.c | 2 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitPost.c | 4 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitReset.c | 6 +-
.../amd/agesa/f16kb/Proc/Common/AmdInitResume.c | 6 +-
.../amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c | 4 +-
.../amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c | 6 +-
.../amd/agesa/f16kb/Proc/Common/AmdS3Save.c | 8 +-
.../amd/agesa/f16kb/Proc/Common/CommonInits.c | 2 +-
.../amd/agesa/f16kb/Proc/Common/CommonReturns.c | 28 ++---
.../amd/agesa/f16kb/Proc/Common/CreateStruct.c | 4 +-
.../amd/agesa/f16kb/Proc/Common/S3RestoreState.c | 8 +-
.../amd/agesa/f16kb/Proc/Common/S3SaveState.c | 24 ++--
.../amd/agesa/f16kb/Proc/Fch/Common/FchLib.c | 18 +--
.../amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c | 10 +-
.../amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c | 10 +-
.../agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../agesa/f16kb/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c | 4 +-
.../agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c | 2 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c | 4 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c | 4 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c | 4 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c | 4 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c | 6 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c | 2 +-
.../amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c | 2 +-
.../f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 28 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 4 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 4 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 26 ++---
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 6 +-
.../Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c | 8 +-
.../Modules/GnbFamTranslation/GnbPcieTranslation.c | 28 ++---
.../GNB/Modules/GnbFamTranslation/GnbTranslation.c | 12 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 2 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c | 8 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c | 2 +-
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 2 +-
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 4 +-
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 14 +--
.../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c | 8 +-
.../GnbGfxIntTableV3/GfxIntegratedInfoTable.c | 16 +--
.../Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c | 10 +-
.../GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c | 60 +++++-----
.../f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c | 4 +-
.../Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c | 12 +-
.../Modules/GnbInitKB/GfxIntegratedInfoTableKB.c | 14 +--
.../f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c | 8 +-
.../Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c | 16 +--
.../Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c | 8 +-
.../Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c | 4 +-
.../Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c | 6 +-
.../Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c | 6 +-
.../f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c | 6 +-
.../Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c | 2 +-
.../Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c | 6 +-
.../Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c | 24 ++--
.../Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c | 32 +++---
.../Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c | 2 +-
.../f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c | 16 +--
.../Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c | 14 +--
.../Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c | 20 ++--
.../f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c | 6 +-
.../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c | 18 +--
.../GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c | 12 +-
.../Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c | 12 +-
.../f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c | 8 +-
.../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c | 22 ++--
.../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c | 6 +-
.../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 14 +--
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 44 +++----
.../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 14 +--
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 20 ++--
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 2 +-
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 22 ++--
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 10 +-
.../Modules/GnbPcieInitLibV1/PciePortServices.c | 20 ++--
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 2 +-
.../GnbPcieInitLibV1/PcieTopologyServices.c | 24 ++--
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 26 ++---
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 16 +--
.../Modules/GnbPcieInitLibV4/PciePortServicesV4.c | 4 +-
.../GnbPcieInitLibV4/PcieWrapperServicesV4.c | 6 +-
.../Modules/GnbPcieInitLibV5/PciePhyServicesV5.c | 2 +-
.../Modules/GnbPcieInitLibV5/PciePifServicesV5.c | 6 +-
.../Modules/GnbPcieInitLibV5/PciePortServicesV5.c | 4 +-
.../GnbPcieInitLibV5/PcieSiliconServicesV5.c | 6 +-
.../GnbPcieInitLibV5/PcieTopologyServicesV5.c | 4 +-
.../GnbPcieInitLibV5/PcieWrapperServicesV5.c | 4 +-
.../GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c | 14 +--
.../GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c | 44 +++----
.../Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c | 16 +--
.../Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c | 6 +-
.../f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c | 8 +-
.../f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c | 6 +-
.../Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c | 6 +-
.../f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c | 2 +-
.../f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c | 4 +-
.../Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c | 10 +-
.../agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c | 14 +--
src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c | 2 +-
.../amd/agesa/f16kb/Proc/HT/htInterface.c | 4 +-
.../amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c | 8 +-
.../amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c | 16 +--
.../agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c | 8 +-
src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c | 18 +--
src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c | 4 +-
src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c | 32 +++---
src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h | 4 +-
.../amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c | 4 +-
.../amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c | 4 +-
.../amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c | 8 +-
.../amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c | 8 +-
.../amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c | 4 +-
.../amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c | 4 +-
.../f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 2 +-
.../f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 8 +-
.../agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 2 +-
.../agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 4 +-
.../f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 2 +-
.../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 2 +-
.../Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 2 +-
.../Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c | 10 +-
.../Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c | 2 +-
.../Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c | 30 ++---
.../RDWR2DTRAINING/mfRdWr2DPatternGeneration.c | 14 +--
.../Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c | 36 +++---
.../amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c | 20 ++--
.../amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mdef.c | 10 +-
.../amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/minit.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c | 8 +-
.../agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c | 14 +--
.../amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c | 16 +--
.../agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c | 2 +-
.../agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c | 2 +-
.../agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Main/mmflow.c | 4 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c | 30 ++---
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c | 36 +++---
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c | 16 +--
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c | 22 ++--
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c | 4 +-
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 34 +++---
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c | 26 ++---
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c | 18 +--
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c | 38 +++---
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c | 54 ++++-----
.../amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c | 44 +++----
.../amd/agesa/f16kb/Proc/Mem/NB/mnflow.c | 10 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c | 22 ++--
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c | 42 +++----
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c | 24 ++--
.../amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c | 6 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c | 44 +++----
.../amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c | 8 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c | 12 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c | 22 ++--
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c | 20 ++--
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c | 10 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c | 16 +--
.../f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c | 26 ++---
.../agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c | 32 +++---
.../amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c | 46 ++++----
.../amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c | 4 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c | 8 +-
.../agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c | 6 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttml.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c | 4 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c | 4 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h | 2 +-
src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c | 8 +-
src/vendorcode/amd/cimx/rd890/amdAcpiLib.c | 8 +-
src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c | 4 +-
src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c | 20 ++--
src/vendorcode/amd/cimx/rd890/amdSbLib.c | 10 +-
src/vendorcode/amd/cimx/rd890/nbEventLog.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbHtInit.c | 16 +--
src/vendorcode/amd/cimx/rd890/nbHtInterface.c | 8 +-
src/vendorcode/amd/cimx/rd890/nbInit.c | 24 ++--
src/vendorcode/amd/cimx/rd890/nbInitializer.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbInterface.c | 18 +--
src/vendorcode/amd/cimx/rd890/nbIoApic.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbIommu.c | 58 +++++-----
src/vendorcode/amd/cimx/rd890/nbLib.c | 128 ++++++++++-----------
src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbMiscInit.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPcieAspm.c | 40 +++----
src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c | 8 +-
src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c | 12 +-
src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c | 52 ++++-----
src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c | 28 ++---
src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c | 14 +--
src/vendorcode/amd/cimx/rd890/nbPcieLib.c | 68 +++++------
src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPciePllControl.c | 6 +-
src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c | 22 ++--
src/vendorcode/amd/cimx/rd890/nbPcieSb.c | 14 +--
src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c | 20 ++--
src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c | 6 +-
src/vendorcode/amd/cimx/rd890/nbRecovery.c | 4 +-
.../amd/cimx/rd890/nbRecoveryInitializer.c | 2 +-
src/vendorcode/amd/cimx/sb800/AMDSBLIB.c | 6 +-
src/vendorcode/amd/cimx/sb800/ECLIB.c | 10 +-
src/vendorcode/amd/cimx/sb800/PMIO2LIB.c | 6 +-
src/vendorcode/amd/cimx/sb800/PMIOLIB.c | 6 +-
src/vendorcode/amd/cimx/sb800/SBMAIN.c | 12 +-
src/vendorcode/amd/cimx/sb800/SBPELIB.c | 6 +-
src/vendorcode/amd/cimx/sb900/EcLib.c | 10 +-
src/vendorcode/amd/cimx/sb900/Pmio2Lib.c | 6 +-
src/vendorcode/amd/cimx/sb900/PmioLib.c | 6 +-
src/vendorcode/amd/cimx/sb900/SbMain.c | 12 +-
src/vendorcode/amd/cimx/sb900/SbPeLib.c | 6 +-
src/vendorcode/amd/pi/00730F01/Lib/amdlib.c | 46 ++++----
2276 files changed, 10300 insertions(+), 10300 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
index 732438e..d06babd 100644
--- a/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
@@ -184,7 +184,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h
index 8c2dc93..13bdd93 100644
--- a/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h
+++ b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h
@@ -61,7 +61,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset Stub
*
@@ -80,7 +80,7 @@ GnbInitAtReset (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Stub
*
@@ -103,7 +103,7 @@ GnbInitAtEarly (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
@@ -122,7 +122,7 @@ GnbInitAtEnv (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
@@ -143,7 +143,7 @@ GnbInitAtPost (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
@@ -162,7 +162,7 @@ GnbInitAtMid (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
@@ -181,7 +181,7 @@ GnbInitAtLate (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AmdGnbRecovery
*
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
index 3516fcb..3c36285 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
@@ -77,7 +77,7 @@ STATIC BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c
index 5471cd1..2658120 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c
@@ -58,7 +58,7 @@
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -124,7 +124,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
index 7ab4176..36970f5 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
@@ -83,7 +83,7 @@ AgesaGetIdsData (
);
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -103,7 +103,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -128,7 +128,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -151,7 +151,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -176,7 +176,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -200,7 +200,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -224,7 +224,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -248,7 +248,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -271,7 +271,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -294,7 +294,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -317,7 +317,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -343,7 +343,7 @@ AgesaGetIdsData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
index b40617f..f1ab5fd 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
@@ -81,7 +81,7 @@
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -179,7 +179,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
diff --git a/src/vendorcode/amd/agesa/f10/Lib/amdlib.c b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c
index 0e8bdd1..de62f4b 100644
--- a/src/vendorcode/amd/agesa/f10/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c
@@ -456,7 +456,7 @@ StopHere (
while (x);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -493,7 +493,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -530,7 +530,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -560,7 +560,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -593,7 +593,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -630,7 +630,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -667,7 +667,7 @@ LibAmdMemWrite (
ASSERT (FALSE);
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -697,7 +697,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -730,7 +730,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -779,7 +779,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -828,7 +828,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -858,7 +858,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -891,7 +891,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -926,7 +926,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -959,7 +959,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -999,7 +999,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1073,7 +1073,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1099,7 +1099,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1127,7 +1127,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1163,7 +1163,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1213,7 +1213,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1235,7 +1235,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1279,7 +1279,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 17b0305..d042a0b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -98,7 +98,7 @@ PmNbCofVidInitWarmCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
@@ -213,7 +213,7 @@ F10PmNbCofVidInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
@@ -245,7 +245,7 @@ PmNbCofVidInitP0P1Core (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index df3ae93..076c8dc 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -87,7 +87,7 @@ PmNbPstateInitCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
@@ -150,7 +150,7 @@ F10PmNbPstateInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmNbPstateInit.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
index 8318530..285994d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable BL-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 90f0afe..fc02ea5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -72,7 +72,7 @@ STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 9cc87a9..b257382 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -70,7 +70,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
index d236a73..2141aab 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index a916fd5..6396a84 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -72,7 +72,7 @@ STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index e03cebe..2d788cc 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -70,7 +70,7 @@
extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
index f262323..09d7d81 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -77,7 +77,7 @@ F10InitializeHwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -97,7 +97,7 @@ F10IsHwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h CPU.
*
@@ -138,7 +138,7 @@ F10InitializeHwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 68d305d..8841ce0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision C processor.
*
@@ -150,7 +150,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision C processor.
*
@@ -236,7 +236,7 @@ F10CommonRevCGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -267,7 +267,7 @@ F10CommonRevCGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -320,7 +320,7 @@ F10CommonRevCGetNbFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -363,7 +363,7 @@ F10CommonRevCIsNbPstateEnabled (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index 79de653..bb79b3f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -74,7 +74,7 @@ STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index 5a58c32..6eea9f5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -70,7 +70,7 @@
CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
index d400807..737075a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
@@ -104,7 +104,7 @@ typedef struct {
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports HT Assist.
*
@@ -146,7 +146,7 @@ F10IsHtAssistSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the Probe filter feature.
*
@@ -195,7 +195,7 @@ F10HtAssistInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save the current settings of the scrubbers, and disabled them.
*
@@ -250,7 +250,7 @@ F10GetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restore the initial settings for the scrubbers.
*
@@ -298,7 +298,7 @@ F10SetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set MSR bits required for HT Assist on each core.
*
@@ -321,7 +321,7 @@ F10HookDisableCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Hook before the probe filter initialization sequence.
*
@@ -377,7 +377,7 @@ F10HookBeforeInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU is running in the optimal configuration.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
index 3343a10..f4a9055 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -88,7 +88,7 @@ IsDramScrubberEnabled (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -113,7 +113,7 @@ F10IsMsgBasedC1eSupported (
return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
@@ -206,7 +206,7 @@ F10InitializeMsgBasedC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable message-based C1e on a family 10h core.
*
@@ -239,7 +239,7 @@ F10InitializeMsgBasedC1eOnCore (
LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 93e5aa2..328afa9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -101,7 +101,7 @@ F10CommonRevDGetNumberOfCoresForBrandstring (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision D processor.
*
@@ -186,7 +186,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
F10CommonRevDSetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision D processor.
*
@@ -260,7 +260,7 @@ F10CommonRevDGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -287,7 +287,7 @@ F10CommonRevDGetNbCofVidUpdate (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -324,7 +324,7 @@ F10CommonRevDGetNbFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index a33a7db..faaf473 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -80,7 +80,7 @@ STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
index 52dcf0d..ff4202c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -88,7 +88,7 @@ CONST PF_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
NULL
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 9d0608b..1a91d73 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -78,7 +78,7 @@ GetF10HyMicroCodePatchesStruct (
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
index 98eb405..1ac9693 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -107,7 +107,7 @@ F10TransferApCoreNumber (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -144,7 +144,7 @@ F10SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -176,7 +176,7 @@ F10GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -210,7 +210,7 @@ F10GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the system AP core number in the AP's Mailbox.
*
@@ -248,7 +248,7 @@ F10SetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -275,7 +275,7 @@ F10GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Move the AP's core number from the mailbox to hardware.
*
@@ -312,7 +312,7 @@ F10TransferApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
index 8a4de65..d967e8f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -93,7 +93,7 @@ extern CONST UINT8 F10BrandIdString2TableCount;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -121,7 +121,7 @@ GetF10BrandIdString1 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 95d75e6..850398d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -94,7 +94,7 @@ CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
index 6507d6e..28c284e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 02040fb..e423813 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -76,7 +76,7 @@ F10Translate7BitVidTo6Bit (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetInfo
@@ -142,7 +142,7 @@ DmiF10GetInfo (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetVoltage
@@ -200,7 +200,7 @@ DmiF10GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMaxSpeed
@@ -381,7 +381,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* F10Translate7BitVidTo6Bit
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index f9e749c..5c0965f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -96,7 +96,7 @@ WaitForCpuFidAndDidToMatch (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -198,7 +198,7 @@ F10PmAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
@@ -367,7 +367,7 @@ F10PmAfterResetCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index 4940222..fa953de 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -84,7 +84,7 @@ updateCpuFeatureList (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function get features which CPU supports.
@@ -203,7 +203,7 @@ F10SaveFeatures (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function set features which All CPUs support.
@@ -310,7 +310,7 @@ F10WriteFeatures (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* cpuFeatureListNeedUpdate
@@ -351,7 +351,7 @@ cpuFeatureListNeedUpdate (
return flag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* updateCpuFeatureList
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index dc18320..88a879d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -90,7 +90,7 @@ F10PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the family 10h Processor-
* Systemboard Power Delivery Check.
@@ -261,7 +261,7 @@ F10PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -347,7 +347,7 @@ F10PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
index a710079..798a72b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -84,7 +84,7 @@ GetF10SysPmTable (
);
/* Family 10h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
{
IDS_INITIAL_F10_PM_STEP
@@ -134,7 +134,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
index df99340..281636d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -135,7 +135,7 @@ F10PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
@@ -289,7 +289,7 @@ F10CpuAmdPmPwrPlaneInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10CpuAmdPmPwrPlaneInit.
*
@@ -327,7 +327,7 @@ F10PmPwrPlaneInitPviCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded altvid voltage stabilization slam time for the executing
* family 10h core.
@@ -395,7 +395,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
index e8ba5a1..293873d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -73,7 +73,7 @@
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
index d7dcab1..c52b521 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
index 9eee85d..4828bca 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -129,7 +129,7 @@ F10SetRegisterForHtLinkTokenEntry (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated CPU
* Voltage Transitions.'
@@ -167,7 +167,7 @@ F10PmSwVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated NB
* Voltage Transitions.'
@@ -217,7 +217,7 @@ F10PmSwVoltageTransitionServerNb (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current VsSlamTime in microseconds.
*
@@ -258,7 +258,7 @@ F10GetCurrentVsTimeInUsecs (
*VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until VsSlamTime microseconds have expired.
*
@@ -279,7 +279,7 @@ F10WaitOutVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Code required to be run on every local core in order to perform
* the steps necessary for 'Software Initiated NB Voltage
@@ -324,7 +324,7 @@ F10SwVoltageTransitionServerNbCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
*
@@ -408,7 +408,7 @@ F10ProgramVSSlamTimeOnSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded voltage stabilization slam time for the executing
* family 10h core.
@@ -469,7 +469,7 @@ F10GetSlamTimeEncoding (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculates the power in milliWatts of the desired P-state.
*
@@ -568,7 +568,7 @@ F10GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculates the frequency in megahertz of the desired P-state.
*
@@ -627,7 +627,7 @@ F10GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -655,7 +655,7 @@ F10DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -692,7 +692,7 @@ F10TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -729,7 +729,7 @@ F10GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -756,7 +756,7 @@ F10GetNbFrequency (
return (AGESA_UNSUPPORTED);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -877,7 +877,7 @@ F10LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
@@ -955,7 +955,7 @@ F10GetFrequencyXlatRegInfo (
return AGESA_ERROR;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function sets the Pstate MSR to each APs base on Pstate Buffer.
*
@@ -1166,7 +1166,7 @@ F10GetPllValueInTime (
} else
*PllLockTimePtr = 0;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Pstate Transition Latency.
*
@@ -1277,7 +1277,7 @@ F10GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate register Informations.
*
@@ -1327,7 +1327,7 @@ F10GetPstateRegisterInfo (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate max state.
*
@@ -1360,7 +1360,7 @@ F10GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -1384,7 +1384,7 @@ F10GetPlatformTypeSpecificInfo (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the given HT link.
*
@@ -1462,7 +1462,7 @@ F10GetHtLinkFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -1614,7 +1614,7 @@ F10DoesLinkHaveHtPhyFeats (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
@@ -1681,7 +1681,7 @@ F10SetHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the HT Link Token Count registers (F3X1[54,50,4C,48]).
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
index d88ad33..4730a1b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -95,7 +95,7 @@ AMD_WHEA_INIT_DATA F10WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
index 74283bb..7ff91da 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
@@ -79,7 +79,7 @@
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The contents of the mailbox registers should always be preserved.
*
@@ -99,7 +99,7 @@ IsPreserveAroundMailboxEnabled (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
index b2bf667..2af560f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
@@ -83,7 +83,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -125,7 +125,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -160,7 +160,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
index e6a0cb0..ce5babe 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
@@ -116,7 +116,7 @@ typedef struct _CST_BODY_STRUCT {
} CST_BODY_STRUCT;
#define CST_BODY_SIZE 33
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -137,7 +137,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index 6d0db2a..5bafe49 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -89,7 +89,7 @@ extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -109,7 +109,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
index 10f4f5c..7367940 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
@@ -122,7 +122,7 @@ CalculateOccupyExeCache (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -381,7 +381,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -468,7 +468,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -493,7 +493,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
index d5ec4b6..70d01db 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -90,7 +90,7 @@ extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -118,7 +118,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
index efab53c..e7f5251 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
@@ -110,7 +110,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -137,7 +137,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -163,7 +163,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -347,7 +347,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -569,7 +569,7 @@ GetType4Type7Info (
}
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -604,7 +604,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -625,7 +625,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -648,7 +648,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
index 57491a8..5db60db 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -108,7 +108,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -184,7 +184,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -209,7 +209,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -234,7 +234,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
index 28c24d6..17451e5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
@@ -172,7 +172,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -191,7 +191,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
index 30e6e0b..c91f1e4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
@@ -89,7 +89,7 @@
extern CPU_FAMILY_SUPPORT_TABLE HtAssistFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should HT Assist be enabled
*
@@ -142,7 +142,7 @@ IsHtAssistEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the HT Assist feature.
*
@@ -272,7 +272,7 @@ InitializeHtAssistFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Disable all the caches on current core.
@@ -305,7 +305,7 @@ DisableAllCaches (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Enable all the caches on current core.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
index 7c86833..0774c68 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
@@ -63,7 +63,7 @@ typedef struct _HT_ASSIST_FAMILY_SERVICES HT_ASSIST_FAMILY_SERVICES;
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -84,7 +84,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before HT Assist is initialized.
*
@@ -102,7 +102,7 @@ typedef VOID F_HT_ASSIST_BEFORE_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_BEFORE_INIT *PF_HT_ASSIST_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -118,7 +118,7 @@ typedef VOID F_HT_ASSIST_DISABLE_CACHE (
/// Reference to a Method.
typedef F_HT_ASSIST_DISABLE_CACHE *PF_HT_ASSIST_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -137,7 +137,7 @@ typedef VOID F_HT_ASSIST_ENABLE_CACHE (
typedef F_HT_ASSIST_ENABLE_CACHE *PF_HT_ASSIST_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -155,7 +155,7 @@ typedef VOID F_HT_ASSIST_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -173,7 +173,7 @@ typedef VOID F_HT_ASSIST_AFTER_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_AFTER_INIT *PF_HT_ASSIST_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -193,7 +193,7 @@ typedef VOID F_HT_ASSIST_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_HT_ASSIST_GET_L3_SCRUB_CTRL *PF_HT_ASSIST_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -214,7 +214,7 @@ typedef VOID F_HT_ASSIST_SET_L3_SCRUB_CTRL (
typedef F_HT_ASSIST_SET_L3_SCRUB_CTRL *PF_HT_ASSIST_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
index 160d819..6074b2e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
@@ -76,7 +76,7 @@
*/
extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -118,7 +118,7 @@ IsHwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
index 9f7b608..a47a720 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
@@ -58,7 +58,7 @@ typedef struct _HW_C1E_FAMILY_SERVICES HW_C1E_FAMILY_SERVICES;
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if hardware C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
index 7df9c7c..6f6f754 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -84,7 +84,7 @@ EnableMsgC1eOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -161,7 +161,7 @@ IsMsgBasedC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Message-based C1e
*
@@ -197,7 +197,7 @@ InitializeMsgBasedC1eFeature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable message-based C1e on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
index 610e343..b085293 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -58,7 +58,7 @@ typedef struct _MSG_BASED_C1E_FAMILY_SERVICES MSG_BASED_C1E_FAMILY_SERVICES;
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
index 169a94f..9c91c2a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -952,7 +952,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
index b3b08d4..eca0b81 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
@@ -58,7 +58,7 @@ typedef struct _PSTATE_CPU_FAMILY_SERVICES PSTATE_CPU_FAMILY_SERVICES;
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
index fc946c5..9296593 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
@@ -125,7 +125,7 @@ ReleaseSlitBuffer (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -149,7 +149,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -174,7 +174,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -292,7 +292,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -320,7 +320,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -341,7 +341,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
index bdb498b..0df8733 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
@@ -141,7 +141,7 @@ STATIC
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -164,7 +164,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -187,7 +187,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -296,7 +296,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -507,7 +507,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -543,7 +543,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
index a9070ff..7e5117c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
@@ -92,7 +92,7 @@ GetAcpiWheaMain (
IN OUT VOID **WheaCmcPtr
);
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -114,7 +114,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -140,7 +140,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -236,7 +236,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c
index 65e465b..fd44d0a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c
@@ -146,7 +146,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -179,7 +179,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -276,7 +276,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -352,7 +352,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -431,7 +431,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -474,7 +474,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -520,7 +520,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -604,7 +604,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -665,7 +665,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -725,7 +725,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -815,7 +815,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -908,7 +908,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -961,7 +961,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1017,7 +1017,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1038,7 +1038,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1062,7 +1062,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1087,7 +1087,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1111,7 +1111,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1135,7 +1135,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c
index 3c998ad..6dd57b6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c
@@ -87,7 +87,7 @@ SetRegistersFromTablesAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -147,7 +147,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -178,7 +178,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -246,7 +246,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -277,7 +277,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -322,7 +322,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Errata Workaround Register Entry.
*
@@ -351,7 +351,7 @@ SetRegisterForErrataWorkaroundEntry (
Entry->ErrataEntry.DoAction (Entry->ErrataEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Finds the HT link capability set for a particular node/link.
*
@@ -409,7 +409,7 @@ FindHtHostCapability (
return Result ;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers using BKDG values.
*
@@ -472,7 +472,7 @@ SetRegisterForHtPhyEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program a range of HT Phy PCI registers using BKDG values.
*
@@ -545,7 +545,7 @@ SetRegisterForHtPhyRangeEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -566,7 +566,7 @@ IsDeemphasisLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, for the current node and real link number.
*
@@ -615,7 +615,7 @@ LookupPackageLink (
return PackageLink;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the platform's specified deemphasis levels for the current link.
*
@@ -671,7 +671,7 @@ GetLinkDeemphasis (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program Deemphasis registers using BKDG values, for the platform specified levels.
*
@@ -750,7 +750,7 @@ SetRegisterForDeemphasisEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers which have complex frequency dependencies.
*
@@ -827,7 +827,7 @@ SetRegisterForHtPhyFreqEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -865,7 +865,7 @@ SetRegisterForPerformanceProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Phy Performance Profile Register Entry.
*
@@ -900,7 +900,7 @@ SetRegisterForHtPhyProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host PCI Register Entry.
*
@@ -971,7 +971,7 @@ SetRegisterForHtHostEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -1012,7 +1012,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -1053,7 +1053,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Token Counts PCI Register Entry.
*
@@ -1097,7 +1097,7 @@ SetRegisterForTokenPciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link Feature PCI Register Entry.
*
@@ -1176,7 +1176,7 @@ SetRegisterForHtFeaturePciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link PCI Register Entry.
*
@@ -1247,7 +1247,7 @@ SetRegisterForHtLinkPciEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -1341,7 +1341,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -1389,7 +1389,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -1433,7 +1433,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -1465,7 +1465,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -1548,7 +1548,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
index 9a30f7e..d4e7e93 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
@@ -120,11 +120,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -159,11 +159,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -586,11 +586,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -829,11 +829,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -880,11 +880,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -911,11 +911,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -957,11 +957,11 @@ typedef struct {
ERRATA_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts errata workaround data initializer.
} ERRATA_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c
index c2d5f49..5fca2f8 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c
@@ -235,7 +235,7 @@ LocalApicInitializationAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -327,7 +327,7 @@ LocalApicInitialization (
CurrentNodeNum, CurrentCore, TempVar_a >> APIC20_ApicId);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -351,7 +351,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -493,7 +493,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -524,7 +524,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -549,7 +549,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -575,7 +575,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -596,7 +596,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -699,7 +699,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -753,7 +753,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -820,7 +820,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -865,7 +865,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -940,7 +940,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -1018,7 +1018,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1163,7 +1163,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1183,7 +1183,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1235,7 +1235,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1264,7 +1264,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1295,7 +1295,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1317,7 +1317,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1350,7 +1350,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1380,7 +1380,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1424,7 +1424,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c
index 015e288..e9987d5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c
@@ -70,7 +70,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -142,7 +142,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c
index 45e0f5c..f15759e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c
@@ -87,7 +87,7 @@ SetBrandIdRegistersAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
@@ -283,7 +283,7 @@ SetBrandIdRegisters (
HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c
index 7580ac0..7dfbc4e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c
@@ -84,7 +84,7 @@ McaInitializationAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
@@ -107,7 +107,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -255,7 +255,7 @@ AmdCpuEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -300,7 +300,7 @@ McaInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -322,7 +322,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c
index b5e0cf6..46f7a1d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c
@@ -91,7 +91,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -127,7 +127,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -164,7 +164,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -232,7 +232,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -286,7 +286,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -348,7 +348,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c
index 8fc68dc..211c1e6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c
@@ -125,7 +125,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -164,7 +164,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -187,7 +187,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -259,7 +259,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -286,7 +286,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -312,7 +312,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -335,7 +335,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -360,7 +360,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -387,7 +387,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -411,7 +411,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -454,7 +454,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
index 5f7bea5..4f584f4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
@@ -826,7 +826,7 @@ typedef VOID F_GET_HT_LINK_FEATURES (
/// Reference to a Method.
typedef F_GET_HT_LINK_FEATURES *PF_GET_HT_LINK_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c
index 04fa437..ea8d945 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c
@@ -178,7 +178,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -222,7 +222,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -266,7 +266,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -308,7 +308,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -327,7 +327,7 @@ GetPlatformNumberOfSockets ()
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -345,7 +345,7 @@ GetPlatformNumberOfModules ()
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -388,7 +388,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -430,7 +430,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -474,7 +474,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -517,7 +517,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -539,7 +539,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
@@ -578,7 +578,7 @@ ModifyCurrentSocketPci (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -600,7 +600,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -630,7 +630,7 @@ GetActiveCoresInCurrentModule (
return ProcessorCoreCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -669,7 +669,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -715,7 +715,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -754,7 +754,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -777,7 +777,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -811,7 +811,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -850,7 +850,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -893,7 +893,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -927,7 +927,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -955,7 +955,7 @@ GetSystemDegree (
return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -985,7 +985,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1013,7 +1013,7 @@ IsBsp (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c
index dabbe0a..f6c72ea 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c
@@ -84,7 +84,7 @@ CONST PF_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
NULL
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c
index b71ac6b..53a5e21 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c
@@ -75,7 +75,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -97,7 +97,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -140,7 +140,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -171,7 +171,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -226,7 +226,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c
index cf13372..650ec86 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c
@@ -111,7 +111,7 @@ LoadMicrocodePatchAtEarly (
);
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -170,7 +170,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -214,7 +214,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -274,7 +274,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -384,7 +384,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -413,7 +413,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c
index ad2d26d..746bfa0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c
@@ -106,7 +106,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -170,7 +170,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -197,7 +197,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -224,7 +224,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -340,7 +340,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -380,7 +380,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
@@ -401,7 +401,7 @@ FinalizeAtPost (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection.
*
@@ -427,7 +427,7 @@ SetTscFreqSel (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection to all cores.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c
index c5d3149..4bd1b94 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c
@@ -96,7 +96,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -148,7 +148,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -187,7 +187,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -214,7 +214,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c
index f20f00c..7c4a005 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -81,7 +81,7 @@ GetNextEvent (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -126,7 +126,7 @@ RunCodeOnAllSystemCore0sMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -166,7 +166,7 @@ GetNumberOfSystemPmStepsPtrMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the frequency that the northbridges must run.
*
@@ -233,7 +233,7 @@ GetSystemNbCofMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -282,7 +282,7 @@ GetSystemNbCofVidUpdateMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -368,7 +368,7 @@ GetEarlyPmErrorsMulti (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to return the next event log entry to the BSC.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
index 1af564e..3deca1a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -96,7 +96,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -121,7 +121,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -153,7 +153,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -182,7 +182,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
index 03c5bac..890bd32 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -95,7 +95,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -126,7 +126,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
index 37b026c..bd0d26f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
@@ -81,7 +81,7 @@
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -176,7 +176,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -313,7 +313,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -460,7 +460,7 @@ HeapDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -551,7 +551,7 @@ HeapLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
index 68bfce4..15f661b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
@@ -85,7 +85,7 @@ EXECUTION_CACHE_REGION InitExeCacheMap[] =
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -105,7 +105,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -133,7 +133,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -168,7 +168,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
index 92bfc82..e2323b9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
@@ -103,7 +103,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
index 78d044c..aebd01a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
@@ -79,7 +79,7 @@ extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user confi
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -171,7 +171,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
index 61c8147..a15cf60 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
@@ -101,7 +101,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
index 507530c..f4aa985 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
@@ -82,7 +82,7 @@
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -187,7 +187,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
index ba3ec3a..aebb9e7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
@@ -66,7 +66,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
@@ -121,7 +121,7 @@ AmdInitRecovery (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initialize defaults and options for Amd Init Reset.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
index 89ec16d..276f034 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
@@ -80,7 +80,7 @@ EXECUTION_CACHE_REGION InitResetExeCacheMap[] =
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -108,7 +108,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -176,7 +176,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
index a3a8e74..4da5c11 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
@@ -81,7 +81,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -151,7 +151,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -182,7 +182,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
index 27fd6f8..45b0b1b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
@@ -73,7 +73,7 @@
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -120,7 +120,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
index 4238d00..abea87b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
@@ -81,7 +81,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -149,7 +149,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -181,7 +181,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
index fd25759..b6a1d89 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
@@ -94,7 +94,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -266,7 +266,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -298,7 +298,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -344,7 +344,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
index ee15e2d..e8eff10 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
@@ -68,7 +68,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
index 52e82c4..8b696b6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
@@ -61,7 +61,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -73,7 +73,7 @@ CommonReturnFalse (VOID)
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -86,7 +86,7 @@ CommonReturnZero8 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -99,7 +99,7 @@ CommonReturnZero32 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -112,7 +112,7 @@ CommonReturnZero64 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -124,7 +124,7 @@ CommonReturnNULL (VOID)
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -137,7 +137,7 @@ CommonReturnAgesaSuccess (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -147,7 +147,7 @@ CommonVoid (VOID)
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
index baa5fa3..c5e670d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
@@ -71,7 +71,7 @@ extern CONST UINTN InitializerCount;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -202,7 +202,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
index de9ad2a..eee0b26 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
@@ -79,7 +79,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -96,7 +96,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -113,7 +113,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -138,7 +138,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
index 8d24b7a..629336f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
@@ -68,7 +68,7 @@ extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -84,7 +84,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -100,7 +100,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -127,7 +127,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -181,7 +181,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -209,7 +209,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -265,7 +265,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -330,7 +330,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -397,7 +397,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
index b98a25c..a1c7686 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return whether the current configuration exceeds the capability.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
index 01a8cb8..6bc8fc0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -66,7 +66,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable config access to a non-coherent chain for the given bus range.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
index 7f62c09..c1d96b5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -65,7 +65,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
@@ -136,7 +136,7 @@ Fam10NorthBridgeFreqMask (
return (Supported);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
index 4904c1b..5d473bb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
@@ -103,7 +103,7 @@ typedef union {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the traffic distribution register for the Links provided.
*
@@ -150,7 +150,7 @@ Fam10WriteTrafficDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write a link pair to the link pair distribution and fixups.
*
@@ -234,7 +234,7 @@ Fam10WriteLinkPairDistribution (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
@@ -315,7 +315,7 @@ Fam10BufferOptimizations (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
index d6cea1f..b630180 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -119,7 +119,7 @@ Fam10GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -172,7 +172,7 @@ Fam10RevDGetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the next link for iterating over the links on a node in the correct order.
*
@@ -263,7 +263,7 @@ Fam10GetNextLink (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Info about Module Type of this northbridge
*
@@ -303,7 +303,7 @@ Fam10GetModuleInfo (
*Module = (UINT8) IntNodeNum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -330,7 +330,7 @@ Fam10GetSocket (
return (Node);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -366,7 +366,7 @@ Fam10RevDGetSocket (
return ((UINT8) Socket);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post info to AP cores via a mailbox.
*
@@ -405,7 +405,7 @@ Fam10PostMailbox (
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrieve info from a node's mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
index ca650ae..a32f48a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -137,7 +137,7 @@ typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
*** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
***************************************************************************/
-/*-----------------------------------------------------------------------------------*/
+
/**
* Ensure a request / response route from target Node to bsp.
*
@@ -183,7 +183,7 @@ routeFromBSP (
State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test Compatibility of a new node, and handle failure.
*
@@ -257,7 +257,7 @@ CheckCompatible (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check the system MP capability with a new node and handle any failure.
*
@@ -311,7 +311,7 @@ CheckCapable (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make all the tests needed to determine if a link should be added to the system data structure.
*
@@ -376,7 +376,7 @@ IsLinkToAdd (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Explore for a new node over a link, handling whatever is found.
*
@@ -476,7 +476,7 @@ ExploreNode (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process all the saved new node info for the current processor.
*
@@ -533,7 +533,7 @@ ProcessSavedNodeInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create and add a new link to the system data structure.
*
@@ -581,7 +581,7 @@ AddLinkToSystem (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Start discovery from a new node.
*
@@ -626,7 +626,7 @@ StartFromANewNode (
State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Back up from exploring a one-deep internal node.
*
@@ -653,7 +653,7 @@ BackUpFromANode (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dynamically Discover all coherent devices in the system.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
index 6095298..6696918 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
@@ -96,7 +96,7 @@
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
index 35f717a..f71f8e4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
@@ -98,7 +98,7 @@
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process a non-coherent Link.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
index 8353316..f5000b3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
@@ -104,7 +104,7 @@ extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Given the bits set in the register field, return the width it represents.
*
@@ -159,7 +159,7 @@ ConvertBitsToWidth (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Translate a desired width setting to the bits to set in the register field.
*
@@ -213,7 +213,7 @@ ConvertWidthToBits (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Access HT Link Control Register.
*
@@ -261,7 +261,7 @@ SetHtControlRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set HT Frequency register for IO Devices
*
@@ -308,7 +308,7 @@ SetHtIoFrequencyRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -405,7 +405,7 @@ GatherLinkData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Links.
*
@@ -545,7 +545,7 @@ SelectOptimalWidthAndFrequency (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
@@ -728,7 +728,7 @@ SetLinkData (
}
}
-/*------------------------------------------------------------------------------------------*/
+
/**
* Find a specific HT capability type.
*
@@ -794,7 +794,7 @@ DoesDeviceHaveHtSubtypeCap (
return IsFound;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
index 46dad6c..511c658 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
@@ -102,7 +102,7 @@ typedef struct {
*** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link on source Node which connects to target Node
*
@@ -141,7 +141,7 @@ FindLinkToNode (
return TargetLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is graphA isomorphic to graphB?
*
@@ -210,7 +210,7 @@ IsIsomorphic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Topology List iterator context to the Beginning and provide the first topology.
*
@@ -242,7 +242,7 @@ BeginTopologies (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through available topologies.
*
@@ -279,7 +279,7 @@ GetNextTopology (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
@@ -413,7 +413,7 @@ LookupComputeAndLoadRoutingTables (
State->Fabric->MatchedTopology = Selected;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a Hop Count Table for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
index 6824c4b..7f23a98 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
@@ -120,7 +120,7 @@ STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
index 9bf7122..c54fd05 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -93,7 +93,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Identify Links which can have traffic distribution.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
index 06c69b4..44a9e62 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
@@ -55,7 +55,7 @@
#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-/*-------------------------------------------------------------------------------------*/
+
/**
* Apply an IDS port override to the desired HT link.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
index 015ffcf..55ca7ba 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
@@ -83,7 +83,7 @@
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Establish a Temporary route from one Node to another.
*
@@ -124,7 +124,7 @@ WriteRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Modifies the NodeID register on the target Node
*
@@ -153,7 +153,7 @@ WriteNodeID (
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the Default Link
*
@@ -192,7 +192,7 @@ ReadDefaultLink (
return (UINT8)DefaultLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables on for a given Node
*
@@ -219,7 +219,7 @@ EnableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables off for a given Node
*
@@ -246,7 +246,7 @@ DisableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is coherent, connected, and ready
*
@@ -286,7 +286,7 @@ VerifyLinkIsCoherent (
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the token stored in the scratchpad register field.
*
@@ -325,7 +325,7 @@ ReadToken (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the token stored in the scratchpad register
*
@@ -361,7 +361,7 @@ WriteToken (
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Full Routing Table Register initialization
*
@@ -416,7 +416,7 @@ WriteFullRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
@@ -440,7 +440,7 @@ IsIllegalTypeMix (
return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fix (hopefully) exceptional conditions.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
index cfe2d30..706a4b5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -71,7 +71,7 @@
*** Northbridge access routines ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link to the Southbridge
*
@@ -97,7 +97,7 @@ ReadSouthbridgeLink (
return (UINT8)Temp;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is non-coherent, connected, and ready
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
index fef3047..c93a9dd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
@@ -74,7 +74,7 @@
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -117,7 +117,7 @@ GatherLinkFeatures (
ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
@@ -148,7 +148,7 @@ SetLinkRegang (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for Unit Id Clumping.
@@ -184,7 +184,7 @@ SetLinkUnitIdClumping (
LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link frequency.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
index 1419f14..bbcc217 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
@@ -70,7 +70,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the HT Host capability base PCI config address for a Link.
*
@@ -108,7 +108,7 @@ MakeLinkBase (
return LinkBase;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
@@ -180,7 +180,7 @@ ReadTrueLinkFailStatus (
return (BOOLEAN) ((After != 0) || (Unconnected != 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores and Nodes to the Node
*
@@ -220,7 +220,7 @@ SetTotalNodesAndCores (
LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -251,7 +251,7 @@ GetNodeCount (
return ((UINT8) (++Temp));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
@@ -279,7 +279,7 @@ LimitNodes (
LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, given the node and real link number.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
index 15ad4a9..467813b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
@@ -84,7 +84,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
index 5bc51ab..fe4b1cd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
@@ -52,7 +52,7 @@
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the AGESA built in topology list
*
@@ -70,7 +70,7 @@ GetAmdTopolist (
*List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the number of Nodes in the compressed graph
*
@@ -86,7 +86,7 @@ GraphHowManyNodes (
return Graph[0];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns true if NodeA is directly connected to NodeB, false otherwise
*
@@ -113,7 +113,7 @@ GraphIsAdjacent (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route responses targeted at NodeB.
*
@@ -141,7 +141,7 @@ GraphGetRsp (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route requests targeted at NodeB.
*
@@ -169,7 +169,7 @@ GraphGetReq (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns a bit vector of Nodes that NodeA should forward a broadcast from
* NodeB towards
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
index 1726d1c..30f62df 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
@@ -184,7 +184,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -209,7 +209,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
index 983ff33..af8a926 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
@@ -93,8 +93,8 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -164,7 +164,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -230,7 +230,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
index 3eb41ea..3abe104 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
@@ -98,7 +98,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -118,7 +118,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -198,7 +198,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -226,7 +226,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -277,7 +277,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -335,7 +335,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -435,7 +435,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -473,7 +473,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
index 6ba128e..e1164df 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
@@ -87,7 +87,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -149,7 +149,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -266,7 +266,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -325,7 +325,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
index 50a8b94..690ad70 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
@@ -78,7 +78,7 @@
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -151,7 +151,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -186,7 +186,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -256,7 +256,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -304,7 +304,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -343,7 +343,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -374,7 +374,7 @@ Tuning (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -407,7 +407,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -435,7 +435,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
index b885bf2..0e3d73b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
@@ -146,7 +146,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -184,7 +184,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
index 04264fa..585d8f1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -122,7 +122,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -154,7 +154,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -189,7 +189,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -224,7 +224,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -256,7 +256,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -297,7 +297,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -335,7 +335,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -370,7 +370,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -405,7 +405,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -440,7 +440,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -479,7 +479,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -518,7 +518,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -547,7 +547,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -582,7 +582,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -620,7 +620,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
index 9cb3fb6..6601372 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
@@ -47,7 +47,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -167,7 +167,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
index 4b1aa3e..d923e8f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
@@ -351,7 +351,7 @@ IdsGetNumPstatesFamCommon (
return pstatesnum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c
index 9da5981..ec774cf 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c
@@ -56,7 +56,7 @@
extern BUILD_OPT_CFG UserOptions;
typedef struct _IDS_CONSOLE IDS_CONSOLE;
-/*--------------------------------------------------------------------------------------*/
+
/**
* IDS back-end code for AGESA_TESTPOINT
*
@@ -64,7 +64,7 @@ typedef struct _IDS_CONSOLE IDS_CONSOLE;
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
-/*--------------------------------------------------------------------------------------*/
+
VOID
IdsAgesaTestPoint (
IN AGESA_TP TestPoint,
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
index 2c455c9..def03bb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
@@ -104,7 +104,7 @@ STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
index 107a430..6d15048 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -101,7 +101,7 @@ STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
index b86c1df..afbb04f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
@@ -93,7 +93,7 @@ STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR2 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
index 41ca0ea..8c34816 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
@@ -95,7 +95,7 @@ STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
index 79f2436..c6861c9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
@@ -93,7 +93,7 @@ STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
index 75229a5..6e73a39 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
@@ -106,7 +106,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR2 L1 system
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
index 1035df9..d8952a7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
@@ -105,7 +105,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
index ab839f4..8ce3228 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
@@ -93,7 +93,7 @@ STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
index 877a8b3..21f585a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
@@ -104,7 +104,7 @@ STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
index 2572a1e..36ec312 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
@@ -101,7 +101,7 @@ STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
index ccbe3f9..7492c29 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
@@ -95,7 +95,7 @@ STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
index 4f26f7f..1995fc9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
@@ -93,7 +93,7 @@ STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
index ef0e849..2eed02c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
@@ -78,7 +78,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -102,7 +102,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
index 7b44248..baeccf4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveChannels:
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
index db76b8a..5a905ab 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -101,7 +101,7 @@ MemFUndoInterleaveBanks (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -137,7 +137,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -196,7 +196,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -284,7 +284,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
index 61f6b7c..45cbba4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
@@ -93,7 +93,7 @@ MemFDMISupport2 (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -355,7 +355,7 @@ MemFDMISupport3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
index 5d08b5c..bcb80a7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
@@ -102,7 +102,7 @@ MemFCheckECC (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -164,7 +164,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -277,7 +277,7 @@ InitECCOverriedeStruct (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
index e3be798..cde2d94 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
@@ -88,7 +88,7 @@ MemFInitEMP (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -152,7 +152,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 68891c7..a9a54b1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -87,7 +87,7 @@ MemFRASExcludeDIMM (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 3beae2b..23ed983 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -110,7 +110,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -202,7 +202,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -462,7 +462,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -494,7 +494,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index f4df3a8..6a2a122 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveRegion:
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index 155b855..ceecfca 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -87,7 +87,7 @@
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index af31a47..31fb0a3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -78,7 +78,7 @@
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -108,7 +108,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
index c57a74b..d472dff 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -90,7 +90,7 @@ MemFCheckInterleaveNodes (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform a check to see if node interleaving can be enabled on each node.
@@ -127,7 +127,7 @@ MemFCheckInterleaveNodes (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Applies Node memory interleaving for each node.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index 270a83b..8e00bc9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -83,7 +83,7 @@
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
index f82dfbe..558c1a3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -84,7 +84,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Enable online spare on current node if it is requested.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index e07c0ca..86acce2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -66,7 +66,7 @@
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index ba32b78..1915167 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -59,7 +59,7 @@
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
index 8a674c3..bcbaebf 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
@@ -91,7 +91,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -148,7 +148,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -190,7 +190,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -289,7 +289,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -351,7 +351,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -412,7 +412,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -473,7 +473,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -534,7 +534,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -601,7 +601,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -720,7 +720,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c
index 31cf163..d9aa133 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c
@@ -88,7 +88,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c
index 30bc840..d0598ac 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c
@@ -88,7 +88,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c
index 94eff04..a2febfb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c
@@ -88,7 +88,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c
index f829abb..d077901 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c
@@ -93,7 +93,7 @@ MemMFlowHy (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c
index 05d8778..ca1a698 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c
@@ -78,7 +78,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
index 96a8a74..7101e6b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
@@ -88,7 +88,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c
index b214be4..bad166d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c
@@ -86,7 +86,7 @@ extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c
index 8474d49..2da677d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c
@@ -90,7 +90,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -125,7 +125,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c
index 0980c3c..8c9db8c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c
@@ -152,7 +152,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -426,7 +426,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -475,7 +475,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -514,7 +514,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -553,7 +553,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -597,7 +597,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -655,7 +655,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c
index d5b7cc9..330d430 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c
@@ -73,7 +73,7 @@ MemMEcc (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c
index 1e42598..29a1459 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c
@@ -72,7 +72,7 @@ MemMRASExcludeDIMM (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c
index 0dc8537..8dd9533 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c
@@ -70,7 +70,7 @@ MemMLvDdr3 (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c
index d00c838..171578d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c
@@ -69,7 +69,7 @@ MemMMctMemClr (
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c
index 620aba2..4d8c2ea 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c
@@ -99,7 +99,7 @@ MemMCreateS3NbBlock (
*/
extern MEM_NB_SUPPORT memNBInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -210,7 +210,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -260,7 +260,7 @@ MemMContextRestore (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices that contains DQS timings
*
@@ -423,7 +423,7 @@ MemMRestoreDqsTimings (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function filters out other settings and only restores DQS timings.
@@ -529,7 +529,7 @@ MemMSetCSRNb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c
index eecca69..c672883 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c
@@ -70,7 +70,7 @@ MemMInterleaveNodes (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c
index fa191e2..84367cb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c
@@ -68,7 +68,7 @@ MemMOnlineSpare (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c
index 2331b6a..ac86456 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c
@@ -81,7 +81,7 @@ BOOLEAN
MemMParallelTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c
index 7dc1560..a53c247 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c
@@ -72,7 +72,7 @@ MemMStandardTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
index d4a7c9b..f49fb34 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
@@ -88,7 +88,7 @@ BOOLEAN
MemMUmaAlloc (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c
index 20c264d..c66d6f6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c
@@ -101,7 +101,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -258,7 +258,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c
index 31856ea..e5a55fd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c
@@ -159,7 +159,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -251,7 +251,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -275,7 +275,7 @@ MemUProcIOClFlush (
MemUResetTargetWTIO (MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Compares two array of bytes.
@@ -317,7 +317,7 @@ MemUCompareTestPattern (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -343,7 +343,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -364,7 +364,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -392,7 +392,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -424,7 +424,7 @@ MemUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -464,7 +464,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -502,7 +502,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -543,7 +543,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -581,7 +581,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -620,7 +620,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -658,7 +658,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c
index 719ed94..b6799e3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -77,7 +77,7 @@ MemConstructRemoteNBBlockC32 (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c
index 3af36a5..2278d70 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c
@@ -456,7 +456,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -533,7 +533,7 @@ MemS3ResumeConstructNBBlockC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -584,7 +584,7 @@ MemNS3GetRegLstPtrC32 (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -613,7 +613,7 @@ MemNS3GetDeviceRegLstC32 (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -667,7 +667,7 @@ MemNS3SetSpecialPCIRegC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
index f232fdf..8ad44e6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
@@ -95,7 +95,7 @@
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -221,7 +221,7 @@ MemConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -337,7 +337,7 @@ MemNInitNBDataC32 (
NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -406,7 +406,7 @@ MemNInitDefaultsC32 (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -429,7 +429,7 @@ MemNWritePatternC32 (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c
index 4960e36..c9b6115 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c
@@ -93,7 +93,7 @@ extern BUILD_OPT_CFG UserOptions;
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -235,7 +235,7 @@ MemNAutoConfigC32 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -264,7 +264,7 @@ MemNSendMrsCmdC32 (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -291,7 +291,7 @@ MemNBeforeDramInitC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -325,7 +325,7 @@ MemNEnDLLShutDownC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -356,7 +356,7 @@ MemNBeforePlatformSpecC32 (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Force LvDimm voltage to 1.5V for D0 part
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
index 8b50978..da41cdd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
@@ -82,7 +82,7 @@
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c
index 5dd104f..6d30e07 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c
@@ -88,7 +88,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c
index b600e42..796f847 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c
@@ -86,7 +86,7 @@
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c
index add84a5..4fb5723 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c
@@ -95,7 +95,7 @@ MemNGetODTDelaysC32 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -134,7 +134,7 @@ MemNOtherTimingC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -158,7 +158,7 @@ MemNSetOtherTimingC32 (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -202,7 +202,7 @@ MemNGetODTDelaysC32 (
ODTDelays += Ld;
return ODTDelays;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c
index d453204..9d54bd0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c
@@ -88,10 +88,10 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -160,7 +160,7 @@ MemNInitPhyCompC32 (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c
index 6469da7..c857211 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c
@@ -87,7 +87,7 @@
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -113,7 +113,7 @@ MemNIsIdSupportedC32 (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -137,7 +137,7 @@ MemNGetSocketRelativeChannelC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -261,7 +261,7 @@ MemNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c
index df3cd03..2d9d330 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -80,7 +80,7 @@ MemConstructRemoteNBBlockDA (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c
index 36644ad..a26821c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c
@@ -474,7 +474,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -551,7 +551,7 @@ MemS3ResumeConstructNBBlockDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -602,7 +602,7 @@ MemNS3GetRegLstPtrDA (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -630,7 +630,7 @@ MemNS3GetDeviceRegLstDA (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -684,7 +684,7 @@ MemNS3SetSpecialPCIRegDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
index 623f530..54ccd53 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
@@ -99,7 +99,7 @@
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -222,7 +222,7 @@ MemConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -345,7 +345,7 @@ MemNInitNBDataDA (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -412,7 +412,7 @@ MemNInitDefaultsDA (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -435,7 +435,7 @@ MemNWritePatternDA (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c
index 1d28b16..ff88547 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c
@@ -97,7 +97,7 @@
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -131,7 +131,7 @@ MemNBeforeDramInitDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -236,7 +236,7 @@ memNAutoConfigDA (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -265,7 +265,7 @@ MemNSendMrsCmdDA (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -296,7 +296,7 @@ MemNBeforePlatformSpecDA (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -336,7 +336,7 @@ MemNChangeAvgValue8DA (
return FALSE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -368,7 +368,7 @@ MemNEnDLLShutDownDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -448,7 +448,7 @@ MemNCapSpeedBatteryLifeDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
index cdb3b8e..d6615ee 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
@@ -87,7 +87,7 @@
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c
index 1634d06..8ff92e2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c
@@ -88,7 +88,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c
index 3a049a1..a158f69 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c
@@ -88,7 +88,7 @@
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
index 444459c..9519080 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
@@ -97,7 +97,7 @@ MemNPowerDownCtlDA (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -136,7 +136,7 @@ MemNOtherTimingDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -159,7 +159,7 @@ MemNSetOtherTimingDA (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
index 623d424..b37ffb6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
@@ -51,7 +51,7 @@
#include "Filecode.h"
#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c
index 2ae2b87..742b97b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c
@@ -89,7 +89,7 @@
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -121,7 +121,7 @@ MemNIsIdSupportedDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -236,7 +236,7 @@ MemNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c
index 94df7f1..daf99fa 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -80,7 +80,7 @@ MemConstructRemoteNBBlockDR (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c
index 472a260..70175ce 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c
@@ -441,7 +441,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -518,7 +518,7 @@ MemS3ResumeConstructNBBlockDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -569,7 +569,7 @@ MemNS3GetRegLstPtrDr (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -598,7 +598,7 @@ MemNS3GetDeviceRegLstDr (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -652,7 +652,7 @@ MemNS3SetSpecialPCIRegDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
index f70dfc3..f2641cf 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
@@ -101,7 +101,7 @@ extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -216,7 +216,7 @@ memNAutoConfigDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -233,7 +233,7 @@ MemNBeforeDramInitDr (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -279,7 +279,7 @@ MemNSendMrsCmdDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -310,7 +310,7 @@ MemNBeforePlatformSpecDr (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -343,7 +343,7 @@ MemTCtlOnDimmMirrorDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -365,7 +365,7 @@ MemNPFenceAdjustDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
index c79fe40..73aa3ed 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
@@ -100,7 +100,7 @@
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -225,7 +225,7 @@ MemConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -335,7 +335,7 @@ MemNInitNBDataDr (
NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -404,7 +404,7 @@ MemNInitDefaultsDR (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -427,7 +427,7 @@ MemNWritePatternDr (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
index 9eba8fe..4cc34d9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
@@ -87,7 +87,7 @@
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c
index 622eddb..207d229 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c
@@ -88,7 +88,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c
index e06159d..4305073 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c
@@ -88,7 +88,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
index fc58fb1..f0cd2f2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
@@ -97,7 +97,7 @@ MemNPowerDownCtlDR (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -135,7 +135,7 @@ MemNOtherTimingDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -158,7 +158,7 @@ MemNSetOtherTimingDR (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
index 855b1c5..ee17f69 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
@@ -71,7 +71,7 @@ MemNTrainFenceWHardCodeValDr (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -99,7 +99,7 @@ MemPPhyFenceTrainingDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -134,7 +134,7 @@ MemNTrainFenceWHardCodeValDr (
NBPtr->SwitchDCT (NBPtr, CurDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c
index c2fe73c..b884a64 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c
@@ -90,7 +90,7 @@
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -124,7 +124,7 @@ MemNIsIdSupportedDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -239,7 +239,7 @@ MemNCmnGetSetFieldDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c
index 5005f8a..516be53 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -79,7 +79,7 @@ MemConstructRemoteNBBlockHY (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
#endif
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c
index a4d3377..03045e5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c
@@ -472,7 +472,7 @@ MemS3ResumeConstructNBBlockHy (
IN UINT8 NodeID
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -549,7 +549,7 @@ MemS3ResumeConstructNBBlockHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -600,7 +600,7 @@ MemNS3GetRegLstPtrHy (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -629,7 +629,7 @@ MemNS3GetDeviceRegLstHy (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -683,7 +683,7 @@ MemNS3SetSpecialPCIRegHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c
index 87b8ed4..8050755 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c
@@ -90,7 +90,7 @@
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -233,7 +233,7 @@ MemNAutoConfigHy (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -262,7 +262,7 @@ MemNSendMrsCmdHy (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -289,7 +289,7 @@ MemNBeforeDramInitHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -323,7 +323,7 @@ MemNEnDLLShutDownHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
index 42ff00d..d6f692e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
@@ -82,7 +82,7 @@
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
index 8780ce5..4132f2f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
@@ -97,7 +97,7 @@
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -223,7 +223,7 @@ MemConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -337,7 +337,7 @@ MemNInitNBDataHy (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -405,7 +405,7 @@ MemNInitDefaultsHY (
// ECC
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -428,7 +428,7 @@ MemNWritePatternHy (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c
index 5e7ed75..6e9af95 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c
@@ -89,7 +89,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c
index ce2acc5..cf3344a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c
@@ -86,7 +86,7 @@
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c
index 730c00f..45b68c2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c
@@ -97,7 +97,7 @@ MemNGetODTDelaysHy (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -136,7 +136,7 @@ MemNOtherTimingHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -160,7 +160,7 @@ MemNSetOtherTimingHY (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -205,7 +205,7 @@ MemNGetODTDelaysHy (
return ODTDelays;
}
#endif
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c
index ddf17c4..cb4f659 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c
@@ -91,10 +91,10 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -177,7 +177,7 @@ MemNInitPhyCompHy (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c
index dba2879..2bfdc67 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c
@@ -87,7 +87,7 @@
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -113,7 +113,7 @@ MemNIsIdSupportedHy (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -137,7 +137,7 @@ MemNGetSocketRelativeChannelHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -261,7 +261,7 @@ MemNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
index b4f4a80..f12f601 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
@@ -100,7 +100,7 @@
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -347,7 +347,7 @@ MemNInitNBDataNi (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -414,7 +414,7 @@ MemNInitDefaultsNi (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -437,7 +437,7 @@ MemNWritePatternNi (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c
index c1306c6..57d441f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c
@@ -473,7 +473,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -550,7 +550,7 @@ MemS3ResumeConstructNBBlockNi (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -601,7 +601,7 @@ MemNS3GetRegLstPtrNi (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -629,7 +629,7 @@ MemNS3GetDeviceRegLstNi (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -683,7 +683,7 @@ MemNS3SetSpecialPCIRegNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c
index 731427c..fe5ff0a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c
@@ -95,7 +95,7 @@ extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -134,7 +134,7 @@ MemNInitNBDataNb (
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -216,7 +216,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -242,7 +242,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -286,7 +286,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -307,7 +307,7 @@ MemNTrainingFlowNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default NB return function
@@ -322,7 +322,7 @@ MemNDefNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function.
@@ -337,7 +337,7 @@ MemNDefFalseNb (
return FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -359,7 +359,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c
index 8ea5783..011c732 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c
@@ -101,7 +101,7 @@ MemNS3GetDummyReadAddr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -208,7 +208,7 @@ MemNS3ResumeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -302,7 +302,7 @@ MemNS3GetConPCIMaskNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -348,7 +348,7 @@ MemNS3GetCSRNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -409,7 +409,7 @@ MemNS3SetCSRNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -432,7 +432,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -455,7 +455,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -485,7 +485,7 @@ MemNS3RestoreScrubNb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -567,7 +567,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c
index 76712ff..6b7a193 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c
@@ -116,7 +116,7 @@ MemNQuarterMemClk2NClkNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -360,7 +360,7 @@ MemNPlatformSpecNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -433,7 +433,7 @@ MemNPlatformSpecClientNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -461,7 +461,7 @@ MemNDisableDCTNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -494,7 +494,7 @@ MemNDisableDCTClientNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -532,7 +532,7 @@ MemNStartupDCTNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DRAM devices on all DCTs at the same time
@@ -588,7 +588,7 @@ MemNStartupDCTClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemNChangeFrequencyHy:
@@ -723,7 +723,7 @@ MemNChangeFrequencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency the next level if it have not reached
@@ -787,7 +787,7 @@ MemNRampUpFrequencyNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -889,7 +889,7 @@ MemNProgramCycTimingsNb (
MemNSetBitFieldNb (NBPtr, BFASR, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -978,7 +978,7 @@ MemNProgramCycTimingsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1006,7 +1006,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1040,7 +1040,7 @@ MemNGetMaxLatParamsNb (
*DlyBiasPtr += 1; // add 1 NCLK
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1087,7 +1087,7 @@ MemNGetMaxLatParamsClientNb (
MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1147,7 +1147,7 @@ MemNSetMaxLatencyNb (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1182,7 +1182,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1212,7 +1212,7 @@ MemNAfterStitchMemNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1234,7 +1234,7 @@ MemNGet1KTFawTkNb (
return Tab1KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1256,7 +1256,7 @@ MemNGet2KTFawTkNb (
return Tab2KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1286,7 +1286,7 @@ MemNQuarterMemClk2NClkNb (
*SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1332,7 +1332,7 @@ MemNTotalSyncComponentsNb (
return SubTotal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1360,7 +1360,7 @@ MemNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -1437,7 +1437,7 @@ MemNProgramPlatformSpecNb (
MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1477,7 +1477,7 @@ MemNGetTrdrdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1512,7 +1512,7 @@ MemNGetTwrwrNb (
return DCTPtr->Timings.Twrwr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1557,7 +1557,7 @@ MemNGetTwrrdNb (
return DCTPtr->Timings.Twrrd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1598,7 +1598,7 @@ MemNGetTrwtTONb (
return DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1622,7 +1622,7 @@ MemNGetTrwtWBNb (
return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1642,7 +1642,7 @@ MemNGetMemClkFreqIdNb (
return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1683,7 +1683,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1703,7 +1703,7 @@ MemNGetMemClkFreqIdClientNb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -1823,7 +1823,7 @@ MemNChangeFrequencyClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
CONST UINT16 PllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6};
/**
@@ -1932,7 +1932,7 @@ MemNProgramNbPstateDependentRegistersClientNb (
MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2014,7 +2014,7 @@ MemNTotalSyncComponentsClientNb (
return (((P * MemClkPeriod + 1) / 2) + T);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c
index 0b8c401..92236be 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c
@@ -156,7 +156,7 @@ MemNInitCPGClientNb (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -184,7 +184,7 @@ MemNInitCPGNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes 9 or 18 cache lines continuously using GH CPG engine
@@ -233,7 +233,7 @@ MemNContWritePatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -325,7 +325,7 @@ MemNContReadPatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -351,7 +351,7 @@ MemNGenHwRcvEnReadsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes cache lines continuously using TCB CPG engine
@@ -413,7 +413,7 @@ MemNContWritePatternClientNb (
MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -461,7 +461,7 @@ MemNContReadPatternClientNb (
MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -486,7 +486,7 @@ MemNGenHwRcvEnReadsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -508,7 +508,7 @@ MemNInitCPGClientNb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -534,7 +534,7 @@ MemNCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c
index 418c0d1..aed5b1b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c
@@ -98,7 +98,7 @@ MemNCleanupDctRegsNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -160,7 +160,7 @@ MemNInitMCTNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -209,7 +209,7 @@ MemNInitDCTNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
@@ -236,7 +236,7 @@ MemNTechBlockSwitchNb (
TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
index 942fe1f..86e9660 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
@@ -101,7 +101,7 @@ MemNSetMTRRrangeNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -139,7 +139,7 @@ MemNInitializeMctNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -270,7 +270,7 @@ MemNSyncTargetSpeedNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -300,7 +300,7 @@ MemNSyncDctsReadyNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -434,7 +434,7 @@ MemNHtMemMapInitNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -505,7 +505,7 @@ MemNSyncAddrMapToAllNodesNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -536,7 +536,7 @@ MemNPowerDownCtlNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -602,7 +602,7 @@ MemNGetOptimalCGDDNb (
return CGDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -662,7 +662,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -777,7 +777,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -837,7 +837,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -932,7 +932,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -977,7 +977,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -995,7 +995,7 @@ MemNGetUmaSizeNb (
return 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c
index 1c3dbe5..5d6b258 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c
@@ -96,7 +96,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -120,7 +120,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -145,7 +145,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -163,7 +163,7 @@ MemNPhyFenceTrainingNb (
NBPtr->MemPPhyFenceTrainingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -244,7 +244,7 @@ MemNPhyFenceTrainingClientNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -321,7 +321,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -405,7 +405,7 @@ MemNInitPhyCompNb (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -459,7 +459,7 @@ MemNBeforeDQSTrainingNb (
MemTEndTraining (NBPtr->TechPtr);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -500,7 +500,7 @@ MemNGetTrainDlyParmsNb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -640,7 +640,7 @@ MemNcmnGetSetTrainDlyNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -752,7 +752,7 @@ MemNcmnGetSetTrainDlyClientNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -819,7 +819,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -847,7 +847,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -873,7 +873,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel.
@@ -891,7 +891,7 @@ MemNCSPerChannelNb (
return MAX_CS_PER_CHANNEL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -910,7 +910,7 @@ MemNCSPerDelayNb (
return MAX_CS_PER_DELAY;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -936,7 +936,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -967,7 +967,7 @@ MemNPhyVoltageLevelClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -986,7 +986,7 @@ MemNPFenceAdjustClientNb (
*Value16 += 2; //for LN, the Avg PRE value is subtracted by 6 only.
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
index 53a8df4..dff3014 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -114,7 +114,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -137,7 +137,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -162,7 +162,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -185,7 +185,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -222,7 +222,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -252,7 +252,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -272,7 +272,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c
index 326ca11..03164a9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c
@@ -87,7 +87,7 @@
*/
extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c
index b63444f..397ffa6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c
@@ -92,7 +92,7 @@ MemTHwWlPart2 (
*/
extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -153,7 +153,7 @@ MemNDQSTiming3Nb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c
index fe4e07c..ac86792 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c
@@ -164,7 +164,7 @@ STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
@@ -201,7 +201,7 @@ MemPConstructPsRC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 C32 DDR3
@@ -258,7 +258,7 @@ MemPDoPsRC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 C32 DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c
index 3b4ed20..4b4b375 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c
@@ -98,7 +98,7 @@ STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
@@ -135,7 +135,7 @@ MemPConstructPsUC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 C32 DDR3
@@ -160,7 +160,7 @@ MemPDoPsUC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 C32
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
index 52f4245..1768ee3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
@@ -91,7 +91,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
{DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
{DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR2
@@ -129,7 +129,7 @@ MemPConstructPsSDA2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c
index 6f5a939..bce2b70 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c
@@ -105,7 +105,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR3
@@ -143,7 +143,7 @@ MemPConstructPsSDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR3
@@ -192,7 +192,7 @@ MemPDoPsSDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c
index d471387..fd66ec2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c
@@ -100,7 +100,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
@@ -138,7 +138,7 @@ MemPConstructPsUDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DA DDR3
@@ -163,7 +163,7 @@ MemPDoPsUDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
index e84769d..efe7e67 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
@@ -96,7 +96,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
@@ -134,7 +134,7 @@ MemPConstructPsRDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
index aa9ab50..66b2c57 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
@@ -111,7 +111,7 @@ STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
{DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
{DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
@@ -149,7 +149,7 @@ MemPConstructPsRDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
index 52b9284..fb2cdb9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
@@ -99,7 +99,7 @@ STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
@@ -136,7 +136,7 @@ MemPConstructPsSDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
index 6c58cb6..33eef64 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
@@ -96,7 +96,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
@@ -134,7 +134,7 @@ MemPConstructPsUDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
index b2b2cb4..a5c52eb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
@@ -92,7 +92,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
@@ -129,7 +129,7 @@ MemPConstructPsUDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
index a65220b..535fe0c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
@@ -163,7 +163,7 @@ STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
@@ -201,7 +201,7 @@ MemPConstructPsRHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 HY DDR3
@@ -257,7 +257,7 @@ MemPDoPsRHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c
index f313e81..e5768d3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
@@ -141,7 +141,7 @@ MemPConstructPsSHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 HY DDR3
@@ -190,7 +190,7 @@ MemPDoPsSHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c
index 37a277c..41fc9ca 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c
@@ -99,7 +99,7 @@ STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
@@ -136,7 +136,7 @@ MemPConstructPsUHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 HY DDR3
@@ -161,7 +161,7 @@ MemPDoPsUhy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c
index d823fcf..d973d2f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c
@@ -106,7 +106,7 @@ STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
@@ -144,7 +144,7 @@ MemPConstructPsSNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ni DDR3
@@ -193,7 +193,7 @@ MemPDoPsSNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c
index dbec150..0f22b1d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
@@ -139,7 +139,7 @@ MemPConstructPsUNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ni DDR3
@@ -164,7 +164,7 @@ MemPDoPsUNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c
index 31ebc27..aab0a4c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -109,7 +109,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -157,7 +157,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -213,7 +213,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
index a8d0810..7ad7daa 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
@@ -91,7 +91,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
index 384b247..e614f18 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
@@ -82,7 +82,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR2.
@@ -107,7 +107,7 @@ MemTAdjustTwrwr2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR2.
@@ -132,7 +132,7 @@ MemTAdjustTwrrd2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c
index 1718846..5e84356 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c
@@ -128,7 +128,7 @@ MemTGetBankAddr2 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -147,7 +147,7 @@ MemTSetDramMode2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -381,7 +381,7 @@ MemTDIMMPresence2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
@@ -497,7 +497,7 @@ MemTSPDGetTargetSpeed2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -581,7 +581,7 @@ MemTSPDCalcWidth2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -768,7 +768,7 @@ MemTAutoCycTiming2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -882,7 +882,7 @@ MemTSPDSetBanks2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -914,7 +914,7 @@ MemTGetCSIntLvAddr2 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency.
@@ -932,7 +932,7 @@ MemTSPDGetTCL2 (
return TechPtr->NBPtr->DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -964,7 +964,7 @@ MemTSysCapability2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine whether dimm(b,i) supports CL(j) and F(k)
@@ -1022,7 +1022,7 @@ MemTDimmSupports2 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the cycle time
@@ -1043,7 +1043,7 @@ MemTGetTk2 (
return TableTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1069,7 +1069,7 @@ MemTGetBankAddr2 (
return TabBankAddr[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
index b0f9a36..0782665 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
@@ -88,7 +88,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
index 8058ebd..c7b2789 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
@@ -84,7 +84,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -112,7 +112,7 @@ MemTAdjustTwrwr3 (
TechPtr->NBPtr->Node, TechPtr->NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -138,7 +138,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
index 77ddfb4..92f22cd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -94,7 +94,7 @@ MemTSendCtlWord3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -152,7 +152,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -212,7 +212,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -255,7 +255,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
index f938413..d5041d7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -103,7 +103,7 @@ MemTMRS3 (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -223,7 +223,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -348,7 +348,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -405,7 +405,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -434,7 +434,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -482,7 +482,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
index b5e7635..b487f00 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -110,7 +110,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -130,7 +130,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -383,7 +383,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -459,7 +459,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -537,7 +537,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -694,7 +694,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -817,7 +817,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -850,7 +850,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -893,7 +893,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1010,7 +1010,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1045,7 +1045,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
index 8cca4f7..324268e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -81,7 +81,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
index 660f227..9be3e18 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -127,7 +127,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -147,7 +147,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -171,7 +171,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -194,7 +194,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -223,7 +223,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -272,7 +272,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -321,7 +321,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -366,7 +366,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -475,7 +475,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE ("\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -574,7 +574,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c
index e54b6b0..4db32f9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c
@@ -83,7 +83,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -98,7 +98,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -126,7 +126,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -160,7 +160,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -190,7 +190,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c
index 79ad0db..ea0f691 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c
@@ -83,7 +83,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
index 7d4f728..b38e64a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
@@ -171,7 +171,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -213,7 +213,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -343,7 +343,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -579,7 +579,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -639,7 +639,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -667,7 +667,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -734,7 +734,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -778,7 +778,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c
index fac8640..2f473ad 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c
@@ -219,7 +219,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -310,7 +310,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -339,7 +339,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -365,7 +365,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -402,7 +402,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -461,7 +461,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -539,7 +539,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -610,7 +610,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -637,7 +637,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -667,7 +667,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -691,7 +691,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -706,7 +706,7 @@ MemTMaxByteLanesByte (VOID)
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -721,7 +721,7 @@ MemTDlyTableWidthByte (VOID)
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -759,7 +759,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -811,7 +811,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -881,7 +881,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -942,7 +942,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1105,7 +1105,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1139,7 +1139,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1272,7 +1272,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c
index b8c165e..1d2508b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c
@@ -91,7 +91,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -140,7 +140,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c
index 783d8f5..2afe44a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c
@@ -108,7 +108,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -129,7 +129,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -160,7 +160,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -240,7 +240,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -316,7 +316,7 @@ MemTPrepareRcvrEnDlySeed (
IDS_HDT_CONSOLE ("\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c
index ad67120..a89f9da 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c
@@ -84,7 +84,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c
index d9f33a1..347efdb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c
@@ -100,7 +100,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -125,7 +125,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
index 933ee94..584d11d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
@@ -93,7 +93,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -124,7 +124,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
index c82ceed..d969c24 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
@@ -137,7 +137,7 @@ TableName[BitFieldIndex] = ( \
#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
index a6b080e..2e47d2c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
index 469c974..7421726 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
@@ -52,7 +52,7 @@
#include "Filecode.h"
#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get new Socket and Node Maps.
*
@@ -107,7 +107,7 @@ NewNodeAndSocketTablesRecovery (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c
index 23623e8..2360b5e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c
@@ -110,7 +110,7 @@ typedef struct {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Routing Tables.
*
@@ -136,7 +136,7 @@ HtrEnableRoutingTables (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process the SouthBridge Link.
*
@@ -259,7 +259,7 @@ AmdHtResetConstructor (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize HT for Reset, Boot Blocks.
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c
index 8c6677d..7129a3e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c
@@ -133,7 +133,7 @@ MemRecNSwitchNodeC32 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -252,7 +252,7 @@ MemRecConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -278,7 +278,7 @@ MemRecNSwitchNodeC32 (
MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -303,7 +303,7 @@ MemRecNSwitchDctC32 (
MemRecNSwitchChannelC32 (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -331,7 +331,7 @@ MemRecNSwitchChannelC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -461,7 +461,7 @@ MemRecNcmnGetSetTrainDlyC32 (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -569,7 +569,7 @@ MemRecNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -672,7 +672,7 @@ MemRecNInitNBRegTableC32 (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
index 6116897..28898d5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
@@ -86,7 +86,7 @@
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c
index c25f85d..26c9013 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c
@@ -124,7 +124,7 @@ MemRecNIsIdSupportedDA (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -240,7 +240,7 @@ MemRecConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -264,7 +264,7 @@ MemRecNSwitchDctDA (
MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -291,7 +291,7 @@ MemRecNSwitchChannelDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -406,7 +406,7 @@ MemRecNcmnGetSetTrainDlyDA (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -509,7 +509,7 @@ MemRecNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -614,7 +614,7 @@ MemRecNInitNBRegTableDA (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c
index 5f54642..59555a4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c
@@ -85,7 +85,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c
index 9479d82..5f13245 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c
@@ -124,7 +124,7 @@ MemRecNIsIdSupportedDr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -240,7 +240,7 @@ MemRecConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -265,7 +265,7 @@ MemRecNSwitchDctDR (
MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -292,7 +292,7 @@ MemRecNSwitchChannelDR (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -407,7 +407,7 @@ MemRecNcmnGetSetTrainDlyDR (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -510,7 +510,7 @@ MemRecNCmnGetSetFieldDR (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -616,7 +616,7 @@ MemRecNInitNBRegTableDR (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
index 6803c3c..81ac031 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
@@ -87,7 +87,7 @@
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c
index 0227a4b..4f703f3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c
@@ -70,7 +70,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c
index cc4fb63..cb16882 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c
@@ -133,7 +133,7 @@ MemRecNSwitchNodeHy (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -252,7 +252,7 @@ MemRecConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -278,7 +278,7 @@ MemRecNSwitchNodeHy (
MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -303,7 +303,7 @@ MemRecNSwitchDctHy (
MemRecNSwitchChannelHy (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -331,7 +331,7 @@ MemRecNSwitchChannelHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -461,7 +461,7 @@ MemRecNcmnGetSetTrainDlyHy (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -569,7 +569,7 @@ MemRecNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -672,7 +672,7 @@ MemRecNInitNBRegTableHy (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
index 75566b3..d50166d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
@@ -86,7 +86,7 @@
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c
index a8cb8a4..52873f4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c
@@ -125,7 +125,7 @@ MemRecNIsIdSupportedNi (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -241,7 +241,7 @@ MemRecConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -265,7 +265,7 @@ MemRecNSwitchDctNi (
MemRecNSwitchChannelNi (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -292,7 +292,7 @@ MemRecNSwitchChannelNi (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -407,7 +407,7 @@ MemRecNcmnGetSetTrainDlyNi (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -510,7 +510,7 @@ MemRecNCmnGetSetFieldNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -615,7 +615,7 @@ MemRecNInitNBRegTableNi (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedNi
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
index d6b9011..66841da 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
@@ -91,7 +91,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a bit field from PCI register
@@ -113,7 +113,7 @@ MemRecNGetBitFieldNb (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets a bit field from PCI register
@@ -134,7 +134,7 @@ MemRecNSetBitFieldNb (
NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
@@ -157,7 +157,7 @@ MemRecNGetTrainDlyNb (
return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c
index bbdd9a5..fb631cd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c
@@ -108,7 +108,7 @@ MemRecNSwapBitsNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
@@ -217,7 +217,7 @@ MemRecNAutoConfigNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -290,7 +290,7 @@ MemRecNPlatformSpecNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function reads MemClkFreqVal bit to see if the DIMMs are present in this node.
@@ -335,7 +335,7 @@ MemRecNStartupDCTNb (
while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -403,7 +403,7 @@ MemRecNSetMaxLatencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -481,7 +481,7 @@ MemRecNSetDramOdtNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -531,7 +531,7 @@ MemRecNSendMrsCmdNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends the ZQCL command
@@ -559,7 +559,7 @@ MemRecNSendZQCmdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -591,7 +591,7 @@ MemRecTCtlOnDimmMirrorNb (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c
index 23044d5..b247b63 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c
@@ -87,7 +87,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for Nb DDR3
@@ -147,7 +147,7 @@ MemRecNMemInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
@@ -179,7 +179,7 @@ MemRecNInitializeMctNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a physical address of a corresponding Chip select
@@ -201,7 +201,7 @@ MemRecNGetMCTSysAddrNb (
return CSBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
@@ -263,7 +263,7 @@ MemRecNCPUMemRecTypingNb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c
index 327a3f9..d53db2c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -80,7 +80,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
index 02a9398..8eba8fe 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
@@ -81,7 +81,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
index 35d19c4..0a7e906 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
@@ -99,7 +99,7 @@ MemRecTSendCtlWord3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -143,7 +143,7 @@ MemRecTDramControlRegInit3 (
MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -192,7 +192,7 @@ MemRecTGetCtlWord3 (
return (Data&0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
index 694103a..7ddf1e4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
@@ -88,7 +88,7 @@
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init
@@ -175,7 +175,7 @@ MemRecTDramInitSw3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -227,7 +227,7 @@ MemRecTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -271,7 +271,7 @@ MemRecTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -300,7 +300,7 @@ MemRecTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MSS value
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
index de458fe..94ec678 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
@@ -88,7 +88,7 @@
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -108,7 +108,7 @@ MemRecTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
index c3c4065..1d21fe6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
@@ -106,7 +106,7 @@ MemRecTBeginWLTrain3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -170,7 +170,7 @@ MemRecTTrainDQSWriteHw3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -228,7 +228,7 @@ MemRecTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function configures the DIMMS for Write Levelization
@@ -290,7 +290,7 @@ MemRecTProcConfig3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
index fda9a54..e0bd23d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -83,7 +83,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function hard-codes DQS position delays for all bytes
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c
index 536e28f..304ee23 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c
@@ -132,7 +132,7 @@ MemRecTEndTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for BSP
@@ -243,7 +243,7 @@ MemRecTTrainRcvrEnSw (
MemRecTEndTraining (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* If WrDatDly is 0, this function sets the DQS Positions in preparation
@@ -278,7 +278,7 @@ MemRecTSetWrDatRdDqs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -306,7 +306,7 @@ MemRecTSetRcvrEnDly (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -346,7 +346,7 @@ MemRecTCompare1ClPattern (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -400,7 +400,7 @@ MemRecTSaveRcvrEnDly (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -437,7 +437,7 @@ MemRecTLoadRcvrEnDly (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -469,7 +469,7 @@ MemRecTBeginTraining (
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
index 88065d9..79eee53 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
@@ -78,7 +78,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -90,7 +90,7 @@ MemRecDefRet (VOID)
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the DCT with initial values
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c
index 1eb113f..14d7f8e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c
@@ -79,7 +79,7 @@
*/
extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default parameter, function pointers, build options
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c
index 04ab8d2..bc3667e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c
@@ -94,7 +94,7 @@ MemRecSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for HY DDR3
@@ -202,7 +202,7 @@ AmdMemRecovery (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
index 515f993..1e92ce3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
@@ -96,7 +96,7 @@ MemRecUSetTargetWTIO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (Index)th UINT8
@@ -122,7 +122,7 @@ MemRecUFillTrainPattern (
LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -149,7 +149,7 @@ MemRecUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -167,7 +167,7 @@ MemRecUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -194,7 +194,7 @@ MemRecUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // ;64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -218,7 +218,7 @@ MemRecUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h
index 179c3f5..ae19bec 100644
--- a/src/vendorcode/amd/agesa/f12/AMD.h
+++ b/src/vendorcode/amd/agesa/f12/AMD.h
@@ -11,7 +11,7 @@
* @e sub-project: Include
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
-/*****************************************************************************/
+
/*
*****************************************************************************
*
diff --git a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h
index d464755..132633f 100644
--- a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h
@@ -184,7 +184,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h
index c760fe3..9ced5c0 100644
--- a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h
+++ b/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h
@@ -61,7 +61,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset Stub
*
@@ -80,7 +80,7 @@ GnbInitAtReset (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Stub
*
@@ -98,7 +98,7 @@ GnbInitAtEarly (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -116,7 +116,7 @@ GnbInitDataStructAtEnvDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
@@ -135,7 +135,7 @@ GnbInitAtEnv (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -154,7 +154,7 @@ GnbInitAtPost (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
@@ -173,7 +173,7 @@ GnbInitAtMid (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
@@ -192,7 +192,7 @@ GnbInitAtLate (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AmdGnbRecovery
*
@@ -209,7 +209,7 @@ AmdGnbRecovery (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
@@ -227,7 +227,7 @@ GnbInitAtPostAfterDram (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Before CPU Stub
*
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
index cfb55cc..0207a68 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
@@ -81,7 +81,7 @@ BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
index 6999c7d..eb7a295 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
@@ -61,7 +61,7 @@ RDATA_GROUP (G1_PEICC)
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -127,7 +127,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
index 044ac61..f3c1289 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
@@ -80,7 +80,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -107,7 +107,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -132,7 +132,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -155,7 +155,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -180,7 +180,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -204,7 +204,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -228,7 +228,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -252,7 +252,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -276,7 +276,7 @@ AgesaHookBeforeDramInitRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -299,7 +299,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -322,7 +322,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -345,7 +345,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -371,7 +371,7 @@ AgesaGetIdsData (
}
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
@@ -394,7 +394,7 @@ AgesaPcieSlotResetControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* OEM callout function for FCH data override
*
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
index 245a2ed..ff7efaf 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -260,7 +260,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
diff --git a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c
index 8b1a7b7..2484699 100644
--- a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c
@@ -456,7 +456,7 @@ LibAmdCLFlush (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -493,7 +493,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -530,7 +530,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -560,7 +560,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -593,7 +593,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -630,7 +630,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -667,7 +667,7 @@ LibAmdMemWrite (
ASSERT (FALSE);
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -697,7 +697,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -730,7 +730,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -781,7 +781,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -832,7 +832,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -862,7 +862,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -895,7 +895,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -930,7 +930,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -963,7 +963,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1003,7 +1003,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1077,7 +1077,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1103,7 +1103,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1131,7 +1131,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1167,7 +1167,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1217,7 +1217,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1239,7 +1239,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1283,7 +1283,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c
index 0bc3561..35d7d4d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c
@@ -88,7 +88,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c
index 6106442..f88d89e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c
@@ -82,7 +82,7 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 10h CPU.
*
@@ -123,7 +123,7 @@ F10InitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 10h core.
*
@@ -142,7 +142,7 @@ F10InitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -164,7 +164,7 @@ F10GetAcpiCstObj (
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -240,7 +240,7 @@ F10CreateAcpiCstObj (
*PstateAcpiBufferPtr = CstBodyPtr;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether IO Cstate should be supported.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index ce1748f..4977d55 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -84,7 +84,7 @@ SetAsymBoost (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Asymmetric Boost
* Configuration" algorithm.
@@ -143,7 +143,7 @@ F10PmAsymBoostInit (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set Asymmetric Boost.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index c787637..3869312 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -84,7 +84,7 @@ SetPstateMSR (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
*
@@ -192,7 +192,7 @@ F10PmDualPlaneOnlySupport (
}
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set P-State MSR.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 0ee939e..154fafe 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -100,7 +100,7 @@ PmNbCofVidInitWarmCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
@@ -225,7 +225,7 @@ F10PmNbCofVidInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
@@ -259,7 +259,7 @@ PmNbCofVidInitP0P1Core (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index ec48d58..97e7b1b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -89,7 +89,7 @@ PmNbPstateInitCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
@@ -149,7 +149,7 @@ F10PmNbPstateInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmNbPstateInit.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
index 3e7d9d9..b970141 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable BL-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 128033a..040d077 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -75,7 +75,7 @@ STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index e1cabaa..a874188 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -75,7 +75,7 @@ extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
index 1f1e4e3..65a27ee 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index f8ecb47..967d7e4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -76,7 +76,7 @@ STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 65008a5..5f69742 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -75,7 +75,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
index 8a7c133..3612256 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -80,7 +80,7 @@ F10InitializeHwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -107,7 +107,7 @@ F10IsHwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h CPU.
*
@@ -154,7 +154,7 @@ F10InitializeHwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
index 3511c50..bea01cd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
@@ -79,7 +79,7 @@ F10InitializeSwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -99,7 +99,7 @@ F10IsSwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h CPU.
*
@@ -140,7 +140,7 @@ F10InitializeSwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 7e06c4a..3248ff2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision C processor.
*
@@ -163,7 +163,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision C processor.
*
@@ -249,7 +249,7 @@ F10CommonRevCGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -280,7 +280,7 @@ F10CommonRevCGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -351,7 +351,7 @@ F10CommonRevCGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -425,7 +425,7 @@ F10RevCGetMinMaxNbFrequency (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -470,7 +470,7 @@ F10CommonRevCIsNbPstateEnabled (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index 44076e4..923a846 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -78,7 +78,7 @@ STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index e4d08f9..a141d26 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -75,7 +75,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
index df2f9ec..5fa2ee0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
@@ -113,7 +113,7 @@ F10RevDProbeFilterCritical (
IN UINT32 LocalPciRegister
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports L3 dependent features.
*
@@ -154,7 +154,7 @@ F10IsL3FeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports HT Assist.
*
@@ -197,7 +197,7 @@ F10IsHtAssistSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the Probe filter feature.
*
@@ -246,7 +246,7 @@ F10HtAssistInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save the current settings of the scrubbers, and disabled them.
*
@@ -301,7 +301,7 @@ F10GetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restore the initial settings for the scrubbers.
*
@@ -349,7 +349,7 @@ F10SetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set MSR bits required for L3 dependent features on each core.
*
@@ -374,7 +374,7 @@ F10HookDisableCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Hook before L3 features initialization sequence.
*
@@ -430,7 +430,7 @@ F10HookBeforeInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU is running in the optimal configuration.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
index f0321ba..28b3c5c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -91,7 +91,7 @@ IsDramScrubberEnabled (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -116,7 +116,7 @@ F10IsMsgBasedC1eSupported (
return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
@@ -209,7 +209,7 @@ F10InitializeMsgBasedC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable message-based C1e on a family 10h core.
*
@@ -242,7 +242,7 @@ F10InitializeMsgBasedC1eOnCore (
LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 0653d68..c0d78e6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision D processor.
*
@@ -172,7 +172,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
F10CommonRevDSetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision D processor.
*
@@ -246,7 +246,7 @@ F10CommonRevDGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -272,7 +272,7 @@ F10CommonRevDGetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -320,7 +320,7 @@ F10CommonRevDGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -356,7 +356,7 @@ F10RevDGetMinMaxNbFrequency (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index 7700b12..7c3ee35 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -75,7 +75,7 @@ STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
index bada89f..fb2a0c7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -92,7 +92,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 14f6d63..828e7d1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -75,7 +75,7 @@ extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
index 90146a9..6fd1dba 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision E processor.
*
@@ -172,7 +172,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
F10CommonRevESetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision E processor.
*
@@ -248,7 +248,7 @@ F10CommonRevEGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -296,7 +296,7 @@ F10CommonRevEGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -332,7 +332,7 @@ F10RevEGetMinMaxNbFrequency (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -363,7 +363,7 @@ F10CommonRevEGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index c56622b..a0d752f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -74,7 +74,7 @@ STATIC CONST UINT16 ROMDATA CpuF10PhMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index c1da173..2af83fa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -74,7 +74,7 @@ extern CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
index 29e78df..9c0846f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -92,7 +92,7 @@ typedef union {
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -129,7 +129,7 @@ F10SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -161,7 +161,7 @@ F10GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -195,7 +195,7 @@ F10GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the system AP core number in the AP's Mailbox.
*
@@ -233,7 +233,7 @@ F10SetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -260,7 +260,7 @@ F10GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Move the AP's core number from the mailbox to hardware.
*
@@ -297,7 +297,7 @@ F10TransferApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
index 0339367..33ff6c4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -81,7 +81,7 @@ extern CONST UINT8 F10BrandIdString2TableCount;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -109,7 +109,7 @@ GetF10BrandIdString1 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 85d5134..49fb53e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -95,7 +95,7 @@ CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
index e55e31b..5f21c08 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Cpb.c
index a1de94e..1b7b949 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Cpb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Cpb.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -106,7 +106,7 @@ F10IsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
index cf92acc..6adea23 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -82,7 +82,7 @@ F10Translate7BitVidTo6Bit (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetInfo
@@ -148,7 +148,7 @@ DmiF10GetInfo (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetVoltage
@@ -214,7 +214,7 @@ DmiF10GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMaxSpeed
@@ -244,7 +244,7 @@ DmiF10GetMaxSpeed (
return ((UINT16) P0Frequency);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetExtClock
@@ -264,7 +264,7 @@ DmiF10GetExtClock (
return (EXTERNAL_CLOCK_DFLT);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMemInfo
@@ -454,7 +454,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* F10Translate7BitVidTo6Bit
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index bfa0017..426b55f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -98,7 +98,7 @@ WaitForCpuFidAndDidToMatch (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -200,7 +200,7 @@ F10PmAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
@@ -375,7 +375,7 @@ F10PmAfterResetCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index beb318b..f523e59 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -87,7 +87,7 @@ updateCpuFeatureList (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function get features which CPU supports.
@@ -206,7 +206,7 @@ F10SaveFeatures (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function set features which All CPUs support.
@@ -313,7 +313,7 @@ F10WriteFeatures (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* cpuFeatureListNeedUpdate
@@ -354,7 +354,7 @@ cpuFeatureListNeedUpdate (
return flag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* updateCpuFeatureList
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index ccb6f43..7087b9a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -93,7 +93,7 @@ F10PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the family 10h Processor-
* Systemboard Power Delivery Check.
@@ -292,7 +292,7 @@ F10PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -380,7 +380,7 @@ F10PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
index 4a258dc..92be840 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -82,7 +82,7 @@ RDATA_GROUP (G1_PEICC)
*/
/* Family 10h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
{
IDS_INITIAL_F10_PM_STEP
@@ -144,7 +144,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
index 59fca3f..81f2c6c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -139,7 +139,7 @@ F10PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
@@ -299,7 +299,7 @@ F10CpuAmdPmPwrPlaneInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10CpuAmdPmPwrPlaneInit.
*
@@ -337,7 +337,7 @@ F10PmPwrPlaneInitPviCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded altvid voltage stabilization slam time for the executing
* family 10h core.
@@ -405,7 +405,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
index f0e1ebb..a274889 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -102,7 +102,7 @@ F10GetFrequencyXlatRegInfo (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -171,7 +171,7 @@ F10SetTscFreqSel (
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -280,7 +280,7 @@ F10GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -337,7 +337,7 @@ F10GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer.
*
@@ -485,7 +485,7 @@ F10PstateLevelingCoreMsrModify (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -582,7 +582,7 @@ F10GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -616,7 +616,7 @@ F10GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
@@ -760,7 +760,7 @@ F10GetPllValueInTime (
*PllLockTimePtr = 0;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
index a6d6a73..b394019 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
index 564094e..557fd7e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -94,7 +94,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated CPU
* Voltage Transitions.'
@@ -132,7 +132,7 @@ F10PmSwVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated NB
* Voltage Transitions.'
@@ -182,7 +182,7 @@ F10PmSwVoltageTransitionServerNb (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current VsSlamTime in microseconds.
*
@@ -223,7 +223,7 @@ F10GetCurrentVsTimeInUsecs (
*VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until VsSlamTime microseconds have expired.
*
@@ -244,7 +244,7 @@ F10WaitOutVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Code required to be run on every local core in order to perform
* the steps necessary for 'Software Initiated NB Voltage
@@ -289,7 +289,7 @@ F10SwVoltageTransitionServerNbCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
*
@@ -373,7 +373,7 @@ F10ProgramVSSlamTimeOnSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded voltage stabilization slam time for the executing
* family 10h core.
@@ -434,7 +434,7 @@ F10GetSlamTimeEncoding (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -462,7 +462,7 @@ F10DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -498,7 +498,7 @@ F10TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -533,7 +533,7 @@ F10GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -581,7 +581,7 @@ F10GetCurrentNbFrequency (
return ReturnCode;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -702,7 +702,7 @@ F10LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -726,7 +726,7 @@ F10GetPlatformTypeSpecificInfo (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the next HT link.
*
@@ -851,7 +851,7 @@ F10GetNextHtLinkFeatures (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -1077,7 +1077,7 @@ F10NextLinkHasHtPhyFeats (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
@@ -1144,7 +1144,7 @@ F10SetHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the number of core performance boost states.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
index c08b7f1..ffd2d8d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -90,7 +90,7 @@ AMD_WHEA_INIT_DATA F10WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c
index 43bd31b..f02ef70 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c
@@ -78,7 +78,7 @@ extern F12_ES_C6_SUPPORT F12EarlySampleC6Support;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -114,7 +114,7 @@ F12IsC6Supported (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C6 on a family 12h CPU.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
index 96b3872..ce8a3b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -109,7 +109,7 @@ F12IsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
index e422b58..f8a61fc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
@@ -79,7 +79,7 @@ F12InitializeIoCstateOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 12h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.3.2.9 BIOS Requirements for Initialization
@@ -146,7 +146,7 @@ F12InitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C-State on a family 12h core.
*
@@ -166,7 +166,7 @@ F12InitializeIoCstateOnCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -188,7 +188,7 @@ F12GetAcpiCstObj (
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the ACPI C-State objects
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
index 31022a6..6757c1e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
@@ -83,7 +83,7 @@ STATIC CONST UINT16 ROMDATA CpuF12LnMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
index bc17159..6b49eca 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
@@ -81,7 +81,7 @@ GetF12LnMicroCodePatchesStruct (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c
index 28e50f7..cbb14d4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c
@@ -135,7 +135,7 @@ F12CpuAmdCoreIdPositionInInitialApicId (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -172,7 +172,7 @@ F12SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -204,7 +204,7 @@ F12GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -232,7 +232,7 @@ F12GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -259,7 +259,7 @@ F12GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
@@ -280,7 +280,7 @@ F12CpuAmdCoreIdPositionInInitialApicId (
return (CoreIdPositionOne);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up a valid set of NB P-states based on the value of MEMCLK, transitions
* to the desired NB P-state, and returns the current NB frequency in megahertz.
@@ -539,7 +539,7 @@ F12NbPstateInit (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs integer division, and rounds the quotient up if the remainder is greater
* than or equal to 50% of the divisor.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c
index ff61867..68f2658 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c
@@ -97,7 +97,7 @@ GetF12BrandIdString2 (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -124,7 +124,7 @@ GetF12BrandIdString1 (
*NumberOfElements = F12BrandIdString1TableCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
index bcdf5f8..07a3ed2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
@@ -100,7 +100,7 @@ CONST CACHE_INFO ROMDATA CpuF12CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c
index 627b3a5..181d9e3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c
@@ -101,7 +101,7 @@ DmiF12GetMemInfo (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF12GetInfo
@@ -154,7 +154,7 @@ DmiF12GetInfo (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF12GetVoltage
@@ -196,7 +196,7 @@ DmiF12GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF12GetMaxSpeed
@@ -231,7 +231,7 @@ DmiF12GetMaxSpeed (
return ((UINT16) P0Frequency);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF12GetExtClock
@@ -251,7 +251,7 @@ DmiF12GetExtClock (
return (EXTERNAL_CLOCK_100MHZ);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF12GetMemInfo
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c
index 01ae3b7..164957d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 12h core 0 entry point for performing early NB P-state initialization.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
index 7ad2980..440edb7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
@@ -93,7 +93,7 @@ F12PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 12h core 0 entry point for performing the family 12h Processor-
* Systemboard Power Delivery Check.
@@ -248,7 +248,7 @@ F12PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -335,7 +335,7 @@ F12PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c
index 62dcf63..9863417 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c
@@ -85,7 +85,7 @@ GetF12SysPmTable (
*/
/* Family 12h Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF12SysPmTableArray[] =
{
IDS_INITIAL_F12_PM_STEP
@@ -120,7 +120,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF12SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c
index da2da21..844ab66 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c
@@ -103,7 +103,7 @@ F12PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 12h core 0 entry point for performing power plane initialization.
*
@@ -204,7 +204,7 @@ F12PmPwrPlaneInit (
WaitMicroseconds (SingleVidStepTransitionTime, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
index a6da2e2..fa668d6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
@@ -120,7 +120,7 @@ F12GetPstateRegisterInfo (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -169,7 +169,7 @@ F12SetTscFreqSel (
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -200,7 +200,7 @@ F12GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -295,7 +295,7 @@ F12GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*--------------------------------------------------------------------------------------*/
+
/**
*
* Family specific call to calculates the power in milliWatts of the desired P-state.
@@ -357,7 +357,7 @@ F12GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -397,7 +397,7 @@ F12GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c
index 99c7045..cc80246 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c
@@ -79,7 +79,7 @@ F12PmThermalInit (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the SW Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c
index ec0d325..ad5cd21 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c
@@ -141,7 +141,7 @@ F12ConvertEnabledBitsIntoCount (
*EnabledCoreCountPtr = EnabledCoreCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -169,7 +169,7 @@ F12DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -205,7 +205,7 @@ F12TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -246,7 +246,7 @@ F12GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -278,7 +278,7 @@ F12GetCurrentNbFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -336,7 +336,7 @@ F12GetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -364,7 +364,7 @@ F12IsNbPstateEnabled (
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPsCap == 1));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -390,7 +390,7 @@ F12GetNbCofVidUpdate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -471,7 +471,7 @@ F12LaunchApCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -496,7 +496,7 @@ F12GetPlatformTypeSpecificInfo (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current.
*
@@ -563,7 +563,7 @@ F12GetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c
index 534402d..e340982 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c
@@ -97,7 +97,7 @@ AMD_WHEA_INIT_DATA F12WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c
index 00caec2..5bb8f0d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c
@@ -82,7 +82,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The contents of the mailbox registers should always be preserved.
*
@@ -102,7 +102,7 @@ IsPreserveAroundMailboxEnabled (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c
index 3baef27..1f91146 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c
@@ -89,7 +89,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -127,7 +127,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -202,7 +202,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
@@ -231,7 +231,7 @@ EnableC6OnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h
index afeef19..814e403 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
@@ -104,7 +104,7 @@ typedef AGESA_STATUS F_C6_INIT (
/// Reference to a Method.
typedef F_C6_INIT *PF_C6_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to reload microcode patch after memory is initialized.
*
@@ -133,7 +133,7 @@ struct _C6_FAMILY_SERVICES {
PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index 5f9f1b3..505c74b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -108,7 +108,7 @@ InitializeCacheFlushOnHaltFeature (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -128,7 +128,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
@@ -165,7 +165,7 @@ InitializeCacheFlushOnHaltFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
index fbc1b5e..2e86621 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
@@ -142,7 +142,7 @@ IsPowerOfTwo (
IN UINT32 TestNumber
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -428,7 +428,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -521,7 +521,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -546,7 +546,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
@@ -594,7 +594,7 @@ CalculateOccupiedExeCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function compares two memory regions for overlap and returns the combined
* Base,Size to describe the new combined region.
@@ -722,7 +722,7 @@ CompareRegions (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This local function tests the parameter for being an even power of two
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
index e9f6f12..ea2d585 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -100,7 +100,7 @@ CoreLevelingAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -128,7 +128,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c
index ca88d3c..0238e6c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should CPB be enabled
*
@@ -115,7 +115,7 @@ IsCpbFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable core performance boost
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h
index 468536e..6d6ea85 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if CPB is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_CPB_IS_SUPPORTED (
/// Reference to a Method.
typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable CPB.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
index 5c05da6..f915a4b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
@@ -116,7 +116,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -143,7 +143,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -169,7 +169,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -374,7 +374,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -557,7 +557,7 @@ GetType4Type7Info (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* DmiGetT4ProcFamilyFromBrandId
*
@@ -594,7 +594,7 @@ DmiGetT4ProcFamilyFromBrandId (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetNameString
@@ -629,7 +629,7 @@ GetNameString (
String[StringIndex] = '\0';
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IsSourceStrContainTargetStr
@@ -673,7 +673,7 @@ IsSourceStrContainTargetStr (
return IsContained;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -708,7 +708,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -729,7 +729,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -752,7 +752,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c
index d43c9a0..faf8cc8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -111,7 +111,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -187,7 +187,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -212,7 +212,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -237,7 +237,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h
index da11585..f5e7e52 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h
@@ -178,7 +178,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -197,7 +197,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c
index 91a861a..c7e9ec5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -130,7 +130,7 @@ IsHwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h
index 205ca8b..e0540b6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if hardware C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c
index 43fe680..39fb9b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c
@@ -86,7 +86,7 @@ EnableIoCstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should IO Cstate be enabled
* If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
@@ -133,7 +133,7 @@ IsIoCstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate feature
*
@@ -169,7 +169,7 @@ InitializeIoCstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable IO Cstate on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h
index bd3649d..814c8df 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h
@@ -166,7 +166,7 @@ typedef struct _ACPI_CST_GET_INPUT {
} ACPI_CST_GET_INPUT ;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if IO Cstate is supported.
*
@@ -184,7 +184,7 @@ typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable IO Cstate.
*
@@ -203,7 +203,7 @@ typedef AGESA_STATUS F_IO_CSTATE_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to return the size of ACPI C-State Objects
*
@@ -220,7 +220,7 @@ typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to create ACPI C-State Objects
*
@@ -237,7 +237,7 @@ typedef VOID F_IO_CSTATE_CREATE_CST (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c
index 5ccda88..41e795d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should L3 features be enabled
*
@@ -129,7 +129,7 @@ IsL3FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable L3 dependent features.
*
@@ -277,7 +277,7 @@ InitializeL3Feature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Disable all the caches on current core.
@@ -310,7 +310,7 @@ DisableAllCaches (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Enable all the caches on current core.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h
index c901b7f..0d92bbf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h
@@ -63,7 +63,7 @@ AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES);
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if L3 Features are supported.
*
@@ -84,7 +84,7 @@ typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before L3 features are initialized.
*
@@ -102,7 +102,7 @@ typedef VOID F_L3_FEATURE_BEFORE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -120,7 +120,7 @@ typedef VOID F_L3_FEATURE_DISABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -138,7 +138,7 @@ typedef VOID F_L3_FEATURE_ENABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize L3 Features
*
@@ -156,7 +156,7 @@ typedef VOID F_L3_FEATURE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook after L3 Features are initialized.
*
@@ -174,7 +174,7 @@ typedef VOID F_L3_FEATURE_AFTER_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -194,7 +194,7 @@ typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -214,7 +214,7 @@ typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -235,7 +235,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize HT Assist
*
@@ -253,7 +253,7 @@ typedef VOID F_HT_ASSIST_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to provide non_optimal HT Assist support
*
@@ -274,7 +274,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if ATM Mode is supported.
*
@@ -295,7 +295,7 @@ typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize ATM mode
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c
index a23a89a..dfef877 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c
@@ -85,7 +85,7 @@ EnableLowPwrPstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
//extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Low Power P-state be enabled
* If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
@@ -129,7 +129,7 @@ IsLowPwrPstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable low power P-state
*
@@ -183,7 +183,7 @@ InitializeLowPwrPstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable low power P-state
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h
index 77da750..50ea49c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Low Power P-state is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable Low Power P-state
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c
index 0e01624..258c71e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -86,7 +86,7 @@ EnableMsgC1eOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -134,7 +134,7 @@ IsMsgBasedC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Message-based C1e
*
@@ -172,7 +172,7 @@ InitializeMsgBasedC1eFeature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable message-based C1e on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h
index 145db2c..f3fc442 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c
index c036dee..305a420 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -960,7 +960,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
index d25d580..ee2a699 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
@@ -99,7 +99,7 @@ typedef struct {
IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
} S_CPU_AMD_PSTATE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -121,7 +121,7 @@ typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c
index 973e031..666d20b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c
@@ -135,7 +135,7 @@ ReleaseSlitBuffer (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -159,7 +159,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -184,7 +184,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -320,7 +320,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -348,7 +348,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -369,7 +369,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
index 3cd7d8c..005e193 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
@@ -142,7 +142,7 @@ GetAcpiSratMain (
IN OUT VOID **SratPtr
);
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -165,7 +165,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -188,7 +188,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -299,7 +299,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -510,7 +510,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -546,7 +546,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c
index cb09ad0..62523e5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -131,7 +131,7 @@ IsSwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h
index 96c3cac..3ea9aea 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if software C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
/// Reference to a Method
typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable software C1e.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
index 4ecdf38..80c8414 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
@@ -97,7 +97,7 @@ GetAcpiWheaMain (
IN OUT VOID **WheaCmcPtr
);
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -119,7 +119,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -145,7 +145,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -243,7 +243,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
index 0897309..b7728a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
@@ -150,7 +150,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -183,7 +183,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -280,7 +280,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -372,7 +372,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -467,7 +467,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -510,7 +510,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -556,7 +556,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -640,7 +640,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -701,7 +701,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -761,7 +761,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -867,7 +867,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -975,7 +975,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -1028,7 +1028,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1084,7 +1084,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1105,7 +1105,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1129,7 +1129,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1154,7 +1154,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1178,7 +1178,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1202,7 +1202,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c
index 65e91f4..a9dc386 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c
@@ -93,7 +93,7 @@ SetRegistersFromTablesAtEarly (
extern BUILD_OPT_CFG UserOptions;
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -154,7 +154,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -185,7 +185,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -258,7 +258,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -289,7 +289,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -340,7 +340,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Family Specific Workaround Register Entry.
*
@@ -369,7 +369,7 @@ SetRegisterForFamSpecificWorkaroundEntry (
Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers using BKDG values.
*
@@ -424,7 +424,7 @@ SetRegisterForHtPhyEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program a range of HT Phy PCI registers using BKDG values.
*
@@ -489,7 +489,7 @@ SetRegisterForHtPhyRangeEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -510,7 +510,7 @@ IsDeemphasisLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, for the current node and real link number.
*
@@ -559,7 +559,7 @@ LookupPackageLink (
return PackageLink;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the platform's specified deemphasis levels for the current link.
*
@@ -615,7 +615,7 @@ GetLinkDeemphasis (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program Deemphasis registers using BKDG values, for the platform specified levels.
*
@@ -706,7 +706,7 @@ SetRegisterForDeemphasisEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers which have complex frequency dependencies.
*
@@ -814,7 +814,7 @@ SetRegisterForHtPhyFreqEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -852,7 +852,7 @@ SetRegisterForPerformanceProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Phy Performance Profile Register Entry.
*
@@ -888,7 +888,7 @@ SetRegisterForHtPhyProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host PCI Register Entry.
*
@@ -947,7 +947,7 @@ SetRegisterForHtHostEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host Performance PCI Register Entry.
*
@@ -989,7 +989,7 @@ SetRegisterForHtHostPerfEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the HT Link Token Count registers.
*
@@ -1068,7 +1068,7 @@ SetRegisterForHtLinkTokenEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -1109,7 +1109,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -1150,7 +1150,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts PCI Register Entry.
*
@@ -1191,7 +1191,7 @@ SetRegisterForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts MSR Register Entry.
*
@@ -1224,7 +1224,7 @@ SetMsrForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Token Counts PCI Register Entry.
*
@@ -1268,7 +1268,7 @@ SetRegisterForTokenPciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link Feature PCI Register Entry.
*
@@ -1341,7 +1341,7 @@ SetRegisterForHtFeaturePciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link PCI Register Entry.
*
@@ -1398,7 +1398,7 @@ SetRegisterForHtLinkPciEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -1492,7 +1492,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -1540,7 +1540,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -1584,7 +1584,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -1619,7 +1619,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -1702,7 +1702,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
index e2c7e14..9d89946 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
@@ -120,11 +120,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -162,11 +162,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -622,11 +622,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -896,11 +896,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -950,11 +950,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -981,11 +981,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -1047,11 +1047,11 @@ typedef struct {
FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
index 3255252..29f478d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
@@ -192,7 +192,7 @@ ExecuteFinalHltInstruction (
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -276,7 +276,7 @@ LocalApicInitialization (
LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -300,7 +300,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -448,7 +448,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -477,7 +477,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -502,7 +502,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -526,7 +526,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -547,7 +547,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -653,7 +653,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -705,7 +705,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -772,7 +772,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -818,7 +818,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -893,7 +893,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -974,7 +974,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1121,7 +1121,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1159,7 +1159,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1207,7 +1207,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1236,7 +1236,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1267,7 +1267,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1289,7 +1289,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1322,7 +1322,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1347,7 +1347,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1389,7 +1389,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c
index d53d5c8..c05d1a0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c
@@ -72,7 +72,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -145,7 +145,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c
index 2a23215..8751a0c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c
@@ -89,7 +89,7 @@ SetBrandIdRegistersAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
@@ -284,7 +284,7 @@ SetBrandIdRegisters (
HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c
index 372c899..2a3a4c4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c
@@ -105,7 +105,7 @@ McaInitializationAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
@@ -128,7 +128,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -289,7 +289,7 @@ AmdCpuEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -334,7 +334,7 @@ McaInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -356,7 +356,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
@@ -392,7 +392,7 @@ ApUtilRunCodeOnAllLocalCoresAtEarly (
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c
index 016dc93..3a2685e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c
@@ -94,7 +94,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -131,7 +131,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -168,7 +168,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -246,7 +246,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -300,7 +300,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -362,7 +362,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c
index 479b315..d4c5a23 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c
@@ -127,7 +127,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -166,7 +166,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -189,7 +189,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -261,7 +261,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -288,7 +288,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -314,7 +314,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -337,7 +337,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -362,7 +362,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -389,7 +389,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -413,7 +413,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -456,7 +456,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
index 6137a69..c44c0eb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
@@ -803,7 +803,7 @@ typedef enum {
} FAMILY_CACHE_INIT_POLICY;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuGeneralServices.c
index e098f51..ac7131e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuGeneralServices.c
@@ -184,7 +184,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -228,7 +228,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -272,7 +272,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -314,7 +314,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -333,7 +333,7 @@ GetPlatformNumberOfSockets ()
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -351,7 +351,7 @@ GetPlatformNumberOfModules ()
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -395,7 +395,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -438,7 +438,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -483,7 +483,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -526,7 +526,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -548,7 +548,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
@@ -587,7 +587,7 @@ ModifyCurrentSocketPci (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -609,7 +609,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -688,7 +688,7 @@ GetNumberOfCompUnitsInCurrentModule (
return ComputeUnitCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -727,7 +727,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -774,7 +774,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -813,7 +813,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -836,7 +836,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -870,7 +870,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -910,7 +910,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -953,7 +953,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -987,7 +987,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -1016,7 +1016,7 @@ GetSystemDegree (
return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -1046,7 +1046,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1075,7 +1075,7 @@ IsBsp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the compute unit mapping algorithm.
*
@@ -1141,7 +1141,7 @@ GetComputeUnitMapping (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is current core the primary core of its compute unit?
*
@@ -1189,7 +1189,7 @@ IsCorePairPrimary (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Are the two specified cores shared in a compute unit?
*
@@ -1238,7 +1238,7 @@ AreCoresPaired (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c
index ecd8827..b1bfc51 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c
@@ -96,7 +96,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c
index 7230517..d4e116a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c
@@ -78,7 +78,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -100,7 +100,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -143,7 +143,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -174,7 +174,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -229,7 +229,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
index a01aa70..0f534f5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
@@ -115,7 +115,7 @@ LoadMicrocodePatchAtEarly (
);
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -174,7 +174,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -218,7 +218,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -278,7 +278,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -388,7 +388,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -417,7 +417,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
index 4b5e5da..196f9c2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
@@ -116,7 +116,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -192,7 +192,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -219,7 +219,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -246,7 +246,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -364,7 +364,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -404,7 +404,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
@@ -425,7 +425,7 @@ FinalizeAtPost (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection.
*
@@ -451,7 +451,7 @@ SetTscFreqSel (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection to all cores.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c
index 347670b..64bd9a2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c
@@ -99,7 +99,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -156,7 +156,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -195,7 +195,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -222,7 +222,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c
index a59b9cb..f946397 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -85,7 +85,7 @@ GetNextEvent (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -130,7 +130,7 @@ RunCodeOnAllSystemCore0sMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -170,7 +170,7 @@ GetNumberOfSystemPmStepsPtrMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the frequency that the northbridges must run.
*
@@ -269,7 +269,7 @@ GetSystemNbCofMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -318,7 +318,7 @@ GetSystemNbCofVidUpdateMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -461,7 +461,7 @@ GetMinNbCofMulti (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to return the next event log entry to the BSC.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c
index 3fa8ce1..bb0828a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -99,7 +99,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -124,7 +124,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -173,7 +173,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -202,7 +202,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
index ead0fff..2f698cb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -99,7 +99,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -144,7 +144,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
@@ -194,7 +194,7 @@ IsWarmReset (
return WarmReset;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
index 4906e91..70b3a56 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
@@ -103,7 +103,7 @@ InsertFreeSpaceNode (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -232,7 +232,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -412,7 +412,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -544,7 +544,7 @@ HeapDeallocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -652,7 +652,7 @@ HeapLocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the heap base address
*
@@ -714,7 +714,7 @@ HeapGetBaseAddress (
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DeleteFreeSpaceNode
@@ -773,7 +773,7 @@ DeleteFreeSpaceNode (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InsertFreeSpaceNode
@@ -826,7 +826,7 @@ InsertFreeSpaceNode (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c
index 5baf82d..72c7956 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c
@@ -99,7 +99,7 @@ AllocateExecutionCacheInitializer (
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -119,7 +119,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -147,7 +147,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -182,7 +182,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
index 38c3ade..1ddd79d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
@@ -112,7 +112,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
index a0a07fe..f265f2c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
@@ -90,7 +90,7 @@ AmdLatePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -184,7 +184,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
index 455648a..fee7e20 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
@@ -109,7 +109,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
index 616a980..a3cce2f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
@@ -89,7 +89,7 @@ AmdPostPlatformConfigInit (
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -197,7 +197,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitRecovery.c
index 28008e6..409f828 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitRecovery.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
@@ -124,7 +124,7 @@ AmdInitRecovery (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initialize defaults and options for Amd Init Reset.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
index bc18566..a9b9dfc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
@@ -90,7 +90,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -114,7 +114,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -220,7 +220,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c
index e7c7b0b..ad13dc7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -166,7 +166,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -197,7 +197,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
index 774fdcc..2e3d371 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G3_DXE)
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -123,7 +123,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
index 8f16ec4..3e17d81 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
@@ -84,7 +84,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -159,7 +159,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -191,7 +191,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3LateRestore stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
index ed50dea..fcecf23 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
@@ -102,7 +102,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -282,7 +282,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -315,7 +315,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -361,7 +361,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
index b7da89e..2abf1a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
@@ -73,7 +73,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
index d27f817..82b399b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
@@ -72,7 +72,7 @@ FchTaskDummy (
IN VOID *DataPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return TRUE.
*
@@ -85,7 +85,7 @@ CommonReturnTrue (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -97,7 +97,7 @@ CommonReturnFalse (VOID)
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -110,7 +110,7 @@ CommonReturnZero8 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -123,7 +123,7 @@ CommonReturnZero32 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -136,7 +136,7 @@ CommonReturnZero64 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -148,7 +148,7 @@ CommonReturnNULL (VOID)
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -161,7 +161,7 @@ CommonReturnAgesaSuccess (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -171,7 +171,7 @@ CommonVoid (VOID)
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
@@ -183,7 +183,7 @@ CommonAssert (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c
index 944cc17..616e679 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c
@@ -77,7 +77,7 @@ extern CONST UINTN InitializerCount;
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -222,7 +222,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
index 33ffd37..020c3bc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
@@ -82,7 +82,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -99,7 +99,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -116,7 +116,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -142,7 +142,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
index 655b648..7fe892c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
@@ -78,7 +78,7 @@ S3SaveStateExtendTableLenth (
IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -94,7 +94,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -110,7 +110,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -138,7 +138,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -192,7 +192,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -220,7 +220,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -284,7 +284,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -358,7 +358,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -434,7 +434,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 info opcode
*
@@ -490,7 +490,7 @@ S3SaveStateSaveInfoOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 dispatch opcode
*
@@ -554,7 +554,7 @@ S3SaveStateSaveDispatchOp (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
@@ -599,7 +599,7 @@ S3SaveDebugOpcodeString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
index e971abe..cfeea39 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
@@ -44,7 +44,7 @@
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchSmmAcpiOn - Config Fch during ACPI_ON
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
index 838fa9f..8a1d865 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
@@ -291,7 +291,7 @@ RwAlink (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -322,7 +322,7 @@ ReadPmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO
*
@@ -353,7 +353,7 @@ WritePmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio - Read/Write PMIO
*
@@ -383,7 +383,7 @@ RwPmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO2
*
@@ -415,7 +415,7 @@ ReadPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO 2
*
@@ -447,7 +447,7 @@ WritePmio2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio2 - Read/Write PMIO2
*
@@ -477,7 +477,7 @@ RwPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read BIOSRAM
*
@@ -508,7 +508,7 @@ ReadBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write BIOSRAM
*
@@ -539,7 +539,7 @@ WriteBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Record SMI Status
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
index 0e191c1..7426500 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
@@ -43,7 +43,7 @@
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
*
@@ -89,7 +89,7 @@ ProgramPciByteTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c
index ae8aa36..b742796 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c
@@ -61,7 +61,7 @@ FchInitEnvEc (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* EnterEcConfig - Force EC into Config mode
*
@@ -83,7 +83,7 @@ EnterEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ExitEcConfig - Force EC exit Config mode
*
@@ -105,7 +105,7 @@ ExitEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ReadEc8 - Read EC register data
*
@@ -131,7 +131,7 @@ ReadEc8 (
LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwEc8 - Read/Write EC register
*
@@ -158,7 +158,7 @@ RwEc8 (
WriteEc8 (Address, &Result, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* WriteEc8 - Write date into EC register
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
index 4fe936f..69ec71c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
@@ -50,7 +50,7 @@
extern FCH_TASK_ENTRY *FchInitEnvTaskTable[];
extern FCH_INTERFACE FchInterfaceDefault;
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitEnv - Config Fch before PCI emulation
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
index 58e24f7..5ec38d1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
@@ -50,7 +50,7 @@
extern FCH_TASK_ENTRY *FchInitLateTaskTable[];
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitLate - Prepare Fch to boot to OS.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
index 41fb5f8..2e4e3cc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
@@ -48,7 +48,7 @@ extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[];
extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[];
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
*
@@ -70,7 +70,7 @@ FchInitS3EarlyRestore (
FchDataPtr->Misc.S3Resume = 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c
index 13505c3..6775418 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c
@@ -75,7 +75,7 @@ GnbCommonFeatureStub (
-/*----------------------------------------------------------------------------------------*/
+
/**
* DIspathc feature tanle
*
@@ -101,7 +101,7 @@ GnbLibDispatchFeatures (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Feature stub function
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
index 1594fae..a89cfd5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
@@ -107,7 +107,7 @@ UINT8 DdiLaneConfigArray [][4] = {
{23, 20, 5, 5},
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -169,7 +169,7 @@ GfxFmMapEngineToDisplayPath (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific integrated info table init
*
@@ -199,7 +199,7 @@ GfxFmIntegratedInfoTableInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific address swizzle settings.
*
@@ -235,7 +235,7 @@ GfxFmGmcAddressSwizzel (
}
}
-/*----------------------------------------------------------------------------------------*/
+
VOID
GfxFmGmcAllowPstateHigh (
@@ -244,7 +244,7 @@ GfxFmGmcAllowPstateHigh (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate COF for DFS out of Main PLL
*
@@ -266,7 +266,7 @@ GfxFmCalculateClock (
return GfxLibCalculateClk (Did, MainPllFreq10kHz);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set idle voltage mode for GFX
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c
index 07b4c6d..b23550b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c
@@ -76,7 +76,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable GMM Access
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
index 72c4e75..b47abfc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
@@ -178,7 +178,7 @@ extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr;
extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr;
extern UINT8 NumberOfChannels;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GMC memory address translation
*
@@ -214,7 +214,7 @@ GfxGmcSetMemoryAddressTranslation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable CLock Gating
*
@@ -236,7 +236,7 @@ GfxGmcDisableClockGating (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Register Engine
*
@@ -259,7 +259,7 @@ GfxGmcInitializeRegisterEngine (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get DCT channel info
*
@@ -312,7 +312,7 @@ GfxGmcDctMemoryChannelInfo (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Sequencer Model
*
@@ -416,7 +416,7 @@ GfxGmcInitializeSequencerModel (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Frame Buffer Location
*
@@ -493,7 +493,7 @@ GfxGmcInitializeFbLocation (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Secure Garlic Access
*
@@ -524,7 +524,7 @@ GfxGmcSecureGarlicAccess (
GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Performance setting
*
@@ -546,7 +546,7 @@ GfxGmcPerformanceTuning (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc. Initialization
*
@@ -574,7 +574,7 @@ GfxGmcMiscInit (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock critical registers
*
@@ -598,7 +598,7 @@ GfxGmcLockCriticalRegisters (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Remove blackout
*
@@ -620,7 +620,7 @@ GfxGmcRemoveBlackout (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable clock Gating
*
@@ -642,7 +642,7 @@ GfxGmcEnableClockGating (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UMA steering
*
@@ -658,7 +658,7 @@ GfxGmcUmaSteering (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize C6 aperture
*
@@ -700,7 +700,7 @@ GfxGmcInitializeC6Aperture (
);
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Power Gating
*
@@ -751,7 +751,7 @@ GfxGmcInitializePowerGating (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GMC
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c
index 3fa0c0e..708774b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c
@@ -73,7 +73,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Env Post.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c
index 7211c36..300f7b8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c
@@ -77,7 +77,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Mid Post.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c
index 0edc8e0..c1847c1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Post.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
index d78a248..c02aa09 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
@@ -193,7 +193,7 @@ GfxIntegratedInfoTableInit (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get CSR phy self refresh power down mode.
*
@@ -220,7 +220,7 @@ GfxLibGetCsrPhySrPllPdMode (
return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get disable DLL shutdown in self-refresh mode.
*
@@ -247,7 +247,7 @@ GfxLibGetDisDllShutdownSR (
return D18F2x090.Field.DisDllShutdownSR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
* GMC FB access requred
@@ -278,7 +278,7 @@ GfxIntegratedInfoTableEntry (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
*
@@ -390,7 +390,7 @@ GfxIntegratedInfoTableInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Dispclk <-> VID table
*
@@ -419,7 +419,7 @@ GfxIntegratedInfoInitDispclkTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Sclk <-> VID table
*
@@ -513,7 +513,7 @@ GfxIntegratedInfoInitSclkTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init HTC Data
*
@@ -540,7 +540,7 @@ GfxFillHtcData (
IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init NbPstateVid
*
@@ -579,7 +579,7 @@ GfxFillNbPStateVid (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init M3 Arbitration Control values.
*
@@ -599,7 +599,7 @@ GfxFillM3ArbritrationControl (
LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init M3 Arbitration Control values.
*
@@ -618,7 +618,7 @@ GfxFillSbMmioBaseAddress (
IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fill in NCLK info
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c
index d96d697..e5879c0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate main PLL VCO
*
@@ -101,7 +101,7 @@ GfxLibGetMainPllFreq (
return MainPllFreq;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate clock from main VCO
*
@@ -135,7 +135,7 @@ GfxLibCalculateClk (
return (((MainPllVco * 100) + (Divider - 1)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate did from main VCO
*
@@ -170,7 +170,7 @@ GfxLibCalculateDid (
return Did;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max non 0 VID index
*
@@ -206,7 +206,7 @@ GfxLibMaxVidIndex (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get min SCLK
*
@@ -231,7 +231,7 @@ GfxLibGetMinSclk (
return MinSclkClk;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get min WRCK
*
@@ -264,7 +264,7 @@ GfxLibGetWrCk (
return 100 * 100 / WrCk;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate NCLK clock from main VCO
*
@@ -296,7 +296,7 @@ GfxLibCalculateNclk (
return ((MainPllVco * 100) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate idle NCLK clock from main VCO
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c
index 3e0fd4f..77a6332 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c
@@ -71,7 +71,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM register
*
@@ -94,7 +94,7 @@ GmmRegisterWrite (
GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GMM register
*
@@ -116,7 +116,7 @@ GmmRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM register field
*
@@ -148,7 +148,7 @@ GmmRegisterWriteField (
GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM registers table
*
@@ -174,7 +174,7 @@ GmmRegisterTableWrite (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c
index 6836938..60e87a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c
@@ -78,7 +78,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GFX straps.
*
@@ -173,7 +173,7 @@ GfxStrapsInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable integrated GFX controller
*
@@ -221,7 +221,7 @@ GfxDisableController (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request GFX boot up voltage
*
@@ -252,7 +252,7 @@ GfxSetBootUpVoltage (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set idle voltage mode for GFX
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c
index 7c781f4..f3d8a7b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c
@@ -70,7 +70,7 @@ extern OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[];
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early
*
@@ -90,7 +90,7 @@ GnbInitAtEarly (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early before CPU
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c
index a97885b..d535d42 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c
@@ -68,7 +68,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -101,7 +101,7 @@ GnbInitDataStructAtEnvDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c
index 918c942..11d83e4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c
@@ -69,7 +69,7 @@ extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[];
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c
index 9bd4c3b..9d93c3f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c
@@ -69,7 +69,7 @@ extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[];
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c
index b2a40aa..cad0041 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c
@@ -70,7 +70,7 @@ extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[];
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -91,7 +91,7 @@ GnbInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c
index 8331a3b..f82413a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c
@@ -65,7 +65,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
index 4ff31b1..ad3c578 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
@@ -107,7 +107,7 @@ GnbCableSafeIsSupported (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Cable Safe module entry
*
@@ -188,7 +188,7 @@ GnbCableSafeEntry (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port Gen capability
*
@@ -215,7 +215,7 @@ GnbCableSafeGetConnectorInfoArrayCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if feature supported
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 56ae612..86d2151 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -84,7 +84,7 @@ GnbLibPciIndirectReadField (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers
*
@@ -110,7 +110,7 @@ GnbLibPciIndirectRead (
GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers field
*
@@ -139,7 +139,7 @@ GnbLibPciIndirectReadField (
*Value = (*Value >> FieldOffset) & Mask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers
*
@@ -167,7 +167,7 @@ GnbLibPciIndirectWrite (
GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers field
*
@@ -201,7 +201,7 @@ GnbLibPciIndirectWriteField (
GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write GNB indirect registers field
*
@@ -237,7 +237,7 @@ GnbLibPciIndirectRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI registers
*
@@ -264,7 +264,7 @@ GnbLibPciRMW (
GnbLibPciWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write I/O registers
*
@@ -291,7 +291,7 @@ GnbLibIoRMW (
GnbLibIoWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Indirect IO block read
*
@@ -324,7 +324,7 @@ GnbLibIndirectIoBlockRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOAPIC ID
*
@@ -346,7 +346,7 @@ GnbLiGetIoapicId (
return (UINT8) (Value >> 24);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write MMIO registers
*
@@ -372,7 +372,7 @@ GnbLibMemRMW (
Data = (Data & Mask) | Value;
GnbLibMemWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of sockets
*
@@ -390,7 +390,7 @@ GnbGetNumberOfSockets (
return GetPlatformNumberOfSockets ();
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of Silicons on the socket
*
@@ -410,7 +410,7 @@ GnbGetNumberOfSiliconsOnSocket (
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCI Address
*
@@ -434,7 +434,7 @@ GnbGetPciAddress (
return Gnb;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if anything plugged in socket
*
@@ -455,7 +455,7 @@ GnbIsDevicePresentInSocket (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Claculate power of number
*
@@ -482,7 +482,7 @@ GnbLibPowerOf (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search buffer for pattern
*
@@ -520,7 +520,7 @@ GnbLibFind (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
@@ -572,7 +572,7 @@ GnbLibDebugDumpBuffer (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index 3cf57b9..76326a3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -68,7 +68,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU (DCT) indirect registers
*
@@ -96,7 +96,7 @@ GnbLibCpuPciIndirectRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write CPU (DCT) indirect registers
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index 210400b..fccaa8a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -65,7 +65,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -99,7 +99,7 @@ GnbAllocateHeapBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap and clear it
*
@@ -127,7 +127,7 @@ GnbAllocateHeapBufferAndClear (
return Buffer;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index d627e41..d027d65 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -67,10 +67,10 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*---------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
+
/**
* Write I/O Port
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 135bf0f..98c9cfe 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write Memory/MMIO registers
*
@@ -94,7 +94,7 @@ GnbLibMemWrite (
LibAmdMemWrite (Width, Address, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Memory/MMIO registers
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
index ef3c865..e43c124 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -60,7 +60,7 @@ GnbLibFindPcieExtendedCapability (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device present
*
@@ -88,7 +88,7 @@ GnbLibPciIsDevicePresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is bridge
*
@@ -115,7 +115,7 @@ GnbLibPciIsBridgeDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is multifunction
*
@@ -142,7 +142,7 @@ GnbLibPciIsMultiFunctionDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is PCIe device
*
@@ -169,7 +169,7 @@ GnbLibPciIsPcieDevice (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCI capability pointer
*
@@ -207,7 +207,7 @@ GnbLibFindPciCapability (
}
return CapabilityPtr;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCIe extended capability pointer
*
@@ -245,7 +245,7 @@ GnbLibFindPcieExtendedCapability (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Scan range of device on PCI bus.
*
@@ -256,7 +256,7 @@ GnbLibFindPcieExtendedCapability (
* @param[in] ScanData Supporting data
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
@@ -313,7 +313,7 @@ GnbLibPciScan (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan all subordinate buses
*
@@ -339,7 +339,7 @@ GnbLibPciScanSecondaryBus (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe device type
*
@@ -350,7 +350,7 @@ GnbLibPciScanSecondaryBus (
*
* @retval PCIE_DEVICE_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_DEVICE_TYPE
GnbLibGetPcieDeviceType (
@@ -369,7 +369,7 @@ GnbLibGetPcieDeviceType (
return PcieNotPcieDevice;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save config space area
*
@@ -382,7 +382,7 @@ GnbLibGetPcieDeviceType (
* @param[in] StdHeader Standard header.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibS3SaveConfigSpace (
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
index 03c2910..cb97dc7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI registers
*
@@ -95,7 +95,7 @@ GnbLibPciWrite (
LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI registers
*
@@ -122,7 +122,7 @@ GnbLibPciRead (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll PCI reg
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
index c3f76ed..b1f5349 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
@@ -56,7 +56,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall and save to script table
*
@@ -77,7 +77,7 @@ GnbLibStallS3Save (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall
*
@@ -104,7 +104,7 @@ GnbLibStall (
} while (TimeStampDelta < Microsecond);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Stall S3 scrept
*
@@ -123,7 +123,7 @@ GnbLibStallS3Script (
{
GnbLibStall (* ((UINT32*) Context), StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Time stamp in us
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c
index 73f77ce..1113a8d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c
@@ -71,7 +71,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process table
*
@@ -95,7 +95,7 @@ GnbProcessTable (
return GnbProcessTableExt (0, 0, Table, Property, Flags, Protocol, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process table
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index c6d067c..f9da01a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -69,7 +69,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -104,7 +104,7 @@ PcieFmConfigureEnginesLaneAllocation (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -141,7 +141,7 @@ PcieFmGetCoreConfigurationValue (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -176,7 +176,7 @@ PcieFmCheckPortPciDeviceMapping (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -208,7 +208,7 @@ PcieFmDebugGetCoreConfigurationString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -238,7 +238,7 @@ PcieFmDebugGetWrapperNameString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -269,7 +269,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
@@ -304,7 +304,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -335,7 +335,7 @@ PcieFmMapPortPciAddress (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -366,7 +366,7 @@ PcieFmGetComplexDataLength (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -393,7 +393,7 @@ PcieFmBuildComplexConfiguration (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -424,7 +424,7 @@ PcieFmGetLinkSpeedCap (
return PcieGen1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get native PHY lane bitmap
*
@@ -454,7 +454,7 @@ PcieFmGetNativePhyLaneBitmap (
return 0x0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SB port info
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
index 5a4a2f3..4812b96 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -79,7 +79,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get UMA info
*
@@ -109,7 +109,7 @@ GfxGetUmaInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate UMA configuration data
*
@@ -138,7 +138,7 @@ GfxLocateConfigData (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 87b3f79..4d8aa10 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -75,7 +75,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate UMA configuration data
*
@@ -129,7 +129,7 @@ GfxConfigPostInterface (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
index 3e1d094..6f1c951 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -85,7 +85,7 @@ GfxScanPcieDevice (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get information about all discrete GFX card in system
*
@@ -116,7 +116,7 @@ GfxGetDiscreteCardInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index a13d7d8..2cd6eb3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -218,7 +218,7 @@ UINT8 ConnectorNumerArray[] = {
// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS)
6, 1, 6, 6, 6, 1, 1, 2
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -292,7 +292,7 @@ EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
0x260,
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -326,7 +326,7 @@ GfxIntegratedExtDisplayDeviceInfo (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors
*
@@ -374,7 +374,7 @@ GfxIntegratedEnumerateAllConnectors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -412,7 +412,7 @@ GfxIntegratedDdiInterfaceCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -492,7 +492,7 @@ GfxIntegratedEnumConnectorsForDevice (
return ConnectorEnumInfo.Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -547,7 +547,7 @@ GfxIntegratedCopyDisplayInfo (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump display path settings
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 2a7e34d..1ca7802 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -177,7 +177,7 @@ GfxIntegratedDebugDumpPpTable (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing tdp
*
@@ -216,7 +216,7 @@ GfxPowerPlayLocateTdp (
return PpFuses->SclkDpmTdpLimit[DpmIndex];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new software state
*
@@ -240,7 +240,7 @@ GfxPowerPlayCreateSwState (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new DPM state
*
@@ -273,7 +273,7 @@ GfxPowerPlayCreateDpmState (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing or Create new DPM state
*
@@ -302,7 +302,7 @@ GfxPowerPlayAddDpmState (
return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add reference to DPM state for SW state
*
@@ -320,7 +320,7 @@ GfxPowerPlayAddDpmStateToSwState (
SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy SW state info to PPTable
*
@@ -358,7 +358,7 @@ GfxPowerPlayCopyStateInfo (
StateArray->ucNumEntries = SwStateIndex;
return (UINT32) ((UINT8*) States - (UINT8*) StateArray);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy clock info to PPTable
*
@@ -392,7 +392,7 @@ GfxPowerPlayCopyClockInfo (
return sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * (ClkStateIndex) - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy non clock info to PPTable
*
@@ -427,7 +427,7 @@ GfxPowerPlayCopyNonClockInfo (
return sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if fused state valid
*
@@ -455,7 +455,7 @@ GfxPowerPlayIsFusedStateValid (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SW state calssification from fuses
*
@@ -507,7 +507,7 @@ GfxPowerPlayGetClassificationFromFuses (
return Classification;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SW state calssification2 from fuses
*
@@ -541,7 +541,7 @@ GfxPowerPlayGetClassification2FromFuses (
return Classification2;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build PP table
*
@@ -661,7 +661,7 @@ GfxPowerPlayBuildTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump PP table
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
index 725546e..65bfe02 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
@@ -76,7 +76,7 @@ extern BUILD_OPT_CFG UserOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if GFX controller fused off
*
@@ -93,7 +93,7 @@ GfxLibIsControllerPresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Gfx SSID Registers
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index c01f9b8..782caaf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -94,7 +94,7 @@ IOMMU_IVRS_HEADER IvrsHeader = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build IVRS table
*
@@ -164,7 +164,7 @@ GnbIommuIvrsTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump IVRS table
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
index d88e03f..13f25fd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for device range
*
@@ -105,7 +105,7 @@ GnbIvhdAddDeviceRangeEntry (
Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for aliased range
*
@@ -144,7 +144,7 @@ GnbIvhdAddDeviceAliasRangeEntry (
Ivhd->Length += (sizeof (IVHD_GENERIC_ENTRY) + Padding);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for special device
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index 3d8a3f9..a9130e4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB set top of memory
*
@@ -138,7 +138,7 @@ GnbSetTom (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Avoid LPC DMA transaction deadlock
*
@@ -175,7 +175,7 @@ GnbLpcDmaDeadlockPrevention (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Dynamic Wake
* ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
@@ -218,7 +218,7 @@ GnbOrbDynamicWake (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock NB registers
*
@@ -246,7 +246,7 @@ GnbLock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -278,7 +278,7 @@ GnbClumpUnitID (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of highest SCLK VID
*
@@ -314,7 +314,7 @@ GnbLocateHighestVidIndex (
return MaxVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of lowest SCLK VID
*
@@ -348,7 +348,7 @@ GnbLocateLowestVidIndex (
return MinVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the highest SCLK VID (high voltage)
*
@@ -372,7 +372,7 @@ GnbLocateHighestVidCode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the lowest SCLK VID (low voltage)
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
index 843fe0e..b1b4557 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -120,7 +120,7 @@ PcieAlibSetSclkVid (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create ACPI ALIB SSDT table
*
@@ -140,7 +140,7 @@ PcieAlibFeature (
return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
@@ -317,7 +317,7 @@ PcieAlibBuildAcpiTable (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -345,7 +345,7 @@ PcieAlibSetPortMaxSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -376,7 +376,7 @@ PcieAlibSetPortOverrideSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init port info
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index 4631ba0..1c394cf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -110,7 +110,7 @@ PcieConfigProcessUserConfig (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration data
*
@@ -142,7 +142,7 @@ PcieConfigurationInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration data
*
@@ -244,7 +244,7 @@ PcieConfigBuildData (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -396,7 +396,7 @@ PcieConfigProcessUserConfig (
return ResultComplexConfig;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -423,7 +423,7 @@ PcieLocateConfigurationData (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attache descriptors
*
@@ -450,7 +450,7 @@ PcieConfigAttachDescriptors (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach configurations of two GNB to each other.
*
@@ -477,7 +477,7 @@ PcieConfigAttachComplexes (
PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update configuration data
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index d6c087a..0f621db 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* get Master Lane of PCIe port engine
*
@@ -97,7 +97,7 @@ PcieConfigGetPcieEngineMasterLane (
return MasterLane;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of core lanes
*
@@ -117,7 +117,7 @@ PcieConfigGetNumberOfCoreLane (
return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable engine
*
@@ -137,7 +137,7 @@ PcieConfigDisableEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable all engines on wrapper
*
@@ -163,7 +163,7 @@ PcieConfigDisableAllEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get engine PHY lanes bitmap
*
@@ -185,7 +185,7 @@ PcieConfigGetEnginePhyLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of phy lanes
*
@@ -209,7 +209,7 @@ PcieConfigGetNumberOfPhyLane (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get port configuration signature for given wrapper and core
*
@@ -238,7 +238,7 @@ PcieConfigGetConfigurationSignature (
return ConfigurationSignature;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check Port Status
*
@@ -257,7 +257,7 @@ PcieConfigCheckPortStatus (
return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set/Reset port status
*
@@ -280,7 +280,7 @@ PcieConfigUpdatePortStatus (
return Engine->InitStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all descriptor of specific type
*
@@ -318,7 +318,7 @@ PcieConfigRunProcForAllDescriptors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all wrappers in topology
*
@@ -356,7 +356,7 @@ PcieConfigRunProcForAllWrappers (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all engine in topology
*
@@ -390,7 +390,7 @@ PcieConfigRunProcForAllEngines (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get parent descriptor of specific type
*
@@ -414,7 +414,7 @@ PcieConfigGetParent (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get child descriptor of specific type
*
@@ -438,7 +438,7 @@ PcieConfigGetChild (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get peer descriptor of specific type
*
@@ -462,7 +462,7 @@ PcieConfigGetPeer (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump engine configuration
*
@@ -541,7 +541,7 @@ PcieConfigEngineDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump wrapper configuration
*
@@ -579,7 +579,7 @@ PcieConfigWrapperDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump configuration to debug out
*
@@ -648,7 +648,7 @@ PcieConfigDebugDump (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to debug out
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index acb374a..29eac30 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -73,7 +73,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of complexes in platform topology configuration
*
@@ -99,7 +99,7 @@ PcieInputParserGetNumberOfComplexes (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of PCIe engines in given complex
*
@@ -126,7 +126,7 @@ PcieInputParserGetLengthOfPcieEnginesList (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of DDI engines in given complex
*
@@ -154,7 +154,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of engines in given complex
*
@@ -176,7 +176,7 @@ PcieInputParserGetNumberOfEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -196,7 +196,7 @@ PcieInputParserGetComplexDescriptor (
return &ComplexList[Index];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -225,7 +225,7 @@ PcieInputParserGetComplexDescriptorOfSocket (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Engine descriptor from given complex by index
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index 67a01ab..00b1b5b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -136,7 +136,7 @@ PcieAllocateEngine (
IN UINT8 DescriptorIndex,
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -186,7 +186,7 @@ PcieMapTopologyOnComplex (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -266,7 +266,7 @@ PcieEnginesToWrapper (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
*
@@ -299,7 +299,7 @@ PcieCheckDescriptorMapsToWrapper (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Engine to be allocated.
*
@@ -317,7 +317,7 @@ PcieAllocateEngine (
Engine->Scratch = DescriptorIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -428,7 +428,7 @@ PcieMapTopologyOnWrapper (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize engine data
*
@@ -466,7 +466,7 @@ PcieMapInitializeEngineData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -497,7 +497,7 @@ PcieCheckPortPciDeviceMapping (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -559,7 +559,7 @@ PcieMapPortsPciAddresses (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* If link width from user descriptor less or equal to link width of engine
*
@@ -605,7 +605,7 @@ PcieCheckLanesMatch (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
index 4296089..dd14a02 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
@@ -102,7 +102,7 @@ PcieAspmGetPmCapability (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable PCIE Advance state power management
*
@@ -128,7 +128,7 @@ PcieLinkAspmEnable (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -193,7 +193,7 @@ PcieAspmCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on PCIe device function
*
@@ -204,7 +204,7 @@ PcieAspmCallback (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnFunction (
IN PCI_ADDR Function,
@@ -225,7 +225,7 @@ PcieAspmEnableOnFunction (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on all function of PCI device
*
@@ -236,7 +236,7 @@ PcieAspmEnableOnFunction (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnDevice (
IN PCI_ADDR Device,
@@ -255,7 +255,7 @@ PcieAspmEnableOnDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on link
*
@@ -313,7 +313,7 @@ PcieAspmEnableOnLink (
-/**----------------------------------------------------------------------------------------*/
+
/**
* Port/Endpoint ASMP capability
*
@@ -324,7 +324,7 @@ PcieAspmEnableOnLink (
*
* @retval PCIE_ASPM_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_ASPM_TYPE
PcieAspmGetPmCapability (
IN PCI_ADDR Device,
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
index 36dcfbb..c8b053a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -94,7 +94,7 @@ UINT16 AspmBrDeviceTable[] = {
0x1B4B, 0x9123, (UINT16) ~(AspmL0s)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie ASPM Black List
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index 1fb5185..a5e1b16 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -81,7 +81,7 @@ PcieAspmGetMaxExitLatencyCallback (
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine ASPM L-state maximum exit latency for PCIe segment
*
@@ -108,7 +108,7 @@ PcieAspmGetMaxExitLatency (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
index 0f13b9e..bdb959c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
@@ -88,7 +88,7 @@ INT8 DeemphGen1Nom [] = { 42, 42, 0, 0, 42,
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane ganging
*
@@ -158,7 +158,7 @@ PciePhyApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Point "virtual" PLL clock picker away from PCIe
*
@@ -200,7 +200,7 @@ PciePhyAvertClockPickers (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PHY channel characteristic
*
@@ -271,7 +271,7 @@ PciePhyChannelCharacteristic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* DCC recalibration
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
index 7b9ff87..af1e735 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -85,7 +85,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply PIF ganging for all lanes for given wrapper
*
@@ -178,7 +178,7 @@ PciePifApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -224,7 +224,7 @@ PciePifPllPowerDown (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL init for DDI
*
@@ -268,7 +268,7 @@ PciePifPllInitForDdi (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for on PIF to indicate action completion
*
@@ -301,7 +301,7 @@ PciePollPifForCompeletion (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable fifo reset
*
@@ -332,7 +332,7 @@ PciePifDisableFifoReset (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program LS2 exit time
*
@@ -364,7 +364,7 @@ PciePifSetLs2ExitTime (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -406,7 +406,7 @@ PciePifSetPllModeForL1 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
@@ -439,7 +439,7 @@ PciePifSetRxDetectPowerMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll ramp up time
*
@@ -512,7 +512,7 @@ PciePifSetPllRampTime (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
@@ -555,7 +555,7 @@ PciePifPllPowerControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 4b52dcf..a355e6f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe port indirect register.
*
@@ -97,7 +97,7 @@ PciePortRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register.
*
@@ -131,7 +131,7 @@ PciePortRegisterWrite (
GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -166,7 +166,7 @@ PciePortRegisterWriteField (
PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -195,7 +195,7 @@ PciePortRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe port register.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
index f047176..c7bf48c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set completion timeout
*
@@ -110,7 +110,7 @@ PcieCompletionTimeout (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init hotplug port
*
@@ -188,7 +188,7 @@ PcieLinkInitHotplug (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set misc slot capability
*
@@ -221,7 +221,7 @@ PcieLinkSetSlotCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Safe mode to force link advertize Gen1 only capability in TS
*
@@ -251,7 +251,7 @@ PcieLinkSafeMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -276,7 +276,7 @@ PcieSetLinkWidthCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -364,7 +364,7 @@ PcieSetLinkSpeedCap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Force compliance
*
@@ -402,7 +402,7 @@ PcieForceCompliance (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slo power limit
*
@@ -433,7 +433,7 @@ PcieEnableSlotPowerLimit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM
*
@@ -465,7 +465,7 @@ PcieEnableAspm (
UINT8 L1State = 0x1b;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L1
*
@@ -486,7 +486,7 @@ PciePollLinkForL1Entry (
} while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L1
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index 1079ecf..0136f47 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes and plls
*
@@ -111,7 +111,7 @@ PciePwrPowerDownUnusedLanes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lane bitmam to enable PLL power down in L1
*
@@ -180,7 +180,7 @@ PcieLanesToPowerDownPllInL1 (
return LaneBitmapForPllOffInL1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Auto-Power Down electrical Idle detector
*
@@ -231,7 +231,7 @@ PciePwrAutoPowerDownElectricalIdleDetector (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clock gating
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 2875dde..5981f4c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -71,7 +71,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Gen1 voltage Index
*
@@ -103,7 +103,7 @@ PcieSiliconGetGen1VoltageIndex (
return Gen1VidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request Pcie voltage change
*
@@ -161,7 +161,7 @@ PcieSiliconRequestVoltage (
} while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Unhide all ports
*
@@ -195,7 +195,7 @@ PcieSiliconUnHidePorts (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide unused ports
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
index 2df357c..2dc9a4e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe timer timestamp
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index 15bd87f..b68dfbc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -79,7 +79,7 @@ PcieTopologyLocateMuxIndex (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for reconfiguration
*
@@ -130,7 +130,7 @@ PcieTopologyPrepareForReconfig (
UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate mux array index
*
@@ -155,7 +155,7 @@ PcieTopologyLocateMuxIndex (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply lane mux
*
@@ -247,7 +247,7 @@ PcieTopologyApplyLaneMux (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Select master PLL
*
@@ -331,7 +331,7 @@ PcieTopologySelectMasterPll (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -402,7 +402,7 @@ PcieTopologyExecuteReconfig (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
@@ -441,7 +441,7 @@ PcieTopologySetLinkReversal (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reduce link width
*
@@ -475,7 +475,7 @@ PcieTopologyReduceLinkWidth (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lanes enable/disable control
*
@@ -514,7 +514,7 @@ PcieTopologyLaneControl (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SRBM reset
*
@@ -551,7 +551,7 @@ PcieTopologyInitSrbmReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set core configuration according to PCIe port topology
*
@@ -606,7 +606,7 @@ PcieTopologySetCoreConfig (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Relinquish control to DDI for specific lanes
*
@@ -654,7 +654,7 @@ PcieSetDdiOwnPhy (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for PCIe lanes
*
@@ -696,7 +696,7 @@ PcieWrapSetTxS1CtrlForLaneMux (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for lane muxes
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 8535e24..63b2751 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -102,7 +102,7 @@ PcieUtilGetDdiEngineLaneBitMap (
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link state history from HW state machine
*
@@ -141,7 +141,7 @@ PcieUtilGetLinkHwStateHistory (
LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search array for specific pattern
*
@@ -181,7 +181,7 @@ PcieUtilSearchArray (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link reversed
*
@@ -214,7 +214,7 @@ PcieUtilIsLinkReversed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link width detected during training
*
@@ -262,7 +262,7 @@ PcieUtilGetLinkWidth (
return LinkWidth;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -329,7 +329,7 @@ PcieUtilGetPcieEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -370,7 +370,7 @@ PcieUtilGetDdiEngineLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of engine lane of requested type
*
@@ -452,7 +452,7 @@ PcieUtilGetEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of Wrapper lane of requested type
*
@@ -490,7 +490,7 @@ PcieUtilGetWrapperLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program port register table
*
@@ -534,7 +534,7 @@ PciePortProgramRegisterTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock registers
*
@@ -568,7 +568,7 @@ PcieLockRegisters (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -612,7 +612,7 @@ PcieUtilGlobalGenCapabilityCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine global GEN capability
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
index 576d2d8..d336292 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -53,7 +53,7 @@
#include "GnbPcieInitLibV1.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -74,7 +74,7 @@ PcieRegisterRead (
return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -99,7 +99,7 @@ PcieSiliconRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -129,7 +129,7 @@ PcieRegisterWrite (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -161,7 +161,7 @@ PcieSiliconRegisterWrite (
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register field.
*
@@ -190,7 +190,7 @@ PcieRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register field.
*
@@ -226,7 +226,7 @@ PcieRegisterWriteField (
PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
@@ -260,7 +260,7 @@ PcieRegisterRMW (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
index 8170342..67a71b7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -115,7 +115,7 @@ PcieTrainingDebugDumpPortState (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set link State
*
@@ -146,7 +146,7 @@ PcieTrainingSetPortState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set state for all engines connected to same reset ID
*
@@ -172,7 +172,7 @@ PcieSetResetStateOnEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Assert GPIO port reset.
*
@@ -203,7 +203,7 @@ PcieTrainingAssertReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for reset duration
*
@@ -226,7 +226,7 @@ PcieTrainingCheckResetDuration (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Deassert GPIO port reset.
*
@@ -250,7 +250,7 @@ PcieTrainingDeassertReset (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for after reset deassertion timeout
*
@@ -274,7 +274,7 @@ PcieTrainingCheckResetTimeout (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Release training
*
@@ -308,7 +308,7 @@ PcieTrainingRelease (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect presence of any EP on the link
*
@@ -341,7 +341,7 @@ PcieTrainingDetectPresence (
UINT8 FailPattern1 [] = {0x2a, 0x6};
UINT8 FailPattern2 [] = {0x2a, 0x9};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect Link State
*
@@ -381,7 +381,7 @@ PcieTrainingDetectLinkState (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Broken Lane
*
@@ -419,7 +419,7 @@ PcieTrainingBrokenLine (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen2
*
@@ -455,7 +455,7 @@ PcieTrainingGen2Fail (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Link in L0
*
@@ -473,7 +473,7 @@ PcieCheckLinkL0 (
{
PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen X
*
@@ -509,7 +509,7 @@ PcieTrainingCheckVcoNegotiation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if for GFX workaround condition
*
@@ -552,7 +552,7 @@ PcieTrainingGfxWorkaround (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrain link
*
@@ -580,7 +580,7 @@ PcieTrainingRetrainLink (
PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training fail on this port
*
@@ -600,7 +600,7 @@ PcieTrainingFail (
PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links training success
*
@@ -621,7 +621,7 @@ PcieTrainingSuccess (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links in compliance
*
@@ -641,7 +641,7 @@ PcieTrainingCompliance (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCie EP not present
*
@@ -672,7 +672,7 @@ PcieTrainingNotPresent (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Final state. Port training completed.
*
@@ -691,7 +691,7 @@ PcieTrainingCompleted (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -780,7 +780,7 @@ PcieTrainingPortCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main link training procedure
*
@@ -814,7 +814,7 @@ PcieTraining (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump port state on state transition
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index 94e79db..817e7d4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -112,7 +112,7 @@ PcieIsDeskewCardDetected (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* ATI RV370/RV380 card workaround
*
@@ -163,7 +163,7 @@ PcieGfxCardWorkaround (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RV370/RV380 Deskew workaround
*
@@ -206,7 +206,7 @@ PcieDeskewWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NV43 card workaround (lost SSID)
*
@@ -241,7 +241,7 @@ PcieNvWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate temporary resources for Pcie P2P bridge
*
@@ -274,7 +274,7 @@ PcieConfigureBridgeResources (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Free temporary resources for Pcie P2P bridge
*
@@ -300,7 +300,7 @@ PcieFreeBridgeResources (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Save CPU MMIO register
*
@@ -326,7 +326,7 @@ PcieProgramCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Restore CPU MMIO register
*
@@ -347,7 +347,7 @@ PcieRestoreCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if card required test for deskew workaround
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
index 4f91ab1..1c1c24c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
@@ -72,7 +72,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHD entry
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
index fa0d770..a64572f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
@@ -71,7 +71,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB IOAPIC Base Address
*
@@ -89,7 +89,7 @@ SbGetSbIoApicBaseAddress (
return ApicBaseAddress & 0xfffffff8;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB MMIO Base Address
*
@@ -108,14 +108,14 @@ SbGetSbMmioBaseAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Alink config address
*
* @param[in] StdHeader Standard configuration header
* @retval Alink base address
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT16
SbGetAlinkIoAddress (
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index 51c0f47..a22df03 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable/Disable ASPM on GNB-SB link
*
@@ -103,7 +103,7 @@ SbPcieLinkAspmControl (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SB ASPM.
* Enable ASPM states on SB
@@ -112,7 +112,7 @@ SbPcieLinkAspmControl (
* @param[in] Aspm ASPM bitmap.
* @param[in] StdHeader Standard configuration header
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
SbPcieInitAspm (
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
index 0013497..4f6c469 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
@@ -94,7 +94,7 @@ UINT32 LclkDpmActivityThresholdTable [] = {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB LCLK DPM in Root Complex Activity mode
*
@@ -287,7 +287,7 @@ NbFmInitLclkDpmRcActivity (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific check PsppPolicy to initially enable appropriate DPM states
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c
index 3201866..883e518 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c
@@ -111,7 +111,7 @@ UINT32 F12GmcPowerGatingTable_1[] = {
(0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* GMC Power Gating
*
@@ -174,7 +174,7 @@ UINT32 F12UvdPowerGatingTable_1[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* UVD Power Gating
*
@@ -215,7 +215,7 @@ F12NbSmuUvdPowerGatingInit (
-/*----------------------------------------------------------------------------------------*/
+
/**
* UVD Power Shutdown
*
@@ -285,7 +285,7 @@ UINT32 F12SmuGmcShutdownTable_2[] = {
0x00
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shutdown GMC
*
@@ -487,7 +487,7 @@ UINT32 F12SmuGfxShutdownTable_2[] = {
0x00
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shutdown GFX
*
@@ -526,7 +526,7 @@ F12NbSmuGfxShutdown (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power gate unused blocks
*
@@ -575,7 +575,7 @@ F12NbPowerGateFeature (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GMC restore latency
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c
index 6018d04..18ab9d8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c
@@ -84,7 +84,7 @@ FUSE_TABLE FuseTable;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB family specific clock gating
*
@@ -101,7 +101,7 @@ NbFmNbClockGating (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -120,7 +120,7 @@ NbFmClumpUnitID (
GnbClumpUnitID (NbPciAddress, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Fuse translation table
*
@@ -135,7 +135,7 @@ NbFmGetFuseTranslationTable (
return &FuseTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific fuse table patch
* Is's correct behavior if we would have 4 states, it would be
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c
index ec22688..69ce0af 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c
@@ -70,7 +70,7 @@ F12NbSmuInitFeature (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Initialize
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
index da523c5..22ed4d6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
@@ -126,7 +126,7 @@ PP_FUSE_ARRAY DefaultPpFuseArray = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fuse Table Init
*
@@ -192,7 +192,7 @@ NbFuseTableFeature (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Fuse Table From FCRs
*
@@ -238,7 +238,7 @@ NbFuseLoadFuseTableFromFcr (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Default Fuse Table
*
@@ -278,7 +278,7 @@ NbFuseLoadDefaultFuseTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Adjust DIDs to current main PLL VCO
*
@@ -335,7 +335,7 @@ NbFuseAdjustFuseTableToCurrentMainPllVco (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump fuse table
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c
index e1be08c..1688015 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c
@@ -80,7 +80,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* LCLK DPM init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c
index 2c6c68c..23668d4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create configuration data
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
index 57e9f24..9d1e270 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
@@ -137,7 +137,7 @@ CONST NB_REGISTER_ENTRY NbOrbInitTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at Power On
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
index ee0c601..8cd74ab 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
@@ -74,7 +74,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c
index 50dcfb1..5d3b337 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at ENV
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c
index 5737c90..5b23a15 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late Post
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
index a139e52..17f7fc0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
@@ -73,7 +73,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at POST
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c
index db44f40..6c7dde4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c
@@ -71,7 +71,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c
index 6a85f71..31dece9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c
@@ -131,7 +131,7 @@ NbInitDceDisplayClockGating (
IN GNB_PLATFORM_CONFIG *Gnb
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init various power management features
*
@@ -155,7 +155,7 @@ NbInitPowerManagement (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB LCLK Deep Sleep
*
@@ -571,7 +571,7 @@ NbInitDceDisplayClockGating (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB clock gating
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c
index 841b25c..36b2325 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c
@@ -100,7 +100,7 @@ NbSmuReadEfuseField (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register read
*
@@ -172,7 +172,7 @@ NbSmuIndirectRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register read
*
@@ -208,7 +208,7 @@ NbSmuIndirectPoll (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register write
*
@@ -272,7 +272,7 @@ NbSmuIndirectWriteEx (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register write
*
@@ -305,7 +305,7 @@ NbSmuIndirectWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request for S3 script
*
@@ -327,7 +327,7 @@ NbSmuIndirectWriteS3Script (
NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU RAM mapped register write
*
@@ -370,7 +370,7 @@ NbSmuRcuRegisterWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU RAM mapped register read
*
@@ -397,7 +397,7 @@ NbSmuRcuRegisterRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request Ext
*
@@ -429,7 +429,7 @@ NbSmuServiceRequestEx (
NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request
*
@@ -458,7 +458,7 @@ NbSmuServiceRequest (
IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request for S3 script
*
@@ -478,7 +478,7 @@ NbSmuServiceRequestS3Script (
NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Read FCR register
*
@@ -500,7 +500,7 @@ NbSmuReadEfuse (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Read arbitrary fuse field
*
@@ -537,7 +537,7 @@ NbSmuReadEfuseField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU SRBM (GMM) register read
*
@@ -569,7 +569,7 @@ NbSmuSrbmRegisterRead (
NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU SRBM (GMM) register write
*
@@ -605,7 +605,7 @@ NbSmuSrbmRegisterWrite (
NbSmuServiceRequest (0x0B, S3Save, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware download
*
@@ -640,7 +640,7 @@ NbSmuFirmwareDownload (
NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware revision
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
index 5932c74..a5b7d80 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
@@ -79,7 +79,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
index ca8aec2..61346d9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
@@ -73,7 +73,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -97,7 +97,7 @@ PcieFmGetComplexDataLength (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -119,7 +119,7 @@ PcieFmBuildComplexConfiguration (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* get native PHY lane bitmap
*
@@ -136,7 +136,7 @@ PcieFmGetNativePhyLaneBitmap (
{
return PhyLaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SB port info
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
index b508daa..e4ebca9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
@@ -75,7 +75,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visability
*
@@ -105,7 +105,7 @@ PcieFmPortVisabilityControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request boot up voltage
*
@@ -159,7 +159,7 @@ PcieFmSetBootUpVoltage (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -207,7 +207,7 @@ PcieFmMapPortPciAddress (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slo power limit
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c
index b8493cb..57b6f3e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c
@@ -91,7 +91,7 @@ PcieFmPostOscPifInitCallback (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL personality
*
@@ -130,7 +130,7 @@ PcieFmSetPhyPersonality (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY Pll Personality Init
*
@@ -174,7 +174,7 @@ PcieFmPhyLetPllPersonalityInitCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PHY channel characteristic
*
@@ -192,7 +192,7 @@ PcieFmPhyChannelCharacteristic (
//@todo
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Point "virtual" PLL clock picker away from PCIe
*
@@ -210,7 +210,7 @@ PcieFmAvertClockPickers (
PciePhyAvertClockPickers (Wrapper, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane ganging
*
@@ -228,7 +228,7 @@ PcieFmPhyApplyGanging (
PciePhyApplyGanging (Wrapper, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* DCC recalibration
*
@@ -253,7 +253,7 @@ PcieFmForceDccRecalibrationCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for Osc switch
*
@@ -284,7 +284,7 @@ PcieFmPreOscPifInitCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Osc init
*
@@ -318,7 +318,7 @@ PcieFmPostOscPifInitCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare PHY for Gen2
*
@@ -476,7 +476,7 @@ PcieFmOscInitPhyForGen2 (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
@@ -495,7 +495,7 @@ PcieFmPifSetRxDetectPowerMode (
PciePifSetRxDetectPowerMode (Wrapper, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane parameter Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c
index 6629eb3..04f5524 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -98,7 +98,7 @@ PcieFmPifSetPllModeForL1 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL power up latency
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c
index 83f95c6..febe185 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c
@@ -163,7 +163,7 @@ PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -213,7 +213,7 @@ CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = {
{0, 7, 8, 15}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -256,7 +256,7 @@ CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = {
{0, 3, 4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID},
{0, 3, 4, 7, 8, 11, 12, 15}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -293,7 +293,7 @@ PcieLnConfigureGfxDdiEnginesLaneAllocation (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -352,7 +352,7 @@ CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = {
{1, 2, 3, 4, 0}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -397,7 +397,7 @@ CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
{0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure DDI engine list to support lane allocation according to configuration ID.
*
@@ -433,7 +433,7 @@ PcieLnConfigureDdiEnginesLaneAllocation (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get configuration Value for GFX wrapper
*
@@ -464,7 +464,7 @@ PcieLnGetGfxConfigurationValue (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get configuration Value for GPP wrapper
*
@@ -507,7 +507,7 @@ PcieLnGetGppConfigurationValue (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -540,7 +540,7 @@ PcieFmGetCoreConfigurationValue (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -586,7 +586,7 @@ PcieFmGetLinkSpeedCap (
return LinkSpeedCapability;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Various initialization needed prior topology and configuration initialization
*
@@ -650,7 +650,7 @@ PcieFmPreInit (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -672,7 +672,7 @@ PcieFmCheckPortPciDeviceMapping (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -708,7 +708,7 @@ PcieFmDebugGetCoreConfigurationString (
return (CONST CHAR8*) " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -736,7 +736,7 @@ PcieFmDebugGetWrapperNameString (
return (CONST CHAR8*) " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -786,7 +786,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c
index 5ce7064..7898183 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c
@@ -89,7 +89,7 @@ UINT32 PciePowerGatingTable_1[] = {
(0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Power Gating
*
@@ -127,7 +127,7 @@ PcieSmuPowerGatingInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -186,7 +186,7 @@ PcieSmuPowerGateLanes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll access required
*
@@ -211,7 +211,7 @@ PciePowerGatePllControl (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Report used lanes to SMU.
*
@@ -238,7 +238,7 @@ PciePowerGateReportUsedLanesCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -282,7 +282,7 @@ PciePowerGatePhyLaneCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -324,7 +324,7 @@ PciePowerGatePhyLane (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power PCIe block
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
index 716b742..fc7e8a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
@@ -102,7 +102,7 @@ PciePostInitCallback (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visibility in PCI config space
*
@@ -175,7 +175,7 @@ PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Common Core Init
*
@@ -217,7 +217,7 @@ PcieCommonCoreInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
*
@@ -236,7 +236,7 @@ PcieInitSrbmCallback (
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -279,7 +279,7 @@ PcieInitCallback (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -309,7 +309,7 @@ PcieInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -330,7 +330,7 @@ PciePostInitCallback (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
index 0198ed4..fe90537 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c
index 207cd26..c78521b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Env Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c
index 55697b7..d800b27 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c
@@ -71,7 +71,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c
index 7628652..3710f13 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init prior DRAM init
*
@@ -110,7 +110,7 @@ PcieInitAtPostEarly (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -153,7 +153,7 @@ PcieInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -199,7 +199,7 @@ PcieInitAtPostS3 (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe S3 restore
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c
index f1a8747..5aef9ad 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c
@@ -86,7 +86,7 @@ PcieLateInitCallback (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down inactive lanes
*
@@ -114,7 +114,7 @@ PciePwrPowerDownPllInL1 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Late Init.
*
@@ -137,7 +137,7 @@ PcieLateInitCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Late Init
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c
index 5ded703..3b29ea4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c
@@ -117,7 +117,7 @@ PCIE_PORT_REGISTER_ENTRY PortInitTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -159,7 +159,7 @@ PciePortInitCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -191,7 +191,7 @@ PciePortInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -232,7 +232,7 @@ PciePortPostInitCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -260,7 +260,7 @@ PciePortPostInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports on S3 resume path
*
@@ -304,7 +304,7 @@ PciePortPostS3InitCallback (
PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init port on S3 resume during destributed training
*
@@ -332,7 +332,7 @@ PciePortPostS3Init (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c
index 950deac..3b67638 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c
@@ -93,7 +93,7 @@ PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slot power limit
*
@@ -131,7 +131,7 @@ PcieSlotPowerLimit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -159,7 +159,7 @@ PciePortLateInitCallback (
PcieEnableAspm (Engine, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c
index 9c08032..8628743 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -71,7 +71,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return whether the current configuration exceeds the capability.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c
index 2cac1d4..6f3e77d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable config access to a non-coherent chain for the given bus range.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c
index e4a8582..0fba2a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -68,7 +68,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
@@ -141,7 +141,7 @@ Fam10NorthBridgeFreqMask (
return (Supported);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
index bd20f36..b009155 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
@@ -106,7 +106,7 @@ typedef union {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the traffic distribution register for the Links provided.
*
@@ -153,7 +153,7 @@ Fam10WriteTrafficDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write a link pair to the link pair distribution and fixups.
*
@@ -237,7 +237,7 @@ Fam10WriteLinkPairDistribution (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
@@ -318,7 +318,7 @@ Fam10BufferOptimizations (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c
index 576a6b1..3b51120 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -122,7 +122,7 @@ Fam10GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -175,7 +175,7 @@ Fam10RevDGetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the next link for iterating over the links on a node in the correct order.
*
@@ -266,7 +266,7 @@ Fam10GetNextLink (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Info about Module Type of this northbridge
*
@@ -306,7 +306,7 @@ Fam10GetModuleInfo (
*Module = (UINT8) IntNodeNum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -333,7 +333,7 @@ Fam10GetSocket (
return (Node);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -369,7 +369,7 @@ Fam10RevDGetSocket (
return ((UINT8) Socket);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post info to AP cores via a mailbox.
*
@@ -408,7 +408,7 @@ Fam10PostMailbox (
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrieve info from a node's mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c
index b093292..3e641fa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -105,7 +105,7 @@ Fam12GetNumCoresOnNode (
return (UINT8) (Cores + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c
index d7b77aa..8905beb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -140,7 +140,7 @@ typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
*** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
***************************************************************************/
-/*-----------------------------------------------------------------------------------*/
+
/**
* Ensure a request / response route from target Node to bsp.
*
@@ -186,7 +186,7 @@ routeFromBSP (
State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test Compatibility of a new node, and handle failure.
*
@@ -260,7 +260,7 @@ CheckCompatible (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check the system MP capability with a new node and handle any failure.
*
@@ -314,7 +314,7 @@ CheckCapable (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make all the tests needed to determine if a link should be added to the system data structure.
*
@@ -379,7 +379,7 @@ IsLinkToAdd (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Explore for a new node over a link, handling whatever is found.
*
@@ -479,7 +479,7 @@ ExploreNode (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process all the saved new node info for the current processor.
*
@@ -536,7 +536,7 @@ ProcessSavedNodeInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create and add a new link to the system data structure.
*
@@ -584,7 +584,7 @@ AddLinkToSystem (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Start discovery from a new node.
*
@@ -629,7 +629,7 @@ StartFromANewNode (
State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Back up from exploring a one-deep internal node.
*
@@ -656,7 +656,7 @@ BackUpFromANode (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dynamically Discover all coherent devices in the system.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c
index 7109374..90a2daf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c
@@ -98,7 +98,7 @@ RDATA_GROUP (G1_PEICC)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c
index 90d2240..26682c8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c
@@ -102,7 +102,7 @@ RDATA_GROUP (G1_PEICC)
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process a non-coherent Link.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c
index f6ab31b..03f5abf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c
@@ -107,7 +107,7 @@ extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Given the bits set in the register field, return the width it represents.
*
@@ -162,7 +162,7 @@ ConvertBitsToWidth (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Translate a desired width setting to the bits to set in the register field.
*
@@ -216,7 +216,7 @@ ConvertWidthToBits (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Access HT Link Control Register.
*
@@ -264,7 +264,7 @@ SetHtControlRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set HT Frequency register for IO Devices
*
@@ -311,7 +311,7 @@ SetHtIoFrequencyRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -408,7 +408,7 @@ GatherLinkData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Links.
*
@@ -548,7 +548,7 @@ SelectOptimalWidthAndFrequency (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
@@ -731,7 +731,7 @@ SetLinkData (
}
}
-/*------------------------------------------------------------------------------------------*/
+
/**
* Find a specific HT capability type.
*
@@ -797,7 +797,7 @@ DoesDeviceHaveHtSubtypeCap (
return IsFound;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c
index 6322d38..9a1dc8c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c
@@ -106,7 +106,7 @@ typedef struct {
*** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link on source Node which connects to target Node
*
@@ -145,7 +145,7 @@ FindLinkToNode (
return TargetLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is graphA isomorphic to graphB?
*
@@ -214,7 +214,7 @@ IsIsomorphic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Topology List iterator context to the Beginning and provide the first topology.
*
@@ -246,7 +246,7 @@ BeginTopologies (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through available topologies.
*
@@ -283,7 +283,7 @@ GetNextTopology (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
@@ -438,7 +438,7 @@ LookupComputeAndLoadRoutingTables (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a Hop Count Table for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c
index f2f7423..fbcf36e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c
@@ -123,7 +123,7 @@ STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
index bba026f..ad97f88 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -118,7 +118,7 @@ UINT32 VictimedLinkFromNodeBToNodeA; ///< Victimed Link from Node B
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Identify Links which can have traffic distribution.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
index ab91fe3..19cf80b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
@@ -57,7 +57,7 @@ RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-/*-------------------------------------------------------------------------------------*/
+
/**
* Apply an IDS port override to the desired HT link.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c
index 304888f..f2eed0a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Establish a Temporary route from one Node to another.
*
@@ -127,7 +127,7 @@ WriteRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Modifies the NodeID register on the target Node
*
@@ -156,7 +156,7 @@ WriteNodeID (
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the Default Link
*
@@ -195,7 +195,7 @@ ReadDefaultLink (
return (UINT8)DefaultLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables on for a given Node
*
@@ -222,7 +222,7 @@ EnableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables off for a given Node
*
@@ -249,7 +249,7 @@ DisableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is coherent, connected, and ready
*
@@ -289,7 +289,7 @@ VerifyLinkIsCoherent (
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the token stored in the scratchpad register field.
*
@@ -328,7 +328,7 @@ ReadToken (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the token stored in the scratchpad register
*
@@ -364,7 +364,7 @@ WriteToken (
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Full Routing Table Register initialization
*
@@ -419,7 +419,7 @@ WriteFullRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
@@ -443,7 +443,7 @@ IsIllegalTypeMix (
return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fix (hopefully) exceptional conditions.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c
index 5c0dc58..14fbd47 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC)
*** Northbridge access routines ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link to the Southbridge
*
@@ -100,7 +100,7 @@ ReadSouthbridgeLink (
return (UINT8)Temp;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is non-coherent, connected, and ready
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c
index 9915b36..1e6c151 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -122,7 +122,7 @@ GatherLinkFeatures (
ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
@@ -153,7 +153,7 @@ SetLinkRegang (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for Unit Id Clumping.
@@ -189,7 +189,7 @@ SetLinkUnitIdClumping (
LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link frequency.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c
index 6320085..d4f61a8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the HT Host capability base PCI config address for a Link.
*
@@ -111,7 +111,7 @@ MakeLinkBase (
return LinkBase;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
@@ -183,7 +183,7 @@ ReadTrueLinkFailStatus (
return (BOOLEAN) ((After != 0) || (Unconnected != 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores and Nodes to the Node
*
@@ -223,7 +223,7 @@ SetTotalNodesAndCores (
LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -254,7 +254,7 @@ GetNodeCount (
return ((UINT8) (++Temp));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
@@ -282,7 +282,7 @@ LimitNodes (
LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, given the node and real link number.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c
index 5f5d6c6..3cdac3d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c
@@ -87,7 +87,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
index 5b5517b..572baea 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
@@ -55,7 +55,7 @@ RDATA_GROUP (G1_PEICC)
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the AGESA built in topology list
*
@@ -73,7 +73,7 @@ GetAmdTopolist (
*List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the number of Nodes in the compressed graph
*
@@ -89,7 +89,7 @@ GraphHowManyNodes (
return Graph[0];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns true if NodeA is directly connected to NodeB, false otherwise
*
@@ -116,7 +116,7 @@ GraphIsAdjacent (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route responses targeted at NodeB.
*
@@ -144,7 +144,7 @@ GraphGetRsp (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route requests targeted at NodeB.
*
@@ -172,7 +172,7 @@ GraphGetReq (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns a bit vector of Nodes that NodeA should forward a broadcast from
* NodeB towards
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c
index b0617b1..7faa1ce 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c
@@ -187,7 +187,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -212,7 +212,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c
index d6d7f20..886cc57 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c
@@ -96,8 +96,8 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -167,7 +167,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -233,7 +233,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c
index 9bbb32c..db73989 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c
@@ -102,7 +102,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -122,7 +122,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -202,7 +202,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -230,7 +230,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -281,7 +281,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -344,7 +344,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -444,7 +444,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -482,7 +482,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
index cd19d3d..d4c5c9e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -152,7 +152,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -269,7 +269,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -328,7 +328,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c
index af8d63e..2b8aedc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c
@@ -88,7 +88,7 @@ IsBootCore (
IN STATE_DATA *State
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -194,7 +194,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -229,7 +229,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -299,7 +299,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -347,7 +347,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -386,7 +386,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -417,7 +417,7 @@ Tuning (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -450,7 +450,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -478,7 +478,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
index 428e897..864a398 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
@@ -152,7 +152,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -190,7 +190,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c
index 696f3f6..aaa77ce 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -126,7 +126,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -159,7 +159,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -195,7 +195,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -230,7 +230,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -262,7 +262,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -303,7 +303,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -341,7 +341,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -376,7 +376,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -411,7 +411,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -446,7 +446,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -485,7 +485,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -524,7 +524,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -554,7 +554,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -590,7 +590,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -629,7 +629,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
index c7c1ba4..ed01b5c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
@@ -47,7 +47,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -167,7 +167,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c
index 8fa8029..236cb1e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c
@@ -108,7 +108,7 @@ STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c
index cc3b739..b68245e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -104,7 +104,7 @@ STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c
index 1be73e4..3b55479 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR2 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c
index 06e2c30..5a6bb83 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c
index dc5a24d..d11a1c8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c
index b66244f..40f4183 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c
@@ -109,7 +109,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR2 L1 system
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c
index ca887d2..7c909fd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c
@@ -108,7 +108,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c
index 0d67898..32f979d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c
index aaf40a3..3edc4c4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c
@@ -108,7 +108,7 @@ STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c
index c3da813..32ce2c2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c
@@ -104,7 +104,7 @@ STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c
index 590d8fc..0548fe9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c
@@ -90,7 +90,7 @@ STATIC CONST UINT8 ROMDATA LnSDdr3CKETri[] = {0x55, 0xAA};
STATIC CONST UINT8 ROMDATA LnSDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
STATIC CONST UINT8 ROMDATA LnSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for LN DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c
index 953bad2..ea05c2e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c
@@ -86,7 +86,7 @@ STATIC CONST UINT8 ROMDATA LnUDdr3CKETri[] = {0x55, 0xAA};
STATIC CONST UINT8 ROMDATA LnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
STATIC CONST UINT8 ROMDATA LnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for LN DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c
index 0b29304..c978267 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c
index c84f485..5b26cf9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c
index 6b5384e..6575b7e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c
index 29f4e9c..1075b19 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c
index fc80bef..4d7683b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c
index 63db725..91821af 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c
@@ -95,7 +95,7 @@ STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c
index 18154d4..5daca9f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -105,7 +105,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c
index 8d70c4b..2338491 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveChannels:
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 4bc794c..7fed18a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -104,7 +104,7 @@ MemFUndoInterleaveBanks (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -199,7 +199,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -305,7 +305,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
index a663337..d86506c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
@@ -98,7 +98,7 @@ MemFDMISupport2 (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -373,7 +373,7 @@ MemFDMISupport3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c
index 757a19c..ec88fc5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c
@@ -100,7 +100,7 @@ MemFCheckECC (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -166,7 +166,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -291,7 +291,7 @@ InitECCOverriedeStruct (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c
index 75763c0..8e9ab07 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c
@@ -91,7 +91,7 @@ MemFInitEMP (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -155,7 +155,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index d146743..883586b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -90,7 +90,7 @@ MemFRASExcludeDIMM (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 02f5630..2fc0092 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -113,7 +113,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -206,7 +206,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -475,7 +475,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -508,7 +508,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index f04d119..2ae30d5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveRegion:
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index f4f90da..6cf812e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 8ace00f..255c27a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -112,7 +112,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c
index 93189b6..e79f279 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform a check to see if node interleaving can be enabled on each node.
@@ -126,7 +126,7 @@ MemFCheckInterleaveNodes (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Applies Node memory interleaving for each node.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index 4150301..a74fa36 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c
index 9482537..2677832 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Enable online spare on current node if it is requested.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index 69e207b..cbe568f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index be45c95..cad6add 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -62,7 +62,7 @@ RDATA_GROUP (G1_PEICC)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
index 728bd01..f14323f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
@@ -94,7 +94,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -198,7 +198,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -295,7 +295,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -357,7 +357,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -407,7 +407,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -457,7 +457,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -507,7 +507,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -564,7 +564,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -688,7 +688,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c
index ebde818..0d77558 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c
index fb34195..f159a1d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c
index 6563da2..4e70270 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c
index 38925cb..7e21c3b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c
index 39ab982..5ecdd4c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c
@@ -97,7 +97,7 @@ MemMFlowLN (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c
index 6f4d6af..b718ee6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c
index cf0a3af..3af2c05 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c
@@ -93,7 +93,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c
index c64b915..8dd449b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c
@@ -86,7 +86,7 @@ MemMFlowDef (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -97,7 +97,7 @@ memDefRet (VOID)
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -109,7 +109,7 @@ memDefTrue (VOID)
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns FALSE.
@@ -120,7 +120,7 @@ memDefFalse (VOID)
{
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function for flow control
@@ -134,7 +134,7 @@ MemMFlowDef (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns AGESA_SUCCESS.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
index 1bf4e5d..e62bd4e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
@@ -89,7 +89,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c
index 22c4b76..b3b52a3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c
@@ -89,7 +89,7 @@ extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c
index c7b0bdb..77c97b1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -126,7 +126,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c
index 59069b4..1d0499c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c
@@ -155,7 +155,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -428,7 +428,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -477,7 +477,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -516,7 +516,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -555,7 +555,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -599,7 +599,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -657,7 +657,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c
index cdf02e3..16bd900 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c
@@ -76,7 +76,7 @@ MemMEcc (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c
index e2415cc..efdd94a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c
@@ -75,7 +75,7 @@ MemMRASExcludeDIMM (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
index 156ab1e..91e7aa6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
@@ -71,7 +71,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
@@ -131,7 +131,7 @@ MemMLvDdr3 (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes, taken into account of the
@@ -202,7 +202,7 @@ MemMLvDdr3PerformanceEnhPre (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Finalize the VDDIO for the board for performance enhancement.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c
index e62b449..33321db 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c
@@ -72,7 +72,7 @@ MemMMctMemClr (
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c
index 5aff259..e8383ab 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c
@@ -112,7 +112,7 @@ MemMContextRestore (
extern MEM_NB_SUPPORT memNBInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -227,7 +227,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -281,7 +281,7 @@ MemMContextRestore (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices that contains DQS timings
*
@@ -444,7 +444,7 @@ MemMRestoreDqsTimings (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function filters out other settings and only restores DQS timings.
@@ -553,7 +553,7 @@ MemMSetCSRNb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c
index 9bfec38..48181d4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c
@@ -73,7 +73,7 @@ MemMInterleaveNodes (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c
index a610f07..e71ffa3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c
@@ -71,7 +71,7 @@ MemMOnlineSpare (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c
index e66d825..9f0abc9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c
@@ -85,7 +85,7 @@ MemMParallelTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c
index 5f48b0e..784ea03 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c
@@ -75,7 +75,7 @@ MemMStandardTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
index 8bdc7fe..925544a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
@@ -92,7 +92,7 @@ MemMUmaAlloc (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c
index 8dc1191..b7b2fd4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c
@@ -104,7 +104,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -301,7 +301,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c
index c76d228..a6c05ed 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c
@@ -163,7 +163,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -255,7 +255,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -285,7 +285,7 @@ MemUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -311,7 +311,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -332,7 +332,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -360,7 +360,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -390,7 +390,7 @@ MemUWait10ns (
} while (CurrentTsc < TargetTsc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -430,7 +430,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -468,7 +468,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -509,7 +509,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -547,7 +547,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -586,7 +586,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -624,7 +624,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
@@ -651,7 +651,7 @@ GetVarMtrrHiMsk (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns number of memclk converted from ns
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c
index aae30e0..69a07dc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -81,7 +81,7 @@ MemConstructRemoteNBBlockC32 (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c
index ff22180..928c6c3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c
@@ -459,7 +459,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -540,7 +540,7 @@ MemS3ResumeConstructNBBlockC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -591,7 +591,7 @@ MemNS3GetRegLstPtrC32 (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -620,7 +620,7 @@ MemNS3GetDeviceRegLstC32 (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -674,7 +674,7 @@ MemNS3SetSpecialPCIRegC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
index f46d501..80b8dd5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
@@ -98,7 +98,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -351,7 +351,7 @@ MemNInitNBDataC32 (
NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -420,7 +420,7 @@ MemNInitDefaultsC32 (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -443,7 +443,7 @@ MemNWritePatternC32 (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -465,7 +465,7 @@ MemNReadPatternC32 (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c
index 7a1feb4..4e1ad58 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c
@@ -96,7 +96,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -238,7 +238,7 @@ MemNAutoConfigC32 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -267,7 +267,7 @@ MemNSendMrsCmdC32 (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -294,7 +294,7 @@ MemNBeforeDramInitC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -328,7 +328,7 @@ MemNEnDLLShutDownC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -359,7 +359,7 @@ MemNBeforePlatformSpecC32 (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initializes extended MMIO address space
@@ -405,7 +405,7 @@ MemNInitExtMMIOAddrC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Force LvDimm voltage to 1.5V for D0 part
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
index d9609ca..7d20e8d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c
index 5994948..fd47729 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c
index 7235b1c..8534fdb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -148,7 +148,7 @@ MemNFinalizeMctC32 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c
index cf8ba2a..5f48354 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c
@@ -99,7 +99,7 @@ MemNGetODTDelaysC32 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -138,7 +138,7 @@ MemNOtherTimingC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -162,7 +162,7 @@ MemNSetOtherTimingC32 (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -206,7 +206,7 @@ MemNGetODTDelaysC32 (
ODTDelays += Ld;
return ODTDelays;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c
index 3756a24..fe006c6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c
@@ -92,10 +92,10 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -164,7 +164,7 @@ MemNInitPhyCompC32 (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c
index a7c833b..275fdf0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -116,7 +116,7 @@ MemNIsIdSupportedC32 (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -140,7 +140,7 @@ MemNGetSocketRelativeChannelC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -278,7 +278,7 @@ MemNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c
index 4abd8dd..bcd1fbb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -84,7 +84,7 @@ MemConstructRemoteNBBlockDA (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c
index a186efd..8397ea0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c
@@ -477,7 +477,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -558,7 +558,7 @@ MemS3ResumeConstructNBBlockDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -609,7 +609,7 @@ MemNS3GetRegLstPtrDA (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -637,7 +637,7 @@ MemNS3GetDeviceRegLstDA (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -691,7 +691,7 @@ MemNS3SetSpecialPCIRegDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
index ed2ae37..c5a6dc2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
@@ -101,7 +101,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -355,7 +355,7 @@ MemNInitNBDataDA (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -422,7 +422,7 @@ MemNInitDefaultsDA (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -445,7 +445,7 @@ MemNWritePatternDA (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -467,7 +467,7 @@ MemNReadPatternDA (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c
index 38d8d0f..7dc48a2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c
@@ -101,7 +101,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -135,7 +135,7 @@ MemNBeforeDramInitDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -240,7 +240,7 @@ memNAutoConfigDA (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -269,7 +269,7 @@ MemNSendMrsCmdDA (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -300,7 +300,7 @@ MemNBeforePlatformSpecDA (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -340,7 +340,7 @@ MemNChangeAvgValue8DA (
return FALSE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -372,7 +372,7 @@ MemNEnDLLShutDownDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -456,7 +456,7 @@ MemNCapSpeedBatteryLifeDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
index 9a95b97..d8a3f69 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c
index bac5693..2d0b750 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c
index d54018d..763a8c6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -152,7 +152,7 @@ MemNFinalizeMctDA (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
index 1038dbf..d3a0fe7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
@@ -101,7 +101,7 @@ MemNPowerDownCtlDA (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemNOtherTimingDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -163,7 +163,7 @@ MemNSetOtherTimingDA (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
index 8ad203f..d60073e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
@@ -55,7 +55,7 @@ RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c
index 51cbac7..9393267 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -125,7 +125,7 @@ MemNIsIdSupportedDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -252,7 +252,7 @@ MemNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c
index f348f51..9c8dbdc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -84,7 +84,7 @@ MemConstructRemoteNBBlockDR (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c
index 897f825..32a185e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c
@@ -444,7 +444,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -525,7 +525,7 @@ MemS3ResumeConstructNBBlockDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -576,7 +576,7 @@ MemNS3GetRegLstPtrDr (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -605,7 +605,7 @@ MemNS3GetDeviceRegLstDr (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -659,7 +659,7 @@ MemNS3SetSpecialPCIRegDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
index b443b76..0d10538 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
@@ -105,7 +105,7 @@ extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -220,7 +220,7 @@ memNAutoConfigDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -237,7 +237,7 @@ MemNBeforeDramInitDr (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -283,7 +283,7 @@ MemNSendMrsCmdDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -314,7 +314,7 @@ MemNBeforePlatformSpecDr (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -347,7 +347,7 @@ MemTCtlOnDimmMirrorDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -369,7 +369,7 @@ MemNPFenceAdjustDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c
index 84d45b0..f45e093 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -228,7 +228,7 @@ MemConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -347,7 +347,7 @@ MemNInitNBDataDr (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -416,7 +416,7 @@ MemNInitDefaultsDR (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -439,7 +439,7 @@ MemNWritePatternDr (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -461,7 +461,7 @@ MemNReadPatternDr (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
index 0e100c8..97a9c06 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c
index 9847e97..5377436 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c
index 9d7ac9e..3132795 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -139,7 +139,7 @@ MemNFinalizeMctDr (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
index 37a2e36..0e0b845 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
@@ -101,7 +101,7 @@ MemNPowerDownCtlDR (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -139,7 +139,7 @@ MemNOtherTimingDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -162,7 +162,7 @@ MemNSetOtherTimingDR (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
index 2dfb5dc..e5eab50 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
@@ -75,7 +75,7 @@ MemNTrainFenceWHardCodeValDr (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -103,7 +103,7 @@ MemPPhyFenceTrainingDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -138,7 +138,7 @@ MemNTrainFenceWHardCodeValDr (
NBPtr->SwitchDCT (NBPtr, CurDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c
index a651d0c..212b7ea 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -126,7 +126,7 @@ MemNIsIdSupportedDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -253,7 +253,7 @@ MemNCmnGetSetFieldDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c
index 399249c..e865524 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -81,7 +81,7 @@ MemConstructRemoteNBBlockHY (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c
index bd1870e..60048aa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c
@@ -468,7 +468,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -549,7 +549,7 @@ MemS3ResumeConstructNBBlockHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -600,7 +600,7 @@ MemNS3GetRegLstPtrHy (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -629,7 +629,7 @@ MemNS3GetDeviceRegLstHy (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -683,7 +683,7 @@ MemNS3SetSpecialPCIRegHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c
index b0acf3d..b2be063 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -238,7 +238,7 @@ MemNAutoConfigHy (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -267,7 +267,7 @@ MemNSendMrsCmdHy (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -309,7 +309,7 @@ MemNSendMrsCmdPerCsHy (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -336,7 +336,7 @@ MemNBeforeDramInitHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -370,7 +370,7 @@ MemNEnDLLShutDownHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -402,7 +402,7 @@ MemNBeforePlatformSpecHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initializes extended MMIO address space
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
index 5f9357c..e3f957d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
index 72274b3..0dfa516 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
@@ -100,7 +100,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ MemConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -352,7 +352,7 @@ MemNInitNBDataHy (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrHy;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -420,7 +420,7 @@ MemNInitDefaultsHY (
// ECC
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -443,7 +443,7 @@ MemNWritePatternHy (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -465,7 +465,7 @@ MemNReadPatternHy (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c
index 79ff314..f9f82dc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c
index cb41835..314bf1c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -148,7 +148,7 @@ MemNFinalizeMctHy (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c
index 58e2118..69b7fb1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c
@@ -99,7 +99,7 @@ MemNGetODTDelaysHy (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -138,7 +138,7 @@ MemNOtherTimingHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -162,7 +162,7 @@ MemNSetOtherTimingHY (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -206,7 +206,7 @@ MemNGetODTDelaysHy (
ODTDelays += Ld;
return ODTDelays;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c
index 6f032cf..a02a180 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c
@@ -94,10 +94,10 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -180,7 +180,7 @@ MemNInitPhyCompHy (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c
index 04b6912..be4374e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -117,7 +117,7 @@ MemNIsIdSupportedHy (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -141,7 +141,7 @@ MemNGetSocketRelativeChannelHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -279,7 +279,7 @@ MemNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
index 812c604..62fa10f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
@@ -475,7 +475,7 @@ VOID *MemS3RegListLN[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -555,7 +555,7 @@ MemS3ResumeConstructNBBlockLN (
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -620,7 +620,7 @@ MemNS3GetConPCIMaskLN (
DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -671,7 +671,7 @@ MemNS3GetRegLstPtrLN (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -700,7 +700,7 @@ MemNS3GetDeviceRegLstLN (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -727,7 +727,7 @@ MemNS3SetDfltPllLockTimeLN (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -754,7 +754,7 @@ MemNS3SetDramPhyCtrlRegLN (
MemNS3SetBitFieldNb (AccessWidth, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to call a CPU routine to change NB P-state and
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c
index 6db8efd..bb06366 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c
@@ -98,7 +98,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -176,7 +176,7 @@ MemNAutoConfigLN (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -205,7 +205,7 @@ MemNSendMrsCmdLN (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -260,7 +260,7 @@ MemNSetMaxLatencyLN (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, N);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -339,7 +339,7 @@ MemNGetMaxLatParamsClientLN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to call a CPU routine to change NB P-state and
@@ -393,7 +393,7 @@ MemNChangeNbFrequencyWrapLN (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -419,7 +419,7 @@ MemNEnableSwapIntlvRgnLN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips setting LowPowerDrvStrengthEn on two DIMMs per channel config
@@ -444,7 +444,7 @@ MemNDisLowPwrDrvStrLN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
index 9b66b23..7d07ad0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -126,7 +126,7 @@ MemNPlatformSpecificFormFactorInitLN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c
index 759bb4f..900abef 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c
index 26f9c45..6991e16 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c
@@ -101,7 +101,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -360,7 +360,7 @@ MemConstructNBBlockLN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default values in the MEM_DATA_STRUCT
@@ -430,7 +430,7 @@ MemNInitDefaultsLN (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -453,7 +453,7 @@ MemNWritePatternLN (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -476,7 +476,7 @@ MemNReadPatternLN (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Client NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c
index e36bd96..4adc03c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function create the HT memory map
@@ -174,7 +174,7 @@ MemNHtMemMapInitLN (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -209,7 +209,7 @@ MemNGetUmaSizeLN (
return SizeOfUma;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
index ded05e4..de43aeb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
@@ -94,7 +94,7 @@ MemNPowerDownCtlLN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the non-SPD timings
@@ -177,7 +177,7 @@ MemNOtherTimingLN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables power down mode
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
index 766b444..4be087a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -137,7 +137,7 @@ MemNBeforeDQSTrainingLN (
MemTEndTraining (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -170,7 +170,7 @@ MemNAfterDQSTrainingLN (
MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel of Llano.
@@ -188,7 +188,7 @@ MemNCSPerChannelLN (
return MAX_CS_PER_CHANNEL_LN;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for Pass N hardware based RcvEn training of UNB.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c
index b0fc19d..fb5d1d8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c
@@ -94,7 +94,7 @@ MemNOverridePllDivValueLN (
CONST UINT8 PllDivOverrideTab[] = {0, 0, 0, 6, 4, 3, 3, 3};
CONST UINT8 PllMultOverrideTab[] = {0, 0, 0, 48, 42, 40, 48, 56};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes early sample support for Llano
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
index 9c52705..0acfa22 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
@@ -94,7 +94,7 @@ STATIC CONST UINT8 InstancesPerTypeLN[8] = {8, 2, 1, 0, 2, 0, 1, 1};
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -120,7 +120,7 @@ MemNIsIdSupportedLN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -292,7 +292,7 @@ MemNCmnGetSetFieldLN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
index aed7aa5f..f78eaf2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -228,7 +228,7 @@ MemConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -359,7 +359,7 @@ MemNInitNBDataNi (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -426,7 +426,7 @@ MemNInitDefaultsNi (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -449,7 +449,7 @@ MemNWritePatternNi (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -472,7 +472,7 @@ MemNReadPatternNi (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c
index 05bbf16..9bc1382 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c
@@ -476,7 +476,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -557,7 +557,7 @@ MemS3ResumeConstructNBBlockNi (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -608,7 +608,7 @@ MemNS3GetRegLstPtrNi (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -636,7 +636,7 @@ MemNS3GetDeviceRegLstNi (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -690,7 +690,7 @@ MemNS3SetSpecialPCIRegNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
index 0991ad6..a291834 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
index 12c4aa5..4c3fb45 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -228,7 +228,7 @@ MemConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -359,7 +359,7 @@ MemNInitNBDataPh (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -426,7 +426,7 @@ MemNInitDefaultsPh (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -449,7 +449,7 @@ MemNWritePatternPh (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -472,7 +472,7 @@ MemNReadPatternPh (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c
index d8ba71e..e9ff351 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c
@@ -477,7 +477,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -505,7 +505,7 @@ MemNIsIdSupportedPh (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -586,7 +586,7 @@ MemS3ResumeConstructNBBlockPh (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -637,7 +637,7 @@ MemNS3GetRegLstPtrPh (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -665,7 +665,7 @@ MemNS3GetDeviceRegLstPh (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -719,7 +719,7 @@ MemNS3SetSpecialPCIRegPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
index e187680..4424c48 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c
index ae6e92b..a980ff7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
index 2829aa7..4efa36d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -228,7 +228,7 @@ MemConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -359,7 +359,7 @@ MemNInitNBDataRb (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -426,7 +426,7 @@ MemNInitDefaultsRb (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -449,7 +449,7 @@ MemNWritePatternRb (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -472,7 +472,7 @@ MemNReadPatternRb (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c
index a3a08a0..00cdb73 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c
@@ -477,7 +477,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -505,7 +505,7 @@ MemNIsIdSupportedRb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -586,7 +586,7 @@ MemS3ResumeConstructNBBlockRb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -637,7 +637,7 @@ MemNS3GetRegLstPtrRb (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -665,7 +665,7 @@ MemNS3GetDeviceRegLstRb (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -719,7 +719,7 @@ MemNS3SetSpecialPCIRegRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
index 3d08535..e6c544e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c
index 7270f8a..72eb2e6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c
index ab261f7..1599518 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c
@@ -96,7 +96,7 @@ extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -135,7 +135,7 @@ MemNInitNBDataNb (
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -217,7 +217,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -243,7 +243,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -287,7 +287,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -308,7 +308,7 @@ MemNTrainingFlowNb (
return TRUE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -330,7 +330,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -481,7 +481,7 @@ MemNInsDlyCompareTestPatternNb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow for UNB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c
index a2f68f9..8324c08 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c
@@ -104,7 +104,7 @@ MemNS3GetDummyReadAddr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -213,7 +213,7 @@ MemNS3ResumeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -265,7 +265,7 @@ MemNS3ResumeClientNb (
// Errata After S3 resume sequence
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -317,7 +317,7 @@ MemNS3ResumeUNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -412,7 +412,7 @@ MemNS3GetConPCIMaskNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -483,7 +483,7 @@ MemNS3GetConPCIMaskUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -529,7 +529,7 @@ MemNS3GetCSRNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -590,7 +590,7 @@ MemNS3SetCSRNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -613,7 +613,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -636,7 +636,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -660,7 +660,7 @@ MemNS3RestoreScrubNb (
MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -690,7 +690,7 @@ MemNS3DisNbPsDbgNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -721,7 +721,7 @@ MemNS3EnNbPsDbg1Nb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -749,7 +749,7 @@ MemNS3SetDynModeChangeNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -797,7 +797,7 @@ MemNS3DisableChannelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -824,7 +824,7 @@ MemNS3SetDisAutoCompUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -851,7 +851,7 @@ MemNS3SetPreDriverCalUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -877,7 +877,7 @@ MemNS3DctCfgSelectUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -925,7 +925,7 @@ MemNS3GetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -973,7 +973,7 @@ MemNS3SetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1013,7 +1013,7 @@ MemNS3SaveNBRegiserUnb (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1058,7 +1058,7 @@ MemNS3RestoreNBRegiserUnb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1141,7 +1141,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1250,7 +1250,7 @@ MemNS3GetDummyReadAddr (
return AddrFound;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1284,7 +1284,7 @@ MemNS3SetMemClkFreqValUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1324,7 +1324,7 @@ MemNS3ChangeMemPStateContextNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
index 5ccc852..6531d56 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
@@ -120,7 +120,7 @@ MemNQuarterMemClk2NClkNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -223,7 +223,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -358,7 +358,7 @@ MemNPlatformSpecNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -435,7 +435,7 @@ MemNPlatformSpecUnb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -462,7 +462,7 @@ MemNDisableDCTNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -495,7 +495,7 @@ MemNDisableDCTClientNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -530,7 +530,7 @@ MemNDisableDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -568,7 +568,7 @@ MemNStartupDCTNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -643,7 +643,7 @@ MemNStartupDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemNChangeFrequencyHy:
@@ -781,7 +781,7 @@ MemNChangeFrequencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency the next level if it have not reached
@@ -844,7 +844,7 @@ MemNRampUpFrequencyNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency to target frequency
@@ -883,7 +883,7 @@ MemNRampUpFrequencyUnb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -996,7 +996,7 @@ MemNProgramCycTimingsNb (
MemNSetBitFieldNb (NBPtr, BFASR, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1104,7 +1104,7 @@ MemNProgramCycTimingsClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1193,7 +1193,7 @@ MemNProgramCycTimingsUnb (
MemNSetBitFieldNb (NBPtr, BFTmod, (DCTPtr->Timings.Speed == DDR1866_FREQUENCY) ? 0xE : 0xC );
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1221,7 +1221,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1255,7 +1255,7 @@ MemNGetMaxLatParamsNb (
*DlyBiasPtr += 1; // add 1 NCLK
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1315,7 +1315,7 @@ MemNSetMaxLatencyNb (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1350,7 +1350,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1380,7 +1380,7 @@ MemNAfterStitchMemNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1402,7 +1402,7 @@ MemNGet1KTFawTkNb (
return Tab1KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1424,7 +1424,7 @@ MemNGet2KTFawTkNb (
return Tab2KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1454,7 +1454,7 @@ MemNQuarterMemClk2NClkNb (
*SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1500,7 +1500,7 @@ MemNTotalSyncComponentsNb (
return SubTotal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1528,7 +1528,7 @@ MemNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1577,7 +1577,7 @@ MemNSwapBitsUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -1661,7 +1661,7 @@ MemNProgramPlatformSpecNb (
MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1701,7 +1701,7 @@ MemNGetTrdrdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1736,7 +1736,7 @@ MemNGetTwrwrNb (
return DCTPtr->Timings.Twrwr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1781,7 +1781,7 @@ MemNGetTwrrdNb (
return DCTPtr->Timings.Twrrd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1822,7 +1822,7 @@ MemNGetTrwtTONb (
return DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1846,7 +1846,7 @@ MemNGetTrwtWBNb (
return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1866,7 +1866,7 @@ MemNGetMemClkFreqIdNb (
return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1907,7 +1907,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1927,7 +1927,7 @@ MemNGetMemClkFreqIdClientNb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1947,7 +1947,7 @@ MemNGetMemClkFreqIdUnb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1975,7 +1975,7 @@ MemNGetMemClkFreqUnb (
return MemClkFreq;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2121,7 +2121,7 @@ MemNChangeFrequencyClientNb (
MemFInitTableDrive (NBPtr, MTAfterFreqChg);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2269,7 +2269,7 @@ MemNChangeFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -2317,7 +2317,7 @@ MemNProgramNbPstateDependentRegistersUnb (
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
@@ -2467,7 +2467,7 @@ MemNProgramNbPstateDependentRegistersClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2544,7 +2544,7 @@ MemNTotalSyncComponentsClientNb (
return (((P * MemClkPeriod + 1) / 2) + T);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2586,7 +2586,7 @@ MemNPhyPowerSavingClientNb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2657,7 +2657,7 @@ MemNPhyPowerSavingUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2699,7 +2699,7 @@ MemNSetASRSRTNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency as below:
@@ -2804,7 +2804,7 @@ MemNBeforePhyFenceTrainingClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency foras below:
@@ -2874,7 +2874,7 @@ MemNChangeNbFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2902,7 +2902,7 @@ MemNGetDramTermNb (
return DramTerm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2925,7 +2925,7 @@ MemNGetDramTermTblDrvNb (
return RttNom;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2945,7 +2945,7 @@ MemNGetDynDramTermNb (
return (NBPtr->PsPtr->DynamicDramTerm);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2968,7 +2968,7 @@ MemNGetDynDramTermTblDrvNb (
return RttWr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2992,7 +2992,7 @@ MemNGetMR0CLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3014,7 +3014,7 @@ MemNGetMR0WRNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3032,7 +3032,7 @@ MemNGetMR0WRTblDrvNb (
return (UINT32) (NBPtr->PsPtr->MR0WR << 9);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3054,7 +3054,7 @@ MemNGetMR2CWLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns MR2[CWL] value for UNB
@@ -3075,7 +3075,7 @@ MemNGetMR2CWLUnb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets Txp and Txpdll
@@ -3141,7 +3141,7 @@ MemNAdjustTxpdllClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to handle or switch NB Pstate for UNB
@@ -3247,7 +3247,7 @@ MemNChangeNbFrequencyWrapUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3276,7 +3276,7 @@ MemNSendMrsCmdUnb (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3294,7 +3294,7 @@ MemNGetMR0CLTblDrvNb (
return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3352,7 +3352,7 @@ MemNSlot1MaxRdLatTrainClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3393,7 +3393,7 @@ MemNDramPowerMngTimingNb (
MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3] - 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets Rcv Fifo
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
index 99d8a16..8061c3b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
@@ -231,7 +231,7 @@ MemNInitCPGUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -249,7 +249,7 @@ MemNInitCPGNb (
NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions of HW Rx En Training.
@@ -265,7 +265,7 @@ MemNInitDqsTrainRcvrEnHwNb (
{
NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables member functions of Hw Rx En Training.
@@ -288,7 +288,7 @@ MemNDisableDqsTrainRcvrEnHwNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes 9 or 18 cache lines continuously using GH CPG engine
@@ -337,7 +337,7 @@ MemNContWritePatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -429,7 +429,7 @@ MemNContReadPatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -455,7 +455,7 @@ MemNGenHwRcvEnReadsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes cache lines continuously using TCB CPG engine
@@ -532,7 +532,7 @@ MemNContWritePatternClientNb (
MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -588,7 +588,7 @@ MemNContReadPatternClientNb (
MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -613,7 +613,7 @@ MemNGenHwRcvEnReadsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -636,7 +636,7 @@ MemNInitCPGClientNb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -662,7 +662,7 @@ MemNCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -687,7 +687,7 @@ MemNInsDlyCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -802,7 +802,7 @@ MemNPrepareRcvrEnDlySeedNb (
);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of MEMCLKs
@@ -820,7 +820,7 @@ MemNWaitXMemClksNb (
MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Issues dummy TCB write read to zero out CL that is used for MemClr
@@ -848,7 +848,7 @@ MemNBeforeMemClrClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Activate command
@@ -883,7 +883,7 @@ MemNRrwActivateCmd (
NBPtr->WaitXMemClks (NBPtr, 75);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Precharge
@@ -924,7 +924,7 @@ MemNRrwPrechargeCmd (
// Wait 25 MEMCLKs
NBPtr->WaitXMemClks (NBPtr, 25);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -950,7 +950,7 @@ MemNGenHwRcvEnReadsUnb (
NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of reads from DRAM using the
@@ -1065,7 +1065,7 @@ MemNContReadPatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1165,7 +1165,7 @@ MemNContWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results
@@ -1224,7 +1224,7 @@ MemNCompareTestPatternUnb (
return Pass;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for offset comparison results
@@ -1266,7 +1266,7 @@ MemNInsDlyCompareTestPatternUnb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c
index 352f4d1..ec726df 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c
@@ -108,7 +108,7 @@ MemNGetPORFreqLimitTblDrvNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -170,7 +170,7 @@ MemNInitMCTNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -199,7 +199,7 @@ MemNPlatformSpecificFormFactorInitTblDrvNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
@@ -232,7 +232,7 @@ MemNTechBlockSwitchNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -281,7 +281,7 @@ MemNInitDCTNb (
return FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
@@ -302,7 +302,7 @@ MemNCleanupDctRegsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
index 5ace03c3..e9ccd9c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
@@ -103,7 +103,7 @@ MemNSetMTRRrangeNb (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -239,7 +239,7 @@ MemNSyncTargetSpeedNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -269,7 +269,7 @@ MemNSyncDctsReadyNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -405,7 +405,7 @@ MemNHtMemMapInitNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -451,7 +451,7 @@ MemNSyncAddrMapToAllNodesNb (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -482,7 +482,7 @@ MemNPowerDownCtlNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -548,7 +548,7 @@ MemNGetOptimalCGDDNb (
return CGDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -611,7 +611,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -666,7 +666,7 @@ GetTrainDlyFromHeapNb (
return TrainDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -782,7 +782,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -843,7 +843,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -938,7 +938,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -998,7 +998,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1016,7 +1016,7 @@ MemNGetUmaSizeNb (
return 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1050,7 +1050,7 @@ MemNAllocateC6StorageClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1120,7 +1120,7 @@ MemNAllocateC6StorageUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function readjusts TOPMEM and MTRRs after allocating storage for C6
@@ -1171,7 +1171,7 @@ MemNC6AdjustMSRs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Family-specific hook to override the DdrMaxRate value for families with a
@@ -1201,7 +1201,7 @@ MemNGetMaxDdrRateUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1226,7 +1226,7 @@ MemNAfterSaveRestoreUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
index 08b3a66..575478b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
@@ -101,7 +101,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -125,7 +125,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -150,7 +150,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -168,7 +168,7 @@ MemNPhyFenceTrainingNb (
NBPtr->MemPPhyFenceTrainingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -272,7 +272,7 @@ MemNPhyFenceTrainingUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -352,7 +352,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -436,7 +436,7 @@ MemNInitPhyCompNb (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -490,7 +490,7 @@ MemNBeforeDQSTrainingNb (
MemTEndTraining (NBPtr->TechPtr);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -526,7 +526,7 @@ MemNGetTrainDlyParmsNb (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -556,7 +556,7 @@ MemNGetTrainDlyParmsClientNb (
Parms->Mask = 0x03E;
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -588,7 +588,7 @@ MemNGetTrainDlyParmsUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -732,7 +732,7 @@ MemNcmnGetSetTrainDlyNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -854,7 +854,7 @@ MemNcmnGetSetTrainDlyClientNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1007,7 +1007,7 @@ MemNcmnGetSetTrainDlyUnb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -1094,7 +1094,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determined the settings for the Reliable Read/Write engine
@@ -1159,7 +1159,7 @@ MemNSetupHwTrainingEngineUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1187,7 +1187,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1213,7 +1213,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel.
@@ -1231,7 +1231,7 @@ MemNCSPerChannelNb (
return MAX_CS_PER_CHANNEL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -1250,7 +1250,7 @@ MemNCSPerDelayNb (
return MAX_CS_PER_DELAY;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -1276,7 +1276,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -1313,7 +1313,7 @@ MemNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1332,7 +1332,7 @@ MemNPFenceAdjustUnb (
*Value16 += 2; //The Avg PRE value is subtracted by 6 only.
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1615,7 +1615,7 @@ MemNSetSkewMemClkUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function masks the RdDqsDly Bit 0 before writing to register for UNB.
@@ -1635,7 +1635,7 @@ MemNAdjustRdDqsDlyOffsetUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1717,7 +1717,7 @@ MemNCalcWrDqDqsEarlyClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1810,7 +1810,7 @@ MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1944,7 +1944,7 @@ MemNPhyPowerSavingMPstateUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets RxFifo pointer during Read DQS training
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c
index abbc751..c0bc73d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -122,7 +122,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -154,7 +154,7 @@ MemNDctCfgSelectUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -177,7 +177,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -202,7 +202,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -225,7 +225,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -262,7 +262,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -292,7 +292,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -312,7 +312,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
@@ -433,7 +433,7 @@ MemNPollBitFieldNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -473,7 +473,7 @@ MemNChangeMemPStateContextNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates buffer for NB register table
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c
index 8e7c9b8..42ab11d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c
index a161b2c..f1db69f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c
@@ -94,7 +94,7 @@ MemNHwWlPart2Nb (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -127,7 +127,7 @@ MemNDQSTiming3Nb (
}
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
@@ -196,7 +196,7 @@ memNSequenceDDR3Nb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c
index 1f35257..97377e8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c
@@ -166,7 +166,7 @@ STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
@@ -203,7 +203,7 @@ MemPConstructPsRC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 C32 DDR3
@@ -260,7 +260,7 @@ MemPDoPsRC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 C32 DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c
index 1038cec..d4b6824 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
@@ -138,7 +138,7 @@ MemPConstructPsUC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 C32 DDR3
@@ -163,7 +163,7 @@ MemPDoPsUC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 C32
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
index 84153f8..339dff4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
@@ -94,7 +94,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
{DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
{DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR2
@@ -132,7 +132,7 @@ MemPConstructPsSDA2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c
index f684be0..e9f2072 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c
@@ -107,7 +107,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR3
@@ -145,7 +145,7 @@ MemPConstructPsSDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR3
@@ -194,7 +194,7 @@ MemPDoPsSDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c
index 008c1a1..6f50363 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c
@@ -102,7 +102,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
@@ -140,7 +140,7 @@ MemPConstructPsUDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DA DDR3
@@ -165,7 +165,7 @@ MemPDoPsUDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
index 059d854..a3049c9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
@@ -99,7 +99,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
@@ -137,7 +137,7 @@ MemPConstructPsRDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
index 589fd37..4f599a4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
@@ -114,7 +114,7 @@ STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
{DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
{DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
@@ -152,7 +152,7 @@ MemPConstructPsRDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
index a30fbf9..2a61059 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
@@ -102,7 +102,7 @@ STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
@@ -139,7 +139,7 @@ MemPConstructPsSDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
index f08fd34..2c570ec 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
@@ -99,7 +99,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
@@ -137,7 +137,7 @@ MemPConstructPsUDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
index 778f4b9..e012dbb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
@@ -95,7 +95,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
@@ -132,7 +132,7 @@ MemPConstructPsUDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c
index 7ef0d0a..ac6f73b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c
@@ -165,7 +165,7 @@ STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
@@ -203,7 +203,7 @@ MemPConstructPsRHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 HY DDR3
@@ -259,7 +259,7 @@ MemPDoPsRHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c
index 41698ac..eb63bb7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c
@@ -107,7 +107,7 @@ STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
@@ -144,7 +144,7 @@ MemPConstructPsSHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 HY DDR3
@@ -193,7 +193,7 @@ MemPDoPsSHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c
index 7cfc9c5..40ff34f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c
@@ -102,7 +102,7 @@ STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
@@ -139,7 +139,7 @@ MemPConstructPsUHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 HY DDR3
@@ -164,7 +164,7 @@ MemPDoPsUhy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c
index 130b468..de504b3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c
@@ -86,7 +86,7 @@ MemPDoPsRLN3 (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 LN DDR3
@@ -124,7 +124,7 @@ MemPConstructPsRLN3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 LN DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
index 2803a39..712c7cd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY LnSDdr3DramTerm[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600 + DDR1866, TWO_DIMM, NO_DIMM, 4, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 LN DDR3
@@ -138,7 +138,7 @@ MemPConstructPsSLN3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 LN DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c
index 0afab69..6f0ebf0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY LnUDdr3DramTerm[] = {
{DDR1600 + DDR1866, TWO_DIMM, NO_DIMM, 4, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 LN DDR3
@@ -138,7 +138,7 @@ MemPConstructPsULN3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 LN DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c
index 37ab159..8dea86e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c
@@ -109,7 +109,7 @@ STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
@@ -147,7 +147,7 @@ MemPConstructPsSNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ni DDR3
@@ -196,7 +196,7 @@ MemPDoPsSNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c
index 004b7f8..542a597 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
@@ -142,7 +142,7 @@ MemPConstructPsUNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ni DDR3
@@ -167,7 +167,7 @@ MemPDoPsUNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c
index 89e4698..02f476a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c
@@ -108,7 +108,7 @@ STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ph DDR3
@@ -146,7 +146,7 @@ MemPConstructPsSPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ph DDR3
@@ -195,7 +195,7 @@ MemPDoPsSPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c
index ea5901c..e82f8f3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3
@@ -141,7 +141,7 @@ MemPConstructPsUPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ph DDR3
@@ -166,7 +166,7 @@ MemPDoPsUPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c
index 6890f65..66d347c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c
@@ -108,7 +108,7 @@ STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM RB DDR3
@@ -146,7 +146,7 @@ MemPConstructPsSRb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM RB DDR3
@@ -195,7 +195,7 @@ MemPDoPsSRb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c
index 0379060..cd9eba6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
@@ -141,7 +141,7 @@ MemPConstructPsURb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 RB DDR3
@@ -166,7 +166,7 @@ MemPDoPsURb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
index 2d261f8..1a66c8f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
@@ -98,7 +98,7 @@ MemPPSCGen (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -122,7 +122,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -170,7 +170,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -226,7 +226,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
@@ -243,7 +243,7 @@ MemPGetPORFreqLimitDef (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -298,7 +298,7 @@ MemPPSCFlow (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -350,7 +350,7 @@ MemPConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -386,7 +386,7 @@ MemPIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -431,7 +431,7 @@ MemPGetPsRankType (
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs the action for the rest of platform specific configuration such as
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c
index 91cfeee..bc0a0f6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c
@@ -94,7 +94,7 @@ MemPGetLRIBT (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c
index 2c69768..ee76e74 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c
@@ -92,7 +92,7 @@ MemPGetLRNLR (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c
index 25186e3..c09d86e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c
@@ -92,7 +92,7 @@ MemPGetLRNPR (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c
index f6f90f9..81acf97 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c
@@ -108,7 +108,7 @@ MemPGetMaxFreqSupported (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts the value of max frequency supported from a input table and
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c
index a6c8b40..e282724 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c
@@ -92,7 +92,7 @@ MemPGetMR0WrCL (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c
index 0f1a4a9..a4b5f0f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c
@@ -94,7 +94,7 @@ MemPGetODTPattern (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c
index df92a4b..17d1481 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c
@@ -93,7 +93,7 @@ MemPGetRC10OpSpd (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC10 operating speed value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c
index ac4e345..3e32b84 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c
@@ -93,7 +93,7 @@ MemPGetRC2IBT (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c
index 338f2a0..c775032 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c
@@ -97,7 +97,7 @@ MemPGetRttNomWr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c
index 9503061..de90f32 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c
@@ -95,7 +95,7 @@ MemPGetSAO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
index be9033a..04dde64 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
index a45a970..0f2560b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR2.
@@ -110,7 +110,7 @@ MemTAdjustTwrwr2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR2.
@@ -135,7 +135,7 @@ MemTAdjustTwrrd2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c
index 680ecab..300911b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c
@@ -131,7 +131,7 @@ MemTGetBankAddr2 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -150,7 +150,7 @@ MemTSetDramMode2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -384,7 +384,7 @@ MemTDIMMPresence2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
@@ -500,7 +500,7 @@ MemTSPDGetTargetSpeed2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -584,7 +584,7 @@ MemTSPDCalcWidth2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -771,7 +771,7 @@ MemTAutoCycTiming2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -885,7 +885,7 @@ MemTSPDSetBanks2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -917,7 +917,7 @@ MemTGetCSIntLvAddr2 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency.
@@ -935,7 +935,7 @@ MemTSPDGetTCL2 (
return TechPtr->NBPtr->DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -967,7 +967,7 @@ MemTSysCapability2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine whether dimm(b,i) supports CL(j) and F(k)
@@ -1025,7 +1025,7 @@ MemTDimmSupports2 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the cycle time
@@ -1046,7 +1046,7 @@ MemTGetTk2 (
return TableTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1072,7 +1072,7 @@ MemTGetBankAddr2 (
return TabBankAddr[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c
index a18befd..62c5e2e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index e7a76dc..291da7e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -174,7 +174,7 @@ MemTLrdimmSyncTrainedDlys (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes LRDIMM functions.
@@ -204,7 +204,7 @@ MemTLrdimmConstructor3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a Control word command to an LRDIMM Memory Buffer
@@ -246,7 +246,7 @@ MemTSendMBCtlWord3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the value of special RCW
@@ -420,7 +420,7 @@ MemTGetSpecialMBCtlWord3 (
return Value8;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -580,7 +580,7 @@ MemTLrDimmControlRegInit3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -688,7 +688,7 @@ MemTWLPrepareLrdimm3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to all physical ranks of an LRDIMM
@@ -782,7 +782,7 @@ MemTSendAllMRCmdsLR3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value for an LRDIMM
@@ -847,7 +847,7 @@ MemTEMRS1Lr3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value for an LRDIMM
@@ -978,7 +978,7 @@ MemTLrdimmRankMultiplication (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs buffer to DRAM training for LRDIMMs
@@ -1057,7 +1057,7 @@ MemTLrdimmBuf2DramTrain3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function copies trained delays of the first rank of a QR LRDIMM to the third rank
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c
index 29359a4..e9ffeb8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -113,7 +113,7 @@ MemTAdjustTwrwr3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -139,7 +139,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
index b1d5994..fbc0ae4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -147,7 +147,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -210,7 +210,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -247,7 +247,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c
index ea86205..f881d1c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -204,7 +204,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -328,7 +328,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -381,7 +381,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -409,7 +409,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -460,7 +460,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
index dac3df3..ecbf564 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -113,7 +113,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -133,7 +133,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -421,7 +421,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -499,7 +499,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -577,7 +577,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -746,7 +746,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -882,7 +882,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -915,7 +915,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -958,7 +958,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1077,7 +1077,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1112,7 +1112,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c
index 0313763..7b94f29 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
index da42c63..e1bfec9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -131,7 +131,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -151,7 +151,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -175,7 +175,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -198,7 +198,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -232,7 +232,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -286,7 +286,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -338,7 +338,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -385,7 +385,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -532,7 +532,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -654,7 +654,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c
index 624a8b9..db33d10 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c
@@ -91,7 +91,7 @@ MemTDefaultTechnologyHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -106,7 +106,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -134,7 +134,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -168,7 +168,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -198,7 +198,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c
index a2d666e..bb6e2c1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
index 9ae5fe0..dea0307 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
@@ -170,7 +170,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -217,7 +217,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -366,7 +366,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -622,7 +622,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -687,7 +687,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -715,7 +715,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -785,7 +785,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -829,7 +829,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c
index 480cc5c..c8ec02b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c
@@ -225,7 +225,7 @@ MemTFindMinMaxGrossDlyByte (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -317,7 +317,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -346,7 +346,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -372,7 +372,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -409,7 +409,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -468,7 +468,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -546,7 +546,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -605,7 +605,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -632,7 +632,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -662,7 +662,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -686,7 +686,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -701,7 +701,7 @@ MemTMaxByteLanesByte (VOID)
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -716,7 +716,7 @@ MemTDlyTableWidthByte (VOID)
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -754,7 +754,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -806,7 +806,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -876,7 +876,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -937,7 +937,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the minimum or maximum gross dly among all the bytes.
@@ -981,7 +981,7 @@ MemTFindMinMaxGrossDlyByte (
return MinMaxGrossDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1137,7 +1137,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1171,7 +1171,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1304,7 +1304,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c
index a7fd6b5..ac53cd5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c
@@ -94,7 +94,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -143,7 +143,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c
index 82b895c..e3ddb52 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c
@@ -106,7 +106,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -127,7 +127,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -158,7 +158,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -243,7 +243,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
index c2ebc9b..81ac1ea 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -168,7 +168,7 @@ MemTTrackRxEnSeedlessRdWrSmallWindBLError (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the RxEn delay
@@ -190,7 +190,7 @@ MemTRdPosRxEnSeedSetDly3 (
TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel >> 1), ByteLane), RcvEnDly);
TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the currert RxEn delay settings have failed
@@ -210,7 +210,7 @@ MemTRdPosRxEnSeedCheckRxEndly3 (
TechPtr->DqsRdWrPosSaved = 0;
MemTTrainDQSEdgeDetect (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training and if fails adjusts the RxEn Gross results for
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c
index 9acbc90..e744a76 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c
index fb162c3..e98abb7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c
@@ -103,7 +103,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -128,7 +128,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
index 2f30178..05ef005 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
@@ -96,7 +96,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -127,7 +127,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
index f211bd8..4e901fd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
@@ -160,7 +160,7 @@ TableName[BitFieldIndex] = ( \
#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
index bd1c441..4b09e85 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
index d020ad7..7074277 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
@@ -70,7 +70,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs Gnb Recovery related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/NbInitRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/NbInitRecovery.c
index 9d0cb91..a1c936d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/NbInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/NbInitRecovery.c
@@ -91,7 +91,7 @@ CONST NB_REGISTER_RECOVERY_ENTRY NbMiscInitRecoveryTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at Power On
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
index dced7d5..e875444 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
@@ -56,7 +56,7 @@ RDATA_GROUP (G2_PEI)
#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get new Socket and Node Maps.
*
@@ -111,7 +111,7 @@ NewNodeAndSocketTablesRecovery (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitReset.c
index db4cb9e..44aebcc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitReset.c
@@ -113,7 +113,7 @@ typedef struct {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Routing Tables.
*
@@ -139,7 +139,7 @@ HtrEnableRoutingTables (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process the SouthBridge Link.
*
@@ -295,7 +295,7 @@ AmdHtResetConstructor (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize HT for Reset, Boot Blocks.
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.c
index 3ea7bb7..f1210e6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.c
@@ -148,7 +148,7 @@ STATIC CONST UINT32 RecModeDefRegArrayC32[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -276,7 +276,7 @@ MemRecConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -302,7 +302,7 @@ MemRecNSwitchNodeC32 (
MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -327,7 +327,7 @@ MemRecNSwitchDctC32 (
MemRecNSwitchChannelC32 (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -355,7 +355,7 @@ MemRecNSwitchChannelC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -485,7 +485,7 @@ MemRecNcmnGetSetTrainDlyC32 (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -593,7 +593,7 @@ MemRecNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -696,7 +696,7 @@ MemRecNInitNBRegTableC32 (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
index 7b46c44..03e1b89 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -122,7 +122,7 @@ MemRecNFinalizeMctC32 (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.c
index 28b579e..cdd50fe 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.c
@@ -139,7 +139,7 @@ STATIC CONST UINT32 RecModeDefRegArrayDA[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -264,7 +264,7 @@ MemRecConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -288,7 +288,7 @@ MemRecNSwitchDctDA (
MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -315,7 +315,7 @@ MemRecNSwitchChannelDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -430,7 +430,7 @@ MemRecNcmnGetSetTrainDlyDA (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -533,7 +533,7 @@ MemRecNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -638,7 +638,7 @@ MemRecNInitNBRegTableDA (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnmctda.c
index 7919584..eebe24c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnmctda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnmctda.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -125,7 +125,7 @@ MemRecNFinalizeMctDA (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.c
index 55def5d..75426d7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.c
@@ -139,7 +139,7 @@ STATIC CONST UINT32 RecModeDefRegArrayDR[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -264,7 +264,7 @@ MemRecConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -289,7 +289,7 @@ MemRecNSwitchDctDR (
MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -316,7 +316,7 @@ MemRecNSwitchChannelDR (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -431,7 +431,7 @@ MemRecNcmnGetSetTrainDlyDR (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -534,7 +534,7 @@ MemRecNCmnGetSetFieldDR (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -640,7 +640,7 @@ MemRecNInitNBRegTableDR (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
index 1cfff88..19f747a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -127,7 +127,7 @@ MemRecNFinalizeMctDR (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.c
index 9f9af1f..d3b0c0c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.c
@@ -147,7 +147,7 @@ STATIC CONST UINT32 RecModeDefRegArrayHy[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -275,7 +275,7 @@ MemRecConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -301,7 +301,7 @@ MemRecNSwitchNodeHy (
MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -326,7 +326,7 @@ MemRecNSwitchDctHy (
MemRecNSwitchChannelHy (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -354,7 +354,7 @@ MemRecNSwitchChannelHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -484,7 +484,7 @@ MemRecNcmnGetSetTrainDlyHy (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -592,7 +592,7 @@ MemRecNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -696,7 +696,7 @@ MemRecNInitNBRegTableHy (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
index 347493c..b5f409a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -122,7 +122,7 @@ MemRecNFinalizeMctHy (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
index 6a6fdb8..8c3e02f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -156,7 +156,7 @@ MemRecNPlatformSpecLN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -199,7 +199,7 @@ MemRecNSetMaxLatencyLN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -264,7 +264,7 @@ MemRecNSetDramOdtLN (
MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.c
index 384f96a..9a7b359 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.c
@@ -136,7 +136,7 @@ MemRecNIsIdSupportedLN (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -263,7 +263,7 @@ MemRecConstructNBBlockLN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -288,7 +288,7 @@ MemRecNSwitchDctLN (
MemRecNSwitchChannelLN (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -316,7 +316,7 @@ MemRecNSwitchChannelLN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -428,7 +428,7 @@ MemRecNcmnGetSetTrainDlyLN (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -533,7 +533,7 @@ MemRecNCmnGetSetFieldLN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -699,7 +699,7 @@ MemRecNInitNBRegTableLN (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnmctln.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnmctln.c
index 5c31d44..15e0305 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnmctln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnmctln.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for LN DDR3
@@ -139,7 +139,7 @@ MemRecNMemInitLN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final values for specific registers
@@ -166,7 +166,7 @@ MemRecNFinalizeMctLN (
MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG2
@@ -193,7 +193,7 @@ MemRecNInitializeMctLN (
LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.c
index f6187ab..91d26b4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.c
@@ -140,7 +140,7 @@ STATIC CONST UINT32 RecModeDefRegArrayNi[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -264,7 +264,7 @@ MemRecConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -288,7 +288,7 @@ MemRecNSwitchDctNi (
MemRecNSwitchChannelNi (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -315,7 +315,7 @@ MemRecNSwitchChannelNi (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -430,7 +430,7 @@ MemRecNcmnGetSetTrainDlyNi (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -533,7 +533,7 @@ MemRecNCmnGetSetFieldNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -638,7 +638,7 @@ MemRecNInitNBRegTableNi (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedNi
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.c
index 12d404f..9d5c5ed 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.c
@@ -140,7 +140,7 @@ STATIC CONST UINT32 RecModeDefRegArrayPh[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -265,7 +265,7 @@ MemRecConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -289,7 +289,7 @@ MemRecNSwitchDctPh (
MemRecNSwitchChannelPh (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -316,7 +316,7 @@ MemRecNSwitchChannelPh (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -431,7 +431,7 @@ MemRecNcmnGetSetTrainDlyPh (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -534,7 +534,7 @@ MemRecNCmnGetSetFieldPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -639,7 +639,7 @@ MemRecNInitNBRegTablePh (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.c
index 01dba47..7444712 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.c
@@ -140,7 +140,7 @@ STATIC CONST UINT32 RecModeDefRegArrayRb[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -264,7 +264,7 @@ MemRecConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -288,7 +288,7 @@ MemRecNSwitchDctRb (
MemRecNSwitchChannelRb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -315,7 +315,7 @@ MemRecNSwitchChannelRb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -430,7 +430,7 @@ MemRecNcmnGetSetTrainDlyRb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -533,7 +533,7 @@ MemRecNCmnGetSetFieldRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -638,7 +638,7 @@ MemRecNInitNBRegTableRb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
index 502f5e2..38a0e37 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
@@ -91,7 +91,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a bit field from PCI register
@@ -113,7 +113,7 @@ MemRecNGetBitFieldNb (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets a bit field from PCI register
@@ -134,7 +134,7 @@ MemRecNSetBitFieldNb (
NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
@@ -157,7 +157,7 @@ MemRecNGetTrainDlyNb (
return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
index 86c68ae..7a4c020 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
@@ -132,7 +132,7 @@ MemRecNCommonReadWritePatternUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
@@ -227,7 +227,7 @@ MemRecNAutoConfigNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -259,7 +259,7 @@ MemRecNPlatformSpecNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function reads MemClkFreqVal bit to see if the DIMMs are present in this node.
@@ -304,7 +304,7 @@ MemRecNStartupDCTNb (
while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DRAM devices on all DCTs at the same time
@@ -347,7 +347,7 @@ MemRecNStartupDCTClientNb (
IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", DDR800_FREQUENCY);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -415,7 +415,7 @@ MemRecNSetMaxLatencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -457,7 +457,7 @@ MemRecNSetDramOdtNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -507,7 +507,7 @@ MemRecNSendMrsCmdNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends the ZQCL command
@@ -535,7 +535,7 @@ MemRecNSendZQCmdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -567,7 +567,7 @@ MemRecTCtlOnDimmMirrorNb (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -596,7 +596,7 @@ MemRecNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -654,7 +654,7 @@ MemRecNTotalSyncComponentsClientNb (
return ((P * MemClkPeriod + 1) / 2) + T;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -684,7 +684,7 @@ MemRecNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -750,7 +750,7 @@ MemRecNTrainPhyFenceNb (
MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -853,7 +853,7 @@ MemRecNProgNbPstateDependentRegClientNb (
MemRecNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -898,7 +898,7 @@ MemRecNContReadPatternClientNb (
MemRecNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with UDIMMs configuration
@@ -983,7 +983,7 @@ MemRecNGetPsCfgUDIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with SODIMMs configuration
@@ -1071,7 +1071,7 @@ MemRecNGetPsCfgSODIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with RDIMMs configuration
@@ -1234,7 +1234,7 @@ MemRecNGetPsCfgRDIMM3Nb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1270,7 +1270,7 @@ RecGetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -1294,7 +1294,7 @@ MemRecNGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -1437,7 +1437,7 @@ MemRecNcmnGetSetTrainDlyClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1461,7 +1461,7 @@ MemRecNContReadPatternUnb (
MemRecNCommonReadWritePatternUnb (NBPtr, CMD_TYPE_READ, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1485,7 +1485,7 @@ MemRecNContWritePatternUnb (
MemRecNCommonReadWritePatternUnb (NBPtr, CMD_TYPE_WRITE, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates either read or write DRAM cycles for training
@@ -1538,7 +1538,7 @@ MemRecNCommonReadWritePatternUnb (
MemRecNSetBitFieldNb (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results using PRBS
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrnmct.c
index a4bf1cb..4345db1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrnmct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrnmct.c
@@ -87,7 +87,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for Nb DDR3
@@ -148,7 +148,7 @@ MemRecNMemInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a physical address of a corresponding Chip select
@@ -170,7 +170,7 @@ MemRecNGetMCTSysAddrNb (
return CSBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
@@ -235,7 +235,7 @@ MemRecNCPUMemRecTypingNb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
index 507e8ab..2193884 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -81,7 +81,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -101,7 +101,7 @@ MemNRecTrainingFlowNb (
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the client training control flow
@@ -136,7 +136,7 @@ MemNRecTrainingFlowClientNb (
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrp.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrp.c
index d5d3e3a..51d0e7f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrp.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrp.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -135,7 +135,7 @@ MemPRecPSCFlow (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -187,7 +187,7 @@ MemPRecConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -223,7 +223,7 @@ MemPRecIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplribt.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplribt.c
index e7daa68..b80eb1a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplribt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplribt.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnlr.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnlr.c
index ba30320..0826521 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnlr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnlr.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnpr.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnpr.c
index bd56747..004eabf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnpr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrplrnpr.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpmr0.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpmr0.c
index ded4fab..2f66f47 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpmr0.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpmr0.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpodtpat.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpodtpat.c
index ca7798f..1aae4fd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpodtpat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpodtpat.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprc2ibt.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprc2ibt.c
index 5b4c777..e3d7412 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprc2ibt.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprtt.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprtt.c
index f222172..5a47d22 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprtt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrprtt.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpsao.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpsao.c
index 2beb511..6443b66 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpsao.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Ps/mrpsao.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
index 1c084ba..60d57a0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
@@ -120,7 +120,7 @@ MemRecConstructTechBlock3 (
TechPtr->DimmPresence = MemRecTDIMMPresence3;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -151,7 +151,7 @@ MemRecTBeginTraining (
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
index dafef83..6bc7fa0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
@@ -102,7 +102,7 @@ MemRecTSendCtlWord3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -146,7 +146,7 @@ MemRecTDramControlRegInit3 (
MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -195,7 +195,7 @@ MemRecTGetCtlWord3 (
return (Data&0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
index 0c813a0..36d4587 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init
@@ -180,7 +180,7 @@ MemRecTDramInitSw3 (
IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -236,7 +236,7 @@ MemRecTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -283,7 +283,7 @@ MemRecTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -312,7 +312,7 @@ MemRecTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MSS value
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
index 11ec0da..299a1d5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -111,7 +111,7 @@ MemRecTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
index b457d47..40f223b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
@@ -109,7 +109,7 @@ MemRecTBeginWLTrain3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -176,7 +176,7 @@ MemRecTTrainDQSWriteHw3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -233,7 +233,7 @@ MemRecTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function configures the DIMMS for Write Levelization
@@ -304,7 +304,7 @@ MemRecTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
index 129532f..bc21bb3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -105,7 +105,7 @@ MemRecTProgramRcvrEnDly (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -177,7 +177,7 @@ MemRecTTrainRcvrEnHw (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -271,7 +271,7 @@ MemRecTPrepareRcvrEnDlySeed (
);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
index da6bf9d..711f83b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
@@ -104,7 +104,7 @@ MemRecTProgramRcvrEnDly (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training without
@@ -231,7 +231,7 @@ MemRecTTrainRcvrEnHwSeedless (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -259,7 +259,7 @@ MemRecTPrepareRcvrEnDlySeed (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
index 67ac527..49cb91b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function hard-codes DQS position delays for all bytes
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttsrc.c
index 3890b87..8618ebd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttsrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttsrc.c
@@ -122,7 +122,7 @@ MemRecTCompare1ClPattern (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for BSP
@@ -230,7 +230,7 @@ MemRecTTrainRcvrEnSw (
MemRecTEndTraining (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* If WrDatDly is 0, this function sets the DQS Positions in preparation
@@ -267,7 +267,7 @@ MemRecTSetWrDatRdDqs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -295,7 +295,7 @@ MemRecTSetRcvrEnDly (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -344,7 +344,7 @@ MemRecTCompare1ClPattern (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -398,7 +398,7 @@ MemRecTSaveRcvrEnDly (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
index 626cd1f..ebb5411 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -91,7 +91,7 @@ MemRecDefRet ()
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -104,7 +104,7 @@ MemRecDefTrue ()
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the DCT with initial values
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrinit.c
index 0013dfb..8a06d78 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrinit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrinit.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G2_PEI)
extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
extern MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default parameter, function pointers, build options
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrm.c
index d9cdf82..fede49c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrm.c
@@ -98,7 +98,7 @@ MemRecSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for HY DDR3
@@ -202,7 +202,7 @@ AmdMemRecovery (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
index d0fa900..2b0ca1b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
@@ -99,7 +99,7 @@ MemRecUSetTargetWTIO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (Index)th UINT8
@@ -125,7 +125,7 @@ MemRecUFillTrainPattern (
LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -152,7 +152,7 @@ MemRecUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -170,7 +170,7 @@ MemRecUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -197,7 +197,7 @@ MemRecUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // ;64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -221,7 +221,7 @@ MemRecUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
diff --git a/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
index a467008..66bb150 100644
--- a/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
@@ -186,7 +186,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
index 2fe7ed7..7fc0df7 100644
--- a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
+++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
@@ -62,7 +62,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset Stub
*
@@ -81,7 +81,7 @@ GnbInitAtReset (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Stub
*
@@ -99,7 +99,7 @@ GnbInitAtEarly (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -117,7 +117,7 @@ GnbInitDataStructAtEnvDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
@@ -136,7 +136,7 @@ GnbInitAtEnv (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -155,7 +155,7 @@ GnbInitAtPost (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
@@ -174,7 +174,7 @@ GnbInitAtMid (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
@@ -193,7 +193,7 @@ GnbInitAtLate (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AmdGnbRecovery
*
@@ -210,7 +210,7 @@ AmdGnbRecovery (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
index 97b2d41..de76dcb 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
@@ -80,7 +80,7 @@ BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
index 8ca47c0..23b720b 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
@@ -64,7 +64,7 @@ RDATA_GROUP (G1_PEICC)
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -130,7 +130,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
index bc1a2fb..7c8f6db 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
@@ -84,7 +84,7 @@ AgesaGetIdsData (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -111,7 +111,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -136,7 +136,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -159,7 +159,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -184,7 +184,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -208,7 +208,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -232,7 +232,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -256,7 +256,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -280,7 +280,7 @@ AgesaHookBeforeDramInitRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -303,7 +303,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -326,7 +326,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -349,7 +349,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -375,7 +375,7 @@ AgesaGetIdsData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
index c61acd5..e5d5403 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -263,7 +263,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
index f858906..59aec46 100644
--- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
@@ -460,7 +460,7 @@ StopHere (
while (x);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -497,7 +497,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -534,7 +534,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -564,7 +564,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -597,7 +597,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -634,7 +634,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -671,7 +671,7 @@ LibAmdMemWrite (
ASSERT (FALSE);
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -701,7 +701,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -734,7 +734,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -783,7 +783,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -832,7 +832,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -862,7 +862,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -895,7 +895,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -930,7 +930,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -963,7 +963,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1003,7 +1003,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1077,7 +1077,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1103,7 +1103,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1131,7 +1131,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1167,7 +1167,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1217,7 +1217,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1239,7 +1239,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1283,7 +1283,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c
index 8ec99e9..5c630e9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c
@@ -90,7 +90,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
index 1c1b5ed..fbf44e7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
@@ -84,7 +84,7 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 10h CPU.
*
@@ -125,7 +125,7 @@ F10InitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 10h core.
*
@@ -144,7 +144,7 @@ F10InitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -166,7 +166,7 @@ F10GetAcpiCstObj (
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -242,7 +242,7 @@ F10CreateAcpiCstObj (
*PstateAcpiBufferPtr = CstBodyPtr;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether IO Cstate should be supported.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index 9911229..8ff0520 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -86,7 +86,7 @@ SetAsymBoost (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Asymmetric Boost
* Configuration" algorithm.
@@ -145,7 +145,7 @@ F10PmAsymBoostInit (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set Asymmetric Boost.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index a8c917c..e9f4bbb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -87,7 +87,7 @@ SetPstateMSR (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
*
@@ -193,7 +193,7 @@ F10PmDualPlaneOnlySupport (
}
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set P-State MSR.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 5558a90..75cb2f9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -103,7 +103,7 @@ PmNbCofVidInitWarmCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
@@ -228,7 +228,7 @@ F10PmNbCofVidInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
@@ -260,7 +260,7 @@ PmNbCofVidInitP0P1Core (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index 0fb4a96..c6ca448 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -92,7 +92,7 @@ PmNbPstateInitCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
@@ -152,7 +152,7 @@ F10PmNbPstateInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmNbPstateInit.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
index 8edb7fd..9126146 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable BL-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 56c663f..da9496c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -77,7 +77,7 @@ STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 124b865..d07f5c7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -77,7 +77,7 @@ extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
index b23f848..6e6963c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index 03e830e..a73b84c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -78,7 +78,7 @@ STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 65f72a9..274e1bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -77,7 +77,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
index 505a097..518eb3b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -82,7 +82,7 @@ F10InitializeHwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -109,7 +109,7 @@ F10IsHwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h CPU.
*
@@ -149,7 +149,7 @@ F10InitializeHwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
index bb1127c..9c655cc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
@@ -81,7 +81,7 @@ F10InitializeSwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -101,7 +101,7 @@ F10IsSwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h CPU.
*
@@ -142,7 +142,7 @@ F10InitializeSwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 46d8e25..c3b1080 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision C processor.
*
@@ -165,7 +165,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision C processor.
*
@@ -251,7 +251,7 @@ F10CommonRevCGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -282,7 +282,7 @@ F10CommonRevCGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -353,7 +353,7 @@ F10CommonRevCGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -398,7 +398,7 @@ F10CommonRevCIsNbPstateEnabled (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index c17935d..6f79409 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -80,7 +80,7 @@ STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index 96f03a2..b92528e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -77,7 +77,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
index 35de6cd..a4f1bcd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
@@ -115,7 +115,7 @@ F10RevDProbeFilterCritical (
IN UINT32 PciRegister
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports HT Assist.
*
@@ -157,7 +157,7 @@ F10IsHtAssistSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the Probe filter feature.
*
@@ -206,7 +206,7 @@ F10HtAssistInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save the current settings of the scrubbers, and disabled them.
*
@@ -261,7 +261,7 @@ F10GetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restore the initial settings for the scrubbers.
*
@@ -309,7 +309,7 @@ F10SetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set MSR bits required for HT Assist on each core.
*
@@ -332,7 +332,7 @@ F10HookDisableCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Hook before the probe filter initialization sequence.
*
@@ -388,7 +388,7 @@ F10HookBeforeInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU is running in the optimal configuration.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
index 6a3cbb9..96dffae 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -93,7 +93,7 @@ IsDramScrubberEnabled (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -118,7 +118,7 @@ F10IsMsgBasedC1eSupported (
return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
@@ -206,7 +206,7 @@ F10InitializeMsgBasedC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable message-based C1e on a family 10h core.
*
@@ -239,7 +239,7 @@ F10InitializeMsgBasedC1eOnCore (
LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 5abf849..69f2a3f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision D processor.
*
@@ -174,7 +174,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
F10CommonRevDSetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision D processor.
*
@@ -248,7 +248,7 @@ F10CommonRevDGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -274,7 +274,7 @@ F10CommonRevDGetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -322,7 +322,7 @@ F10CommonRevDGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index 11069fb..52f8e08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -77,7 +77,7 @@ STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
index a823e67..5eafeda 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -94,7 +94,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 6aa6f85..4a5301f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -77,7 +77,7 @@ extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
index bbad939..0d07630 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision E processor.
*
@@ -174,7 +174,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
F10CommonRevESetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision E processor.
*
@@ -250,7 +250,7 @@ F10CommonRevEGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -298,7 +298,7 @@ F10CommonRevEGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -329,7 +329,7 @@ F10CommonRevEGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index c5453e0..55a5602 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -76,7 +76,7 @@ STATIC CONST UINT16 ROMDATA CpuF10PhMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index b818350..373cae0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -76,7 +76,7 @@ extern CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
index ddea5b5..dfe0916 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -94,7 +94,7 @@ typedef union {
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -131,7 +131,7 @@ F10SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -163,7 +163,7 @@ F10GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -197,7 +197,7 @@ F10GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the system AP core number in the AP's Mailbox.
*
@@ -235,7 +235,7 @@ F10SetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -262,7 +262,7 @@ F10GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Move the AP's core number from the mailbox to hardware.
*
@@ -299,7 +299,7 @@ F10TransferApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
index e07c653..8b5c3fc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -83,7 +83,7 @@ extern CONST UINT8 F10BrandIdString2TableCount;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -111,7 +111,7 @@ GetF10BrandIdString1 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 4ad4879..857269a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -97,7 +97,7 @@ CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
index 2bab20a..5d52b51 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c
index c0a5490..bf68d0d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -117,7 +117,7 @@ F10IsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 4611dc7..4f8fba2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -85,7 +85,7 @@ F10Translate7BitVidTo6Bit (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetInfo
@@ -151,7 +151,7 @@ DmiF10GetInfo (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetVoltage
@@ -209,7 +209,7 @@ DmiF10GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMaxSpeed
@@ -251,7 +251,7 @@ DmiF10GetMaxSpeed (
return ((UINT16) P0Frequency);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetExtClock
@@ -271,7 +271,7 @@ DmiF10GetExtClock (
return (EXTERNAL_CLOCK_DFLT);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMemInfo
@@ -448,7 +448,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* F10Translate7BitVidTo6Bit
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index c2496f5..bb0d112 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -100,7 +100,7 @@ WaitForCpuFidAndDidToMatch (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -202,7 +202,7 @@ F10PmAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
@@ -377,7 +377,7 @@ F10PmAfterResetCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index fff369c..3764fd9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -89,7 +89,7 @@ updateCpuFeatureList (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function get features which CPU supports.
@@ -208,7 +208,7 @@ F10SaveFeatures (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function set features which All CPUs support.
@@ -315,7 +315,7 @@ F10WriteFeatures (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* cpuFeatureListNeedUpdate
@@ -356,7 +356,7 @@ cpuFeatureListNeedUpdate (
return flag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* updateCpuFeatureList
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index a2dc740..14375c4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -95,7 +95,7 @@ F10PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the family 10h Processor-
* Systemboard Power Delivery Check.
@@ -304,7 +304,7 @@ F10PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -392,7 +392,7 @@ F10PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
index 6d4150d..bfe9f61 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*/
/* Family 10h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
{
IDS_INITIAL_F10_PM_STEP
@@ -146,7 +146,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
index c2bda35..eb1cc21 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -141,7 +141,7 @@ F10PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
@@ -301,7 +301,7 @@ F10CpuAmdPmPwrPlaneInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10CpuAmdPmPwrPlaneInit.
*
@@ -339,7 +339,7 @@ F10PmPwrPlaneInitPviCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded altvid voltage stabilization slam time for the executing
* family 10h core.
@@ -407,7 +407,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
index 436f441..5d474f2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -104,7 +104,7 @@ F10GetFrequencyXlatRegInfo (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -173,7 +173,7 @@ F10SetTscFreqSel (
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -282,7 +282,7 @@ F10GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -339,7 +339,7 @@ F10GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer.
*
@@ -487,7 +487,7 @@ F10PstateLevelingCoreMsrModify (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -584,7 +584,7 @@ F10GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -625,7 +625,7 @@ F10GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
@@ -778,7 +778,7 @@ F10GetPllValueInTime (
*PllLockTimePtr = 0;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
index 40f3419..6421e3e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
index c3791f2..6554aad 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -96,7 +96,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated CPU
* Voltage Transitions.'
@@ -134,7 +134,7 @@ F10PmSwVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated NB
* Voltage Transitions.'
@@ -184,7 +184,7 @@ F10PmSwVoltageTransitionServerNb (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current VsSlamTime in microseconds.
*
@@ -225,7 +225,7 @@ F10GetCurrentVsTimeInUsecs (
*VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until VsSlamTime microseconds have expired.
*
@@ -246,7 +246,7 @@ F10WaitOutVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Code required to be run on every local core in order to perform
* the steps necessary for 'Software Initiated NB Voltage
@@ -291,7 +291,7 @@ F10SwVoltageTransitionServerNbCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
*
@@ -375,7 +375,7 @@ F10ProgramVSSlamTimeOnSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded voltage stabilization slam time for the executing
* family 10h core.
@@ -436,7 +436,7 @@ F10GetSlamTimeEncoding (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -464,7 +464,7 @@ F10DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -501,7 +501,7 @@ F10TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -536,7 +536,7 @@ F10GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -584,7 +584,7 @@ F10GetCurrentNbFrequency (
return ReturnCode;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -705,7 +705,7 @@ F10LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -729,7 +729,7 @@ F10GetPlatformTypeSpecificInfo (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the next HT link.
*
@@ -854,7 +854,7 @@ F10GetNextHtLinkFeatures (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -1045,7 +1045,7 @@ F10NextLinkHasHtPhyFeats (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
index d59ba9b..6f1bb2b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -92,7 +92,7 @@ AMD_WHEA_INIT_DATA F10WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
index f198cae..363fe39 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
@@ -78,7 +78,7 @@ extern F14_ES_C6_SUPPORT F14EarlySampleC6Support;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -116,7 +116,7 @@ F14IsC6Supported (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C6 on a family 14h CPU.
*
@@ -191,7 +191,7 @@ F14InitializeC6 (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch for a family 14h CPU after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
index 41a672f..17f50f1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
@@ -85,7 +85,7 @@ F14InitializeIoCstateOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 14h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
@@ -153,7 +153,7 @@ F14InitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C-State on a family 14h core.
*
@@ -172,7 +172,7 @@ F14InitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -194,7 +194,7 @@ F14GetAcpiCstObj (
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
index ec58faa..ab635db 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -115,7 +115,7 @@ F14OnIsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
index fb181eb..5f00e02 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
@@ -95,7 +95,7 @@ STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
index 0c3646c..dc660ba 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
@@ -125,7 +125,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F14OnEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
@@ -151,7 +151,7 @@ GetF14OnEarlyInitOnCoreTable (
F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor for Family14h ON.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
index 77bc2b9..c049591 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
@@ -80,7 +80,7 @@ GetF14OnMicroCodePatchesStruct (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
index ac625ec..1f286be 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
@@ -130,7 +130,7 @@ RoundedDivision (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -167,7 +167,7 @@ F14SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -199,7 +199,7 @@ F14GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -227,7 +227,7 @@ F14GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -254,7 +254,7 @@ F14GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
@@ -275,7 +275,7 @@ F14CpuAmdCoreIdPositionInInitialApicId (
return (CoreIdPositionOne);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up a valid set of NB P-states based on the value of MEMCLK, transitions
* to the desired NB P-state, and returns the current NB frequency in megahertz.
@@ -506,7 +506,7 @@ F14NbPstateInit (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs integer division, and rounds the quotient up if the remainder is greater
* than or equal to 50% of the divisor.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
index a160bce..b41497a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
@@ -95,7 +95,7 @@ extern CONST UINT8 F14BrandIdString2TableCount;
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -122,7 +122,7 @@ GetF14BrandIdString1 (
*NumberOfElements = F14BrandIdString1TableCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
index 75606b9..90615e0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
@@ -101,7 +101,7 @@ CONST CACHE_INFO ROMDATA CpuF14CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
index 8a2106f..aecdc99 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
@@ -104,7 +104,7 @@ DmiF14GetMemInfo (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF14GetInfo
@@ -151,7 +151,7 @@ DmiF14GetInfo (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF14GetVoltage
@@ -199,7 +199,7 @@ DmiF14GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF14GetMaxSpeed
@@ -240,7 +240,7 @@ DmiF14GetMaxSpeed (
return ((UINT16) P0Frequency);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF14GetExtClock
@@ -260,7 +260,7 @@ DmiF14GetExtClock (
return (EXTERNAL_CLOCK_100MHZ);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF14GetMemInfo
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
index 65ded02..80bd8e0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
index 956bd77..699e1bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
@@ -92,7 +92,7 @@ F14PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor-
* Systemboard Power Delivery Check.
@@ -301,7 +301,7 @@ F14PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -425,7 +425,7 @@ F14PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
index 6185b16..31795d1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
@@ -84,7 +84,7 @@ GetF14SysPmTable (
*/
/* Family 14h Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
{
IDS_INITIAL_F14_PM_STEP
@@ -119,7 +119,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
index 20af402..23b6adb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
@@ -102,7 +102,7 @@ F14PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 14h core 0 entry point for performing power plane initialization.
*
@@ -184,7 +184,7 @@ F14PmPwrPlaneInit (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
index c25924d..9de53be 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
@@ -140,7 +140,7 @@ F14SetTscFreqSel (
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -171,7 +171,7 @@ F14GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -248,7 +248,7 @@ F14GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*--------------------------------------------------------------------------------------*/
+
/**
*
* Family specific call to calculates the power in milliWatts of the desired P-state.
@@ -310,7 +310,7 @@ F14GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -345,7 +345,7 @@ F14GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
index 176e2e5..bc31907 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the SW Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
index 5fef702..7400f63 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
@@ -141,7 +141,7 @@ F14ConvertEnabledBitsIntoCount (
*EnabledCoreCountPtr = EnabledCoreCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -169,7 +169,7 @@ F14DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -206,7 +206,7 @@ F14TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -241,7 +241,7 @@ F14GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -280,7 +280,7 @@ F14GetCurrentNbFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -338,7 +338,7 @@ F14GetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -366,7 +366,7 @@ F14IsNbPstateEnabled (
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -392,7 +392,7 @@ F14GetNbCofVidUpdate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -448,7 +448,7 @@ F14LaunchApCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -473,7 +473,7 @@ F14GetPlatformTypeSpecificInfo (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current.
*
@@ -540,7 +540,7 @@ F14GetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get number of processor cores to be used in determining the brand string.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
index 857b333..a9665c2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
@@ -96,7 +96,7 @@ AMD_WHEA_INIT_DATA F14WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c
index 0d8de96..d997164 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The contents of the mailbox registers should always be preserved.
*
@@ -104,7 +104,7 @@ IsPreserveAroundMailboxEnabled (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c
index 47db47a..48e1a7d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c
@@ -91,7 +91,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -129,7 +129,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -204,7 +204,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
@@ -233,7 +233,7 @@ EnableC6OnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h
index 66e787f..172a6c8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h
@@ -61,7 +61,7 @@ AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
@@ -104,7 +104,7 @@ typedef AGESA_STATUS F_C6_INIT (
/// Reference to a Method.
typedef F_C6_INIT *PF_C6_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to reload microcode patch after memory is initialized.
*
@@ -133,7 +133,7 @@ struct _C6_FAMILY_SERVICES {
PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index fea677c..92c5c08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -109,7 +109,7 @@ InitializeCacheFlushOnHaltFeature (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -129,7 +129,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
@@ -166,7 +166,7 @@ InitializeCacheFlushOnHaltFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
index f5772e9..3104dcb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
@@ -144,7 +144,7 @@ IsPowerOfTwo (
IN UINT32 TestNumber
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -421,7 +421,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -514,7 +514,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -539,7 +539,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
@@ -587,7 +587,7 @@ CalculateOccupiedExeCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function compares two memory regions for overlap and returns the combined
* Base,Size to describe the new combined region.
@@ -715,7 +715,7 @@ CompareRegions (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This local function tests the parameter for being an even power of two
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
index 7850510..98cdc1d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -95,7 +95,7 @@ extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -123,7 +123,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c
index 4ab5b3d..53e7a7f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c
@@ -75,7 +75,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should CPB be enabled
*
@@ -117,7 +117,7 @@ IsCpbFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable core performance boost
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h
index fc73f8d..3a371af 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h
@@ -62,7 +62,7 @@ AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if CPB is supported.
*
@@ -85,7 +85,7 @@ typedef BOOLEAN F_CPB_IS_SUPPORTED (
/// Reference to a Method.
typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable CPB.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
index fffd4d6..a0feef7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
@@ -120,7 +120,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -147,7 +147,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -173,7 +173,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -388,7 +388,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -578,7 +578,7 @@ GetType4Type7Info (
}
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -613,7 +613,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -634,7 +634,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -657,7 +657,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c
index 3d65549..b22936e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -112,7 +112,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -188,7 +188,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -213,7 +213,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -238,7 +238,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h
index 59f63df..589f965 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h
@@ -179,7 +179,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -198,7 +198,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c
index 778b95e..31064e8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
extern CPU_FAMILY_SUPPORT_TABLE HtAssistFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should HT Assist be enabled
*
@@ -148,7 +148,7 @@ IsHtAssistEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the HT Assist feature.
*
@@ -285,7 +285,7 @@ InitializeHtAssistFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Disable all the caches on current core.
@@ -318,7 +318,7 @@ DisableAllCaches (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Enable all the caches on current core.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h
index 0efbec2..ec8281b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h
@@ -65,7 +65,7 @@ AGESA_FORWARD_DECLARATION (HT_ASSIST_FAMILY_SERVICES);
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -86,7 +86,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before HT Assist is initialized.
*
@@ -104,7 +104,7 @@ typedef VOID F_HT_ASSIST_BEFORE_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_BEFORE_INIT *PF_HT_ASSIST_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -120,7 +120,7 @@ typedef VOID F_HT_ASSIST_DISABLE_CACHE (
/// Reference to a Method.
typedef F_HT_ASSIST_DISABLE_CACHE *PF_HT_ASSIST_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -139,7 +139,7 @@ typedef VOID F_HT_ASSIST_ENABLE_CACHE (
typedef F_HT_ASSIST_ENABLE_CACHE *PF_HT_ASSIST_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize HT Assist
*
@@ -158,7 +158,7 @@ typedef VOID F_HT_ASSIST_INIT (
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize ATM mode
*
@@ -177,7 +177,7 @@ typedef VOID F_ATM_MODE_INIT (
typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook after HT Assist is initialized.
*
@@ -195,7 +195,7 @@ typedef VOID F_HT_ASSIST_AFTER_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_AFTER_INIT *PF_HT_ASSIST_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -215,7 +215,7 @@ typedef VOID F_HT_ASSIST_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_HT_ASSIST_GET_L3_SCRUB_CTRL *PF_HT_ASSIST_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -236,7 +236,7 @@ typedef VOID F_HT_ASSIST_SET_L3_SCRUB_CTRL (
typedef F_HT_ASSIST_SET_L3_SCRUB_CTRL *PF_HT_ASSIST_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to provide non_optimal HT Assist support
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c
index 0f56d60..73f66dd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -125,7 +125,7 @@ IsHwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h
index ee1e6b5..b97ada9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if hardware C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c
index 5e963d1..a4f230d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c
@@ -87,7 +87,7 @@ EnableIoCstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should IO Cstate be enabled
* If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
@@ -134,7 +134,7 @@ IsIoCstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate feature
*
@@ -170,7 +170,7 @@ InitializeIoCstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable IO Cstate on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h
index 5c683c2..c93244f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h
@@ -168,7 +168,7 @@ typedef struct _ACPI_CST_GET_INPUT {
} ACPI_CST_GET_INPUT ;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if IO Cstate is supported.
*
@@ -186,7 +186,7 @@ typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable IO Cstate.
*
@@ -205,7 +205,7 @@ typedef AGESA_STATUS F_IO_CSTATE_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to return the size of ACPI C-State Objects
*
@@ -222,7 +222,7 @@ typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to create ACPI C-State Objects
*
@@ -239,7 +239,7 @@ typedef VOID F_IO_CSTATE_CREATE_CST (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c
index 2e8a3c9..5100b3a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c
@@ -86,7 +86,7 @@ EnableLowPwrPstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Low Power P-state be enabled
* If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
@@ -130,7 +130,7 @@ IsLowPwrPstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable low power P-state
*
@@ -166,7 +166,7 @@ InitializeLowPwrPstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable low power P-state
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h
index eb84714..e928f3c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h
@@ -62,7 +62,7 @@ AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Low Power P-state is supported.
*
@@ -85,7 +85,7 @@ typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable Low Power P-state
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c
index ef1cf63..c4da762 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -88,7 +88,7 @@ EnableMsgC1eOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -136,7 +136,7 @@ IsMsgBasedC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Message-based C1e
*
@@ -174,7 +174,7 @@ InitializeMsgBasedC1eFeature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable message-based C1e on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h
index 14646a2..728df19 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -81,7 +81,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c
index a7269af..3f6dbed 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -955,7 +955,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
index e9f143a..af4ddea 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
@@ -100,7 +100,7 @@ typedef struct {
IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
} S_CPU_AMD_PSTATE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -122,7 +122,7 @@ typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c
index 3d23e8a..9a90ff5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c
@@ -134,7 +134,7 @@ ReleaseSlitBuffer (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -158,7 +158,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -183,7 +183,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -303,7 +303,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -331,7 +331,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -352,7 +352,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
index cb9bb0d..394ba14 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
@@ -138,7 +138,7 @@ STATIC
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -161,7 +161,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -184,7 +184,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -295,7 +295,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -470,7 +470,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -506,7 +506,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c
index 881043b..ebc3b1a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c
@@ -82,7 +82,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -129,7 +129,7 @@ IsSwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h
index 70273eb..45cbe27 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if software C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
/// Reference to a Method
typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable software C1e.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
index 6aa3212..a12e601 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
@@ -99,7 +99,7 @@ GetAcpiWheaMain (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -121,7 +121,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -147,7 +147,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -245,7 +245,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c
index 1492182..76a62b7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c
@@ -152,7 +152,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -185,7 +185,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -282,7 +282,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -370,7 +370,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -461,7 +461,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -504,7 +504,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -550,7 +550,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -634,7 +634,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -695,7 +695,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -755,7 +755,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -857,7 +857,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -961,7 +961,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -1014,7 +1014,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1070,7 +1070,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1091,7 +1091,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1115,7 +1115,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1140,7 +1140,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1164,7 +1164,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1188,7 +1188,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c
index dfad926..fcb71a3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c
@@ -92,7 +92,7 @@ SetRegistersFromTablesAtEarly (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -153,7 +153,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -184,7 +184,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -252,7 +252,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -283,7 +283,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -334,7 +334,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Family Specific Workaround Register Entry.
*
@@ -363,7 +363,7 @@ SetRegisterForFamSpecificWorkaroundEntry (
Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers using BKDG values.
*
@@ -418,7 +418,7 @@ SetRegisterForHtPhyEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program a range of HT Phy PCI registers using BKDG values.
*
@@ -483,7 +483,7 @@ SetRegisterForHtPhyRangeEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -504,7 +504,7 @@ IsDeemphasisLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, for the current node and real link number.
*
@@ -553,7 +553,7 @@ LookupPackageLink (
return PackageLink;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the platform's specified deemphasis levels for the current link.
*
@@ -609,7 +609,7 @@ GetLinkDeemphasis (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program Deemphasis registers using BKDG values, for the platform specified levels.
*
@@ -680,7 +680,7 @@ SetRegisterForDeemphasisEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers which have complex frequency dependencies.
*
@@ -788,7 +788,7 @@ SetRegisterForHtPhyFreqEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -826,7 +826,7 @@ SetRegisterForPerformanceProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Phy Performance Profile Register Entry.
*
@@ -862,7 +862,7 @@ SetRegisterForHtPhyProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host PCI Register Entry.
*
@@ -921,7 +921,7 @@ SetRegisterForHtHostEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host Performance PCI Register Entry.
*
@@ -963,7 +963,7 @@ SetRegisterForHtHostPerfEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the HT Link Token Count registers.
*
@@ -1042,7 +1042,7 @@ SetRegisterForHtLinkTokenEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -1083,7 +1083,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -1124,7 +1124,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts PCI Register Entry.
*
@@ -1165,7 +1165,7 @@ SetRegisterForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Token Counts PCI Register Entry.
*
@@ -1209,7 +1209,7 @@ SetRegisterForTokenPciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link Feature PCI Register Entry.
*
@@ -1282,7 +1282,7 @@ SetRegisterForHtFeaturePciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link PCI Register Entry.
*
@@ -1339,7 +1339,7 @@ SetRegisterForHtLinkPciEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -1433,7 +1433,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -1481,7 +1481,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -1525,7 +1525,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -1560,7 +1560,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -1643,7 +1643,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
index 2d33021..2dc9f81 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
@@ -122,11 +122,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -163,11 +163,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -606,11 +606,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -871,11 +871,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -924,11 +924,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -955,11 +955,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -1001,11 +1001,11 @@ typedef struct {
FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
index 8458c20..49b200d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
@@ -246,7 +246,7 @@ ExecuteFinalHltInstruction (
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -330,7 +330,7 @@ LocalApicInitialization (
LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -354,7 +354,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -498,7 +498,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -529,7 +529,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -554,7 +554,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -580,7 +580,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -601,7 +601,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -704,7 +704,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -758,7 +758,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -825,7 +825,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -870,7 +870,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -945,7 +945,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -1023,7 +1023,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1167,7 +1167,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1205,7 +1205,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1257,7 +1257,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1286,7 +1286,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1317,7 +1317,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1339,7 +1339,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1372,7 +1372,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1402,7 +1402,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1446,7 +1446,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c
index 248202f..bc0273e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c
@@ -74,7 +74,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -147,7 +147,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c
index 1d05c00..fb9a1fb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c
@@ -93,7 +93,7 @@ SetBrandIdRegistersAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
@@ -288,7 +288,7 @@ SetBrandIdRegisters (
HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c
index 152d9a8..07c4b4c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c
@@ -100,7 +100,7 @@ McaInitializationAtEarly (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
VOID
AmdCpuEarlyInitializer (
@@ -131,7 +131,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -291,7 +291,7 @@ AmdCpuEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -336,7 +336,7 @@ McaInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -358,7 +358,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
@@ -394,7 +394,7 @@ ApUtilRunCodeOnAllLocalCoresAtEarly (
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c
index dba8f6a..4b2da64 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c
@@ -97,7 +97,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -134,7 +134,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -171,7 +171,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -249,7 +249,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -303,7 +303,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -365,7 +365,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c
index 1c05941..ccc5cbf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c
@@ -127,7 +127,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -166,7 +166,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -189,7 +189,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -261,7 +261,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -288,7 +288,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -314,7 +314,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -337,7 +337,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -362,7 +362,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -389,7 +389,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -413,7 +413,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -456,7 +456,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
index 1fd2127..74c0b8d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
@@ -756,7 +756,7 @@ typedef enum {
} FAMILY_CACHE_INIT_POLICY;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c
index d844119..612541d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c
@@ -186,7 +186,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -230,7 +230,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -274,7 +274,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -316,7 +316,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -335,7 +335,7 @@ GetPlatformNumberOfSockets ()
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -353,7 +353,7 @@ GetPlatformNumberOfModules ()
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -397,7 +397,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -440,7 +440,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -485,7 +485,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -528,7 +528,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -550,7 +550,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
@@ -589,7 +589,7 @@ ModifyCurrentSocketPci (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -611,7 +611,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -690,7 +690,7 @@ GetNumberOfCompUnitsInCurrentModule (
return ComputeUnitCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -729,7 +729,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -776,7 +776,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -815,7 +815,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -838,7 +838,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -872,7 +872,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -912,7 +912,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -955,7 +955,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -989,7 +989,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -1018,7 +1018,7 @@ GetSystemDegree (
return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -1048,7 +1048,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1077,7 +1077,7 @@ IsBsp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the compute unit mapping algorithm.
*
@@ -1143,7 +1143,7 @@ GetComputeUnitMapping (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is current core the primary core of its compute unit?
*
@@ -1191,7 +1191,7 @@ IsCorePairPrimary (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Are the two specified cores shared in a compute unit?
*
@@ -1240,7 +1240,7 @@ AreCoresPaired (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c
index 95521db..892c03a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c
@@ -98,7 +98,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c
index d5efdd8..7b624c0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c
@@ -80,7 +80,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -102,7 +102,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -145,7 +145,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -176,7 +176,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -231,7 +231,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
index 06dbe2b..1a2e0ba 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
@@ -118,7 +118,7 @@ LoadMicrocodePatchAtEarly (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -177,7 +177,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -221,7 +221,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -281,7 +281,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -391,7 +391,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -420,7 +420,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c
index bc80203..1c6b6d1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c
@@ -113,7 +113,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -181,7 +181,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -208,7 +208,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -235,7 +235,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -353,7 +353,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -393,7 +393,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
@@ -414,7 +414,7 @@ FinalizeAtPost (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection.
*
@@ -440,7 +440,7 @@ SetTscFreqSel (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection to all cores.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c
index 42957e2..cd71c3a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c
@@ -101,7 +101,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -158,7 +158,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -197,7 +197,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -224,7 +224,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c
index 167f20e..b883f98 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -92,7 +92,7 @@ GetEarlyPmErrorsMulti (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -137,7 +137,7 @@ RunCodeOnAllSystemCore0sMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -177,7 +177,7 @@ GetNumberOfSystemPmStepsPtrMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the frequency that the northbridges must run.
*
@@ -276,7 +276,7 @@ GetSystemNbCofMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -325,7 +325,7 @@ GetSystemNbCofVidUpdateMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -411,7 +411,7 @@ GetEarlyPmErrorsMulti (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to return the next event log entry to the BSC.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
index 1e4a17c..5749069 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -83,7 +83,7 @@ GetEarlyPmErrorsSingle (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -106,7 +106,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -131,7 +131,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -180,7 +180,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -209,7 +209,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
index ae9e448..b42825a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
@@ -75,7 +75,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -101,7 +101,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -146,7 +146,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
@@ -196,7 +196,7 @@ IsWarmReset (
return WarmReset;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
index d4d3dec..f0e199e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
@@ -106,7 +106,7 @@ InsertFreeSpaceNode (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -236,7 +236,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -409,7 +409,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -534,7 +534,7 @@ HeapDeallocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -635,7 +635,7 @@ HeapLocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the heap base address
*
@@ -697,7 +697,7 @@ VOID
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DeleteFreeSpaceNode
@@ -756,7 +756,7 @@ DeleteFreeSpaceNode (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InsertFreeSpaceNode
@@ -809,7 +809,7 @@ InsertFreeSpaceNode (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c
index 6f183be..b456827 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c
@@ -107,7 +107,7 @@ AmdInitEarlyInitializer (
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -127,7 +127,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -155,7 +155,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -190,7 +190,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
index 0495ad4..5a54156 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
@@ -110,7 +110,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
index 1a19c7b..f48f5d3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
@@ -103,7 +103,7 @@ AmdInitLateDestructor (
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -197,7 +197,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
index 45409f8..1c1a596 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
@@ -106,7 +106,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
index 076dca9..620a1e1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
@@ -93,7 +93,7 @@ AmdPostPlatformConfigInit (
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -201,7 +201,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitRecovery.c
index c6c9fc5..06bc276 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitRecovery.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
@@ -127,7 +127,7 @@ AmdInitRecovery (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initialize defaults and options for Amd Init Reset.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
index deaa0e1..228c502 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
@@ -93,7 +93,7 @@ AmdInitResetConstructor (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -117,7 +117,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -225,7 +225,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c
index 563955b..554e250 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -162,7 +162,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -193,7 +193,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
index c14aee8..505d294 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G3_DXE)
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -125,7 +125,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c
index 8aa2006..530c562 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c
@@ -86,7 +86,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -158,7 +158,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -190,7 +190,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
index 52c0e9b..d80ff91 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
@@ -101,7 +101,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -278,7 +278,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -310,7 +310,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -356,7 +356,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
index b3254f1..088917d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
@@ -76,7 +76,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c
index 4e8beac..d5936b0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c
@@ -64,7 +64,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return TRUE.
*
@@ -77,7 +77,7 @@ CommonReturnTrue (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -89,7 +89,7 @@ CommonReturnFalse (VOID)
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -102,7 +102,7 @@ CommonReturnZero8 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -115,7 +115,7 @@ CommonReturnZero32 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -128,7 +128,7 @@ CommonReturnZero64 (VOID)
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -140,7 +140,7 @@ CommonReturnNULL (VOID)
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -153,7 +153,7 @@ CommonReturnAgesaSuccess (VOID)
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -163,7 +163,7 @@ CommonVoid (VOID)
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c
index 03f2bd5..7168835 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c
@@ -79,7 +79,7 @@ extern CONST UINTN InitializerCount;
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -224,7 +224,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
index 8625781..4d4099a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
@@ -84,7 +84,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -101,7 +101,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -118,7 +118,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -144,7 +144,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
index 6c3fa62..d676b7f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
@@ -80,7 +80,7 @@ S3SaveStateExtendTableLenth (
IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -96,7 +96,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -112,7 +112,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -140,7 +140,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -194,7 +194,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -222,7 +222,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -286,7 +286,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -360,7 +360,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -436,7 +436,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 info opcode
*
@@ -492,7 +492,7 @@ S3SaveStateSaveInfoOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 dispatch opcode
*
@@ -556,7 +556,7 @@ S3SaveStateSaveDispatchOp (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
@@ -601,7 +601,7 @@ S3SaveDebugOpcodeString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c
index 9127f94..93e32ed 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c
@@ -76,7 +76,7 @@ GnbCommonFeatureStub (
-/*----------------------------------------------------------------------------------------*/
+
/**
* DIspathc feature tanle
*
@@ -102,7 +102,7 @@ GnbLibDispatchFeatures (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Feature stub function
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
index f284639..1d164af 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
@@ -98,7 +98,7 @@ UINT8 DdiLaneConfigArray [][4] = {
{19, 16, 6, 6}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -191,7 +191,7 @@ GfxFmMapEngineToDisplayPath (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific integrated info table init
*
@@ -236,7 +236,7 @@ GfxFmIntegratedInfoTableInit (
IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific address swizzle settings.
*
@@ -263,7 +263,7 @@ GfxFmGmcAddressSwizzel (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Allow_Nb_Pstate High
*
@@ -306,7 +306,7 @@ GfxFmGmcAllowPstateHigh (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate COF for DFS out of Main PLL
*
@@ -328,7 +328,7 @@ GfxFmCalculateClock (
return GfxLibCalculateClk (Did, MainPllFreq10kHz);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set idle voltage mode for GFX
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c
index ceaf098..70e557b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c
@@ -77,7 +77,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable GMM Access
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
index 9275d45..0bbf659 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
@@ -184,7 +184,7 @@ extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr;
extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr;
extern UINT8 NumberOfChannels;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GMC memory address translation
*
@@ -220,7 +220,7 @@ GfxGmcSetMemoryAddressTranslation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable CLock Gating
*
@@ -242,7 +242,7 @@ GfxGmcDisableClockGating (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Register Engine
*
@@ -265,7 +265,7 @@ GfxGmcInitializeRegisterEngine (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get DCT channel info
*
@@ -318,7 +318,7 @@ GfxGmcDctMemoryChannelInfo (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Sequencer Model
*
@@ -422,7 +422,7 @@ GfxGmcInitializeSequencerModel (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Frame Buffer Location
*
@@ -499,7 +499,7 @@ GfxGmcInitializeFbLocation (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Secure Garlic Access
*
@@ -530,7 +530,7 @@ GfxGmcSecureGarlicAccess (
GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Performance setting
*
@@ -552,7 +552,7 @@ GfxGmcPerformanceTuning (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc. Initialization
*
@@ -574,7 +574,7 @@ GfxGmcMiscInit (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock critical registers
*
@@ -598,7 +598,7 @@ GfxGmcLockCriticalRegisters (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Remove blackout
*
@@ -620,7 +620,7 @@ GfxGmcRemoveBlackout (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable clock Gating
*
@@ -642,7 +642,7 @@ GfxGmcEnableClockGating (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UMA steering
*
@@ -666,7 +666,7 @@ GfxGmcUmaSteering (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize C6 aperture
*
@@ -708,7 +708,7 @@ GfxGmcInitializeC6Aperture (
);
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Power Gating
*
@@ -759,7 +759,7 @@ GfxGmcInitializePowerGating (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GMC
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c
index 17dc9e0..2ac2698 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c
@@ -74,7 +74,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Env Post.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c
index b8ab73d..36e0b08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c
@@ -77,7 +77,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Mid Post.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c
index 8e61f80..62af733 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c
@@ -76,7 +76,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Post.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
index fe54944..4e3e544 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
@@ -194,7 +194,7 @@ GfxIntegratedInfoTableInit (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get CSR phy self refresh power down mode.
*
@@ -221,7 +221,7 @@ GfxLibGetCsrPhySrPllPdMode (
return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get disable DLL shutdown in self-refresh mode.
*
@@ -248,7 +248,7 @@ GfxLibGetDisDllShutdownSR (
return D18F2x090.Field.DisDllShutdownSR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
* GMC FB access requred
@@ -279,7 +279,7 @@ GfxIntegratedInfoTableEntry (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
*
@@ -392,7 +392,7 @@ GfxIntegratedInfoTableInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Dispclk <-> VID table
*
@@ -421,7 +421,7 @@ GfxIntegratedInfoInitDispclkTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Sclk <-> VID table
*
@@ -513,7 +513,7 @@ GfxIntegratedInfoInitSclkTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init HTC Data
*
@@ -540,7 +540,7 @@ GfxFillHtcData (
IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init NbPstateVid
*
@@ -579,7 +579,7 @@ GfxFillNbPStateVid (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init M3 Arbitration Control values.
*
@@ -599,7 +599,7 @@ GfxFillM3ArbritrationControl (
LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init M3 Arbitration Control values.
*
@@ -631,7 +631,7 @@ GfxFillSbMmioBaseAddress (
IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fill in NCLK info
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c
index 2ad9965..ec7bce0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate main PLL VCO
*
@@ -106,7 +106,7 @@ GfxLibGetMainPllFreq (
return MainPllFreq;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate clock from main VCO
*
@@ -140,7 +140,7 @@ GfxLibCalculateClk (
return (((MainPllVco * 100) + (Divider - 1)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate did from main VCO
*
@@ -175,7 +175,7 @@ GfxLibCalculateDid (
return Did;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if GFX controller fused off
*
@@ -191,7 +191,7 @@ GfxLibIsControllerPresent (
return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max non 0 VID index
*
@@ -227,7 +227,7 @@ GfxLibMaxVidIndex (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get min SCLK
*
@@ -252,7 +252,7 @@ GfxLibGetMinSclk (
return MinSclkClk;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get min WRCK
*
@@ -285,7 +285,7 @@ GfxLibGetWrCk (
return 100 * 100 / WrCk;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate NCLK clock from main VCO
*
@@ -317,7 +317,7 @@ GfxLibCalculateNclk (
return ((MainPllVco * 100) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate idle NCLK clock from main VCO
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c
index 0c06bbb..fb8cbf6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM register
*
@@ -95,7 +95,7 @@ GmmRegisterWrite (
GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GMM register
*
@@ -117,7 +117,7 @@ GmmRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM register field
*
@@ -149,7 +149,7 @@ GmmRegisterWriteField (
GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GMM registers table
*
@@ -175,7 +175,7 @@ GmmRegisterTableWrite (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c
index 436b19b..50826c3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c
@@ -78,7 +78,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Gfx SSID Registers
*
@@ -124,7 +124,7 @@ GfxInitSsid (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GFX straps.
*
@@ -217,7 +217,7 @@ GfxStrapsInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable integrated GFX controller
*
@@ -265,7 +265,7 @@ GfxDisableController (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request GFX boot up voltage
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
index 0462c95..6543ab6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
@@ -72,7 +72,7 @@ extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[];
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c
index abbe63a..b2b8670 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c
@@ -69,7 +69,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -92,7 +92,7 @@ GnbInitDataStructAtEnvDef (
GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c
index 3dd1497..ec7cd28 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c
@@ -70,7 +70,7 @@ extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[];
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c
index 93ae1ed..29e33e6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c
@@ -70,7 +70,7 @@ extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[];
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c
index bb9a162..5c217c8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c
@@ -71,7 +71,7 @@ extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[];
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -92,7 +92,7 @@ GnbInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c
index f3d278d..5140a8d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c
@@ -66,7 +66,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
index 7838233..2c701db 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
@@ -98,7 +98,7 @@ GnbCableSafeIsSupported (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Cable Safe module entry
*
@@ -163,7 +163,7 @@ GnbCableSafeEntry (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port Gen capability
*
@@ -190,7 +190,7 @@ GnbCableSafeGetConnectorInfoArrayCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if feature supported
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index f0e3727..fb1cc05 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -82,7 +82,7 @@ GnbLibPciIndirectReadField (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers
*
@@ -108,7 +108,7 @@ GnbLibPciIndirectRead (
GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers field
*
@@ -137,7 +137,7 @@ GnbLibPciIndirectReadField (
*Value = (*Value >> FieldOffset) & Mask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers
*
@@ -165,7 +165,7 @@ GnbLibPciIndirectWrite (
GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers field
*
@@ -199,7 +199,7 @@ GnbLibPciIndirectWriteField (
GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write GNB indirect registers field
*
@@ -235,7 +235,7 @@ GnbLibPciIndirectRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI registers
*
@@ -262,7 +262,7 @@ GnbLibPciRMW (
GnbLibPciWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write I/O registers
*
@@ -289,7 +289,7 @@ GnbLibIoRMW (
GnbLibIoWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write MMIO registers
*
@@ -315,7 +315,7 @@ GnbLibMemRMW (
Data = (Data & Mask) | Value;
GnbLibMemWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of sockets
*
@@ -333,7 +333,7 @@ GnbGetNumberOfSockets (
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of Silicons on the socket
*
@@ -353,7 +353,7 @@ GnbGetNumberOfSiliconsOnSocket (
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCI Address
*
@@ -377,7 +377,7 @@ GnbGetPciAddress (
return Gnb;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if anything plugged in socket
*
@@ -398,7 +398,7 @@ GnbIsDevicePresentInSocket (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Claculate power of number
*
@@ -425,7 +425,7 @@ GnbLibPowerOf (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search buffer for pattern
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index 0b5a642..e2ed523 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -69,7 +69,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU (DCT) indirect registers
*
@@ -97,7 +97,7 @@ GnbLibCpuPciIndirectRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write CPU (DCT) indirect registers
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index 65c67b6..c97c621 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -65,7 +65,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -98,7 +98,7 @@ GnbAllocateHeapBuffer (
return AllocHeapParams.BufferPtr;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index b56af42..cb8e5ca 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -68,10 +68,10 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*---------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
+
/**
* Write I/O Port
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 1b6b3f0..1c8ed9b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write Memory/MMIO registers
*
@@ -95,7 +95,7 @@ GnbLibMemWrite (
LibAmdMemWrite (Width, Address, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Memory/MMIO registers
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
index 6f72172..288f8b2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -55,7 +55,7 @@
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device present
*
@@ -83,7 +83,7 @@ GnbLibPciIsDevicePresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is bridge
*
@@ -110,7 +110,7 @@ GnbLibPciIsBridgeDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is multifunction
*
@@ -137,7 +137,7 @@ GnbLibPciIsMultiFunctionDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is PCIe device
*
@@ -164,7 +164,7 @@ GnbLibPciIsPcieDevice (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCI capability pointer
*
@@ -202,7 +202,7 @@ GnbLibFindPciCapability (
}
return CapabilityPtr;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCIe extended capability pointer
*
@@ -240,7 +240,7 @@ GnbLibFindPcieExtendedCapability (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Scan range of device on PCI bus.
*
@@ -251,7 +251,7 @@ GnbLibFindPcieExtendedCapability (
* @param[in] ScanData Supporting data
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
@@ -308,7 +308,7 @@ GnbLibPciScan (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan all subordinate buses
*
@@ -334,7 +334,7 @@ GnbLibPciScanSecondaryBus (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe device type
*
@@ -345,7 +345,7 @@ GnbLibPciScanSecondaryBus (
*
* @retval PCIE_DEVICE_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_DEVICE_TYPE
GnbLibGetPcieDeviceType (
@@ -364,7 +364,7 @@ GnbLibGetPcieDeviceType (
return PcieNotPcieDevice;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save config space area
*
@@ -377,7 +377,7 @@ GnbLibGetPcieDeviceType (
* @param[in] StdHeader Standard header.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibS3SaveConfigSpace (
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
index e9d1efe..1d5f3f9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI registers
*
@@ -96,7 +96,7 @@ GnbLibPciWrite (
LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI registers
*
@@ -123,7 +123,7 @@ GnbLibPciRead (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll PCI reg
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
index 3621966..14accb6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -83,7 +83,7 @@ GfxConfigEnvInterface (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get UMA info
*
@@ -113,7 +113,7 @@ GfxGetUmaInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate UMA configuration data
*
@@ -142,7 +142,7 @@ GfxLocateConfigData (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 00a6502..d4b1a61 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -80,7 +80,7 @@ GfxConfigPostInterface (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate UMA configuration data
*
@@ -136,7 +136,7 @@ GfxConfigPostInterface (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
index d6f5805..e008309 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -86,7 +86,7 @@ GfxScanPcieDevice (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get information about all discrete GFX card in system
*
@@ -117,7 +117,7 @@ GfxGetDiscreteCardInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index 8b2ad95..2767fb8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -220,7 +220,7 @@ UINT8 ConnectorNumerArray[] = {
// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS)
6, 1, 6, 6, 6, 1, 1, 2
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -294,7 +294,7 @@ EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
0x260,
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -328,7 +328,7 @@ GfxIntegratedExtDisplayDeviceInfo (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors
*
@@ -376,7 +376,7 @@ GfxIntegratedEnumerateAllConnectors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -414,7 +414,7 @@ GfxIntegratedDdiInterfaceCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -494,7 +494,7 @@ GfxIntegratedEnumConnectorsForDevice (
return ConnectorEnumInfo.Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -548,7 +548,7 @@ GfxIntegratedCopyDisplayInfo (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump display path settings
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index b1dad22..1ede58c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -170,7 +170,7 @@ GfxIntegratedDebugDumpPpTable (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing tdp
*
@@ -209,7 +209,7 @@ GfxPowerPlayLocateTdp (
return PpFuses->SclkDpmTdpLimit[DpmIndex];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new software state
*
@@ -233,7 +233,7 @@ GfxPowerPlayCreateSwState (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new DPM state
*
@@ -266,7 +266,7 @@ GfxPowerPlayCreateDpmState (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing or Create new DPM state
*
@@ -295,7 +295,7 @@ GfxPowerPlayAddDpmState (
return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add reference to DPM state for SW state
*
@@ -313,7 +313,7 @@ GfxPowerPlayAddDpmStateToSwState (
SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy SW state info to PPTable
*
@@ -351,7 +351,7 @@ GfxPowerPlayCopyStateInfo (
StateArray->ucNumEntries = SwStateIndex;
return (UINT32) ((UINT8*) States - (UINT8*) StateArray);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy clock info to PPTable
*
@@ -384,7 +384,7 @@ GfxPowerPlayCopyClockInfo (
return sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * (ClkStateIndex) - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy non clock info to PPTable
*
@@ -418,7 +418,7 @@ GfxPowerPlayCopyNonClockInfo (
return sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if fused state valid
*
@@ -446,7 +446,7 @@ GfxPowerPlayIsFusedStateValid (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SW state calssification from fuses
*
@@ -497,7 +497,7 @@ GfxPowerPlayGetClassificationFromFuses (
return Classification;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build PP table
*
@@ -615,7 +615,7 @@ GfxPowerPlayBuildTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump PP table
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index 506228e..da220fb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -71,7 +71,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB set top of memory
*
@@ -137,7 +137,7 @@ GnbSetTom (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Avoid LPC DMA transaction deadlock
*
@@ -174,7 +174,7 @@ GnbLpcDmaDeadlockPrevention (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Dynamic Wake
* ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
@@ -217,7 +217,7 @@ GnbOrbDynamicWake (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock NB registers
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
index 83b8cb9..886401e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -115,7 +115,7 @@ PcieAlibBuildAcpiTable (
OUT VOID **AlibSsdtPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create ACPI ALIB SSDT table
*
@@ -135,7 +135,7 @@ PcieAlibFeature (
return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
@@ -317,7 +317,7 @@ PcieAlibBuildAcpiTable (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -345,7 +345,7 @@ PcieAlibSetPortMaxSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -376,7 +376,7 @@ PcieAlibSetPortOverrideSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init port info
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index fc381b3..e77cb2f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -88,7 +88,7 @@ PcieConfigDebugDump (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration data
*
@@ -185,7 +185,7 @@ PcieConfigurationInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -223,7 +223,7 @@ PcieLocateConfigurationData (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Rebase all pointers in Complex Configuration Data
*
@@ -261,7 +261,7 @@ PcieRebaseConfigurationData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump configuration to debug out
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 81a7fa5..9674c1c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of core lanes
*
@@ -93,7 +93,7 @@ PcieConfigGetNumberOfCoreLane (
return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable engine
*
@@ -113,7 +113,7 @@ PcieConfigDisableEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable all engines on wrapper
*
@@ -139,7 +139,7 @@ PcieConfigDisableAllEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get engine PHY lanes bitmap
*
@@ -161,7 +161,7 @@ PcieConfigGetEnginePhyLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of phy lanes
*
@@ -185,7 +185,7 @@ PcieConfigGetNumberOfPhyLane (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get port configuration signature for given wrapper and core
*
@@ -214,7 +214,7 @@ PcieConfigGetConfigurationSignature (
return ConfigurationSignature;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check Port Status
*
@@ -233,7 +233,7 @@ PcieConfigCheckPortStatus (
return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set/Reset port status
*
@@ -257,7 +257,7 @@ PcieConfigUpdatePortStatus (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all engine in topology
*
@@ -304,7 +304,7 @@ PcieConfigRunProcForAllWrappers (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all engine in topology
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 1cc6868..6779861 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -79,7 +79,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of complexes in platform topology configuration
*
@@ -103,7 +103,7 @@ PcieInputParserGetNumberOfComplexes (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of PCIe engines in given complex
*
@@ -128,7 +128,7 @@ PcieInputParserGetLengthOfPcieEnginesList (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of DDI engines in given complex
*
@@ -154,7 +154,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of engines in given complex
*
@@ -176,7 +176,7 @@ PcieInputParserGetNumberOfEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -196,7 +196,7 @@ PcieInputParserGetComplexDescriptor (
return &ComplexList[Index];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Engine descriptor from given complex by index
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index f987271..82777cb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -136,7 +136,7 @@ PcieAllocateEngine (
IN UINT8 DescriptorIndex,
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -189,7 +189,7 @@ PcieMapTopologyOnComplex (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -267,7 +267,7 @@ PcieEnginesToWrapper (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
*
@@ -300,7 +300,7 @@ PcieCheckDescriptorMapsToWrapper (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Engine to be allocated.
*
@@ -318,7 +318,7 @@ PcieAllocateEngine (
Engine->Scratch = DescriptorIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -437,7 +437,7 @@ PcieMapTopologyOnWrapper (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize engine data
*
@@ -475,7 +475,7 @@ PcieMapInitializeEngineData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -506,7 +506,7 @@ PcieCheckPortPciDeviceMapping (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -568,7 +568,7 @@ PcieMapPortsPciAddresses (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* If link width from user descriptor less or equal to link width of engine
*
@@ -614,7 +614,7 @@ PcieCheckLanesMatch (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
*
@@ -662,7 +662,7 @@ PcieIsDescriptorLinkWidthValid (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to debug out
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
index 149dd6e..67e8bd4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
@@ -112,7 +112,7 @@ PcieAspmGetPmCapability (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable PCIE Advance state power management
*
@@ -138,7 +138,7 @@ PcieLinkAspmEnable (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -203,7 +203,7 @@ PcieAspmCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on PCIe device function
*
@@ -214,7 +214,7 @@ PcieAspmCallback (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnFunction (
IN PCI_ADDR Function,
@@ -235,7 +235,7 @@ PcieAspmEnableOnFunction (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on all function of PCI device
*
@@ -246,7 +246,7 @@ PcieAspmEnableOnFunction (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnDevice (
IN PCI_ADDR Device,
@@ -265,7 +265,7 @@ PcieAspmEnableOnDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on link
*
@@ -323,7 +323,7 @@ PcieAspmEnableOnLink (
-/**----------------------------------------------------------------------------------------*/
+
/**
* Port/Endpoint ASMP capability
*
@@ -334,7 +334,7 @@ PcieAspmEnableOnLink (
*
* @retval PCIE_ASPM_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_ASPM_TYPE
PcieAspmGetPmCapability (
IN PCI_ADDR Device,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
index bdba144..e7a74b4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -95,7 +95,7 @@ UINT16 AspmBrDeviceTable[] = {
0x1B4B, 0x9123, (UINT16) ~(AspmL0s)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie ASPM Black List
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index a8ff698..4584a7d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -82,7 +82,7 @@ PcieAspmGetMaxExitLatencyCallback (
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine ASPM L-state maximum exit latency for PCIe segment
*
@@ -109,7 +109,7 @@ PcieAspmGetMaxExitLatency (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
index c02f4a4..a01e280 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
@@ -80,7 +80,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane ganging
*
@@ -150,7 +150,7 @@ PciePhyApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Point "virtual" PLL clock picker away from PCIe
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
index 9e9dca4..97251f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -86,7 +86,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply PIF ganging for all lanes for given wrapper
*
@@ -179,7 +179,7 @@ PciePifApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -225,7 +225,7 @@ PciePifPllPowerDown (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL init for DDI
*
@@ -269,7 +269,7 @@ PciePifPllInitForDdi (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for on PIF to indicate action completion
*
@@ -302,7 +302,7 @@ PciePollPifForCompeletion (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable fifo reset
*
@@ -333,7 +333,7 @@ PciePifDisableFifoReset (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program LS2 exit time
*
@@ -365,7 +365,7 @@ PciePifSetLs2ExitTime (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -407,7 +407,7 @@ PciePifSetPllModeForL1 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
@@ -440,7 +440,7 @@ PciePifSetRxDetectPowerMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll ramp up time
*
@@ -511,7 +511,7 @@ PciePifSetPllRampTime (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 236ba93..bac1640 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -73,7 +73,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe port indirect register.
*
@@ -98,7 +98,7 @@ PciePortRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register.
*
@@ -132,7 +132,7 @@ PciePortRegisterWrite (
GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -167,7 +167,7 @@ PciePortRegisterWriteField (
PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -196,7 +196,7 @@ PciePortRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe port register.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
index 7017a34..36e0deb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set completion timeout
*
@@ -109,7 +109,7 @@ PcieCompletionTimeout (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init hotplug port
*
@@ -187,7 +187,7 @@ PcieLinkInitHotplug (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set misc slot capability
*
@@ -220,7 +220,7 @@ PcieLinkSetSlotCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Safe mode to force link advertize Gen1 only capability in TS
*
@@ -249,7 +249,7 @@ PcieLinkSafeMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -274,7 +274,7 @@ PcieSetLinkWidthCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -362,7 +362,7 @@ PcieSetLinkSpeedCap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Force compliance
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index 3c995c1..b212448 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes and plls
*
@@ -110,7 +110,7 @@ PciePwrPowerDownUnusedLanes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lane bitmam to enable PLL power down in L1
*
@@ -177,7 +177,7 @@ PcieLanesToPowerDownPllInL1 (
return LaneBitmapForPllOffInL1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Auto-Power Down electrical Idle detector
*
@@ -228,7 +228,7 @@ PciePwrAutoPowerDownElectricalIdleDetector (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clock gating
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
index d7c5489..60137d0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable/Disable ASPM on GNB-SB link
*
@@ -103,7 +103,7 @@ PcieSbLinkAspmControl (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SB ASPM.
* Enable ASPM states on SB
@@ -112,7 +112,7 @@ PcieSbLinkAspmControl (
* @param[in] Aspm ASPM bitmap.
* @param[in] StdHeader Standard configuration header
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieSbInitAspm (
@@ -136,13 +136,13 @@ PcieSbInitAspm (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Alink config address
*
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieSbAgetAlinkIoAddress (
@@ -166,7 +166,7 @@ PcieSbAgetAlinkIoAddress (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on PCIe device function
*
@@ -177,7 +177,7 @@ PcieSbAgetAlinkIoAddress (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieNbAspmEnable (
@@ -199,7 +199,7 @@ PcieNbAspmEnable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable VC on GNB-SB link
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 0860b60..e896150 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Gen1 voltage Index
*
@@ -104,7 +104,7 @@ PcieSiliconGetGen1VoltageIndex (
return Gen1VidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request Pcie voltage change
*
@@ -162,7 +162,7 @@ PcieSiliconRequestVoltage (
} while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Unhide all ports
*
@@ -196,7 +196,7 @@ PcieSiliconUnHidePorts (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide unused ports
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
index 19e453b..1e546d1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe timer timestamp
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index 4f3c52f..dc062c3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -80,7 +80,7 @@ PcieTopologyLocateMuxIndex (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for reconfiguration
*
@@ -131,7 +131,7 @@ PcieTopologyPrepareForReconfig (
UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate mux array index
*
@@ -156,7 +156,7 @@ PcieTopologyLocateMuxIndex (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply lane mux
*
@@ -248,7 +248,7 @@ PcieTopologyApplyLaneMux (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Select master PLL
*
@@ -329,7 +329,7 @@ PcieTopologySelectMasterPll (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -400,7 +400,7 @@ PcieTopologyExecuteReconfig (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
@@ -439,7 +439,7 @@ PcieTopologySetLinkReversal (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reduce link width
*
@@ -473,7 +473,7 @@ PcieTopologyReduceLinkWidth (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lanes enable/disable control
*
@@ -512,7 +512,7 @@ PcieTopologyLaneControl (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SRBM reset
*
@@ -549,7 +549,7 @@ PcieTopologyInitSrbmReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set core configuration according to PCIe port topology
*
@@ -604,7 +604,7 @@ PcieTopologySetCoreConfig (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Relinquish control to DDI for specific lanes
*
@@ -627,7 +627,7 @@ PcieSetDdiOwnPhy (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for PCIe lanes
*
@@ -669,7 +669,7 @@ PcieWrapSetTxS1CtrlForLaneMux (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for lane muxes
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 131d336..5ac3199 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -76,7 +76,7 @@ typedef struct {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link state history from HW state machine
*
@@ -115,7 +115,7 @@ PcieUtilGetLinkHwStateHistory (
LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search array for specific pattern
*
@@ -155,7 +155,7 @@ PcieUtilSearchArray (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link reversed
*
@@ -188,7 +188,7 @@ PcieUtilIsLinkReversed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link width detected during training
*
@@ -236,7 +236,7 @@ PcieUtilGetLinkWidth (
return LinkWidth;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of engine lane of requested type
*
@@ -316,7 +316,7 @@ PcieUtilGetEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of Wrapper lane of requested type
*
@@ -356,7 +356,7 @@ PcieUtilGetWrapperLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program port register table
*
@@ -400,7 +400,7 @@ PciePortProgramRegisterTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock registers
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
index 04d397d..62bbf18 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -53,7 +53,7 @@
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -74,7 +74,7 @@ PcieRegisterRead (
return PcieSiliconRegisterRead (PcieWrapperGetParentSilicon (Wrapper), Address, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -99,7 +99,7 @@ PcieSiliconRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -129,7 +129,7 @@ PcieRegisterWrite (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -161,7 +161,7 @@ PcieSiliconRegisterWrite (
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register field.
*
@@ -190,7 +190,7 @@ PcieRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register field.
*
@@ -226,7 +226,7 @@ PcieRegisterWriteField (
PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
@@ -260,7 +260,7 @@ PcieRegisterRMW (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
index b4352b8..d014532 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -115,7 +115,7 @@ GNB_DEBUG_CODE (
);
)
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set link State
*
@@ -147,7 +147,7 @@ PcieTrainingSetPortState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set state for all engines connected to same reset ID
*
@@ -173,7 +173,7 @@ PcieSetResetStateOnEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Assert GPIO port reset.
*
@@ -204,7 +204,7 @@ PcieTrainingAssertReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for reset duration
*
@@ -227,7 +227,7 @@ PcieTrainingCheckResetDuration (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Deassert GPIO port reset.
*
@@ -251,7 +251,7 @@ PcieTrainingDeassertReset (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for after reset deassertion timeout
*
@@ -275,7 +275,7 @@ PcieTrainingCheckResetTimeout (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Release training
*
@@ -309,7 +309,7 @@ PcieTrainingRelease (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect presence of any EP on the link
*
@@ -342,7 +342,7 @@ PcieTrainingDetectPresence (
UINT8 FailPattern1 [] = {0x2a, 0x6};
UINT8 FailPattern2 [] = {0x2a, 0x9};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect Link State
*
@@ -382,7 +382,7 @@ PcieTrainingDetectLinkState (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Broken Lane
*
@@ -420,7 +420,7 @@ PcieTrainingBrokenLine (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen2
*
@@ -456,7 +456,7 @@ PcieTrainingGen2Fail (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Link in L0
*
@@ -474,7 +474,7 @@ PcieCheckLinkL0 (
{
PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen X
*
@@ -510,7 +510,7 @@ PcieTrainingCheckVcoNegotiation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if for GFX workaround condition
*
@@ -553,7 +553,7 @@ PcieTrainingGfxWorkaround (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrain link
*
@@ -581,7 +581,7 @@ PcieTrainingRetrainLink (
PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training fail on this port
*
@@ -601,7 +601,7 @@ PcieTrainingFail (
PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links training success
*
@@ -622,7 +622,7 @@ PcieTrainingSuccess (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links in compliance
*
@@ -642,7 +642,7 @@ PcieTrainingCompliance (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCie EP not present
*
@@ -673,7 +673,7 @@ PcieTrainingNotPresent (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Final state. Port training completed.
*
@@ -692,7 +692,7 @@ PcieTrainingCompleted (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -781,7 +781,7 @@ PcieTrainingPortCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main link training procedure
*
@@ -815,7 +815,7 @@ PcieTraining (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump port state on state transition
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index 94b73e3..c4f5e05 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -113,7 +113,7 @@ PcieIsDeskewCardDetected (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* ATI RV370/RV380 card workaround
*
@@ -164,7 +164,7 @@ PcieGfxCardWorkaround (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RV370/RV380 Deskew workaround
*
@@ -207,7 +207,7 @@ PcieDeskewWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NV43 card workaround (lost SSID)
*
@@ -242,7 +242,7 @@ PcieNvWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate temporary resources for Pcie P2P bridge
*
@@ -275,7 +275,7 @@ PcieConfigureBridgeResources (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Free temporary resources for Pcie P2P bridge
*
@@ -301,7 +301,7 @@ PcieFreeBridgeResources (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Save CPU MMIO register
*
@@ -327,7 +327,7 @@ PcieProgramCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Restore CPU MMIO register
*
@@ -348,7 +348,7 @@ PcieRestoreCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if card required test for deskew workaround
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
index 2abc91f..3e0e93f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
@@ -95,7 +95,7 @@ UINT32 LclkDpmActivityThresholdTable [] = {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB LCLK DPM in Root Complex Activity mode
*
@@ -287,7 +287,7 @@ NbFmInitLclkDpmRcActivity (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific check PsppPolicy to initially enable appropriate DPM states
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
index e157bad..afc8b18 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
@@ -72,7 +72,7 @@ typedef struct {
} NLCK_SCLK;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power gate unused blocks
*
@@ -104,7 +104,7 @@ F14NbLclkNclkAllocatePair (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power gate unused blocks
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
index e560308..974a95f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
@@ -115,7 +115,7 @@ UINT32 F14GmcPowerGatingTable_1[] = {
(0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* GMC Power Gating
*
@@ -192,7 +192,7 @@ UINT32 F14UvdPowerGatingTable_1[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* UVD Power Gating
*
@@ -247,7 +247,7 @@ F14NbSmuUvdPowerGatingInit (
-/*----------------------------------------------------------------------------------------*/
+
/**
* UVD Power Shutdown
*
@@ -317,7 +317,7 @@ UINT32 F14SmuGmcShutdownTable_2[] = {
0x00
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shutdown GMC
*
@@ -521,7 +521,7 @@ UINT32 F14SmuGfxShutdownTable_2[] = {
0x00
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shutdown GFX
*
@@ -560,7 +560,7 @@ F14NbSmuGfxShutdown (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power gate unused blocks
*
@@ -609,7 +609,7 @@ F14NbPowerGateFeature (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GMC restore latency
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
index e3be806..31b5f33 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
@@ -84,7 +84,7 @@ FUSE_TABLE FuseTable;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB family specific clock gating
*
@@ -108,7 +108,7 @@ NbFmNbClockGating (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -127,7 +127,7 @@ NbFmClumpUnitID (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Fuse translation table
*
@@ -143,7 +143,7 @@ NbFmGetFuseTranslationTable (
return &FuseTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific fuse table patch
* Is's correct behavior if we would have 4 states, it would be
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
index fea7ca3..4a2a4df 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
@@ -71,7 +71,7 @@ F14NbSmuInitFeature (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Initialize
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
index b8dc155..04be6e0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
@@ -122,7 +122,7 @@ PP_FUSE_ARRAY DefaultPpFuseArray = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fuse Table Init
*
@@ -187,7 +187,7 @@ NbFuseTableFeature (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Fuse Table From FCRs
*
@@ -233,7 +233,7 @@ NbFuseLoadFuseTableFromFcr (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Default Fuse Table
*
@@ -273,7 +273,7 @@ NbFuseLoadDefaultFuseTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Adjust DIDs to current main PLL VCO
*
@@ -330,7 +330,7 @@ NbFuseAdjustFuseTableToCurrentMainPllVco (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump fuse table
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c
index a656cac..743d53c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c
@@ -81,7 +81,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* LCLK DPM init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c
index a8f1cf0..8303e3b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create configuration data
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
index 9de0c56..cfeab9c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
@@ -138,7 +138,7 @@ CONST NB_REGISTER_ENTRY NbOrbInitTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at Power On
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
index b611d07..4f05a02 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
@@ -75,7 +75,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c
index 54da3d5..ab2c353 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at ENV
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c
index 4fc8ed1..c950285 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late Post
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
index 29cb3fa..cc832b4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
@@ -74,7 +74,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at POST
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c
index 446c494..206b69e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c
@@ -72,7 +72,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c
index b7dff93..2d848fa 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c
@@ -87,7 +87,7 @@ NbInitClockGating (
IN GNB_PLATFORM_CONFIG *Gnb
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init various power management features
*
@@ -111,7 +111,7 @@ NbInitPowerManagement (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB LCLK Deep Sleep
*
@@ -528,7 +528,7 @@ NbInitDceDisplayClockGating (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB clock gating
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c
index 780d471..58f71d9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c
@@ -79,7 +79,7 @@ typedef struct {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register read
*
@@ -151,7 +151,7 @@ NbSmuIndirectRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register read
*
@@ -187,7 +187,7 @@ NbSmuIndirectPoll (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register write
*
@@ -251,7 +251,7 @@ NbSmuIndirectWriteEx (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU indirect register write
*
@@ -284,7 +284,7 @@ NbSmuIndirectWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request for S3 script
*
@@ -306,7 +306,7 @@ NbSmuIndirectWriteS3Script (
NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU RAM mapped register write
*
@@ -349,7 +349,7 @@ NbSmuRcuRegisterWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU RAM mapped register read
*
@@ -376,7 +376,7 @@ NbSmuRcuRegisterRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request Ext
*
@@ -408,7 +408,7 @@ NbSmuServiceRequestEx (
NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request
*
@@ -437,7 +437,7 @@ NbSmuServiceRequest (
IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Service request for S3 script
*
@@ -457,7 +457,7 @@ NbSmuServiceRequestS3Script (
NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Read FCR register
*
@@ -479,7 +479,7 @@ NbSmuReadEfuse (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU Read arbitrary fuse field
*
@@ -516,7 +516,7 @@ NbSmuReadEfuseField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU SRBM (GMM) register read
*
@@ -548,7 +548,7 @@ NbSmuSrbmRegisterRead (
NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU SRBM (GMM) register write
*
@@ -584,7 +584,7 @@ NbSmuSrbmRegisterWrite (
NbSmuServiceRequest (0x0B, S3Save, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware download
*
@@ -619,7 +619,7 @@ NbSmuFirmwareDownload (
NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware revision
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
index 9a6afda..c4dc26d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
@@ -79,7 +79,7 @@ PcieFmAlibBuildAcpiTable (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
index b120d5c..b0217a9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
@@ -74,7 +74,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -96,7 +96,7 @@ PcieFmGetComplexDataLength (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
index 0983a8d..fe2315f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
@@ -76,7 +76,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visability
*
@@ -105,7 +105,7 @@ PcieFmPortVisabilityControl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request boot up voltage
*
@@ -160,7 +160,7 @@ PcieFmSetBootUpVoltage (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -209,7 +209,7 @@ PcieFmMapPortPciAddress (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
index 8c44679..8b6cc85 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
@@ -100,7 +100,7 @@ PcieFmPifSetRxDetectPowerMode (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY Pll Personality Init
*
@@ -120,7 +120,7 @@ PcieFmPhyLetPllPersonalityInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Port channel characteristic
*
@@ -137,7 +137,7 @@ PcieFmPhyChannelCharacteristic (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Point "virtual" PLL clock picker away from PCIe
*
@@ -155,7 +155,7 @@ PcieFmAvertClockPickers (
// Stub function
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane ganging
*
@@ -173,7 +173,7 @@ PcieFmPhyApplyGanging (
// Stub function
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
index 9ff56ac..4ad4f6c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
@@ -73,7 +73,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -99,7 +99,7 @@ PcieFmPifSetPllModeForL1 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL power up latency
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
index 3169a66..83e2dc9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
@@ -168,7 +168,7 @@ PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = {
},
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -230,7 +230,7 @@ CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = {
{1, 2, 3, 4, 0}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -275,7 +275,7 @@ CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
{0, 3, 4, 7, 8, 11}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure DDI engine list to support lane allocation according to configuration ID.
*
@@ -313,7 +313,7 @@ PcieOnConfigureDdiEnginesLaneAllocation (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure clock to run out of the wrapper at specific speed
*
@@ -332,7 +332,7 @@ PcieFmConfigureClock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get configuration Value for GPP wrapper
*
@@ -375,7 +375,7 @@ PcieOnGetGppConfigurationValue (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -406,7 +406,7 @@ PcieFmGetCoreConfigurationValue (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -445,7 +445,7 @@ PcieFmGetLinkSpeedCap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Various initialization needed prior topology and configuration initialization
*
@@ -496,7 +496,7 @@ PcieFmPreInit (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -518,7 +518,7 @@ PcieFmCheckPortPciDeviceMapping (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -550,7 +550,7 @@ PcieFmDebugGetCoreConfigurationString (
return (CONST CHAR8*)" !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -576,7 +576,7 @@ PcieFmDebugGetWrapperNameString (
return (CONST CHAR8*)" !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -606,7 +606,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration for Gen 1 native mode
*
@@ -624,7 +624,7 @@ PcieFmExecuteNativeGen1Reconfig (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c
index 89ac18f..6fb57a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c
@@ -90,7 +90,7 @@ UINT32 PciePowerGatingTable_1[] = {
(0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Power Gating
*
@@ -137,7 +137,7 @@ PcieSmuPowerGatingInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -196,7 +196,7 @@ PcieSmuPowerGateLanes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll access required
*
@@ -221,7 +221,7 @@ PciePowerGatePllControl (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Report used lanes to SMU.
*
@@ -248,7 +248,7 @@ PciePowerGateReportUsedLanesCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -288,7 +288,7 @@ PciePowerGatePhyLaneCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe PowerGate PHY lanes
*
@@ -330,7 +330,7 @@ PciePowerGatePhyLane (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power PCIe block
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
index 4e32723..7be0593 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
@@ -104,7 +104,7 @@ PciePostInitCallback (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visibility in PCI config space
*
@@ -176,7 +176,7 @@ PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Common Core Init
*
@@ -218,7 +218,7 @@ PcieCommonCoreInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
*
@@ -237,7 +237,7 @@ PcieInitSrbmCallback (
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -281,7 +281,7 @@ PcieInitCallback (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -312,7 +312,7 @@ PcieInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -339,7 +339,7 @@ PciePostInitCallback (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
index df207af..9dd7c46 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c
index c09e74b..845dd72 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c
@@ -71,7 +71,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Env Init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c
index 58b7850..96a1c00 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c
index e7f858f..e32d664 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c
@@ -93,7 +93,7 @@ PcieLateRestoreS3Script (
IN VOID* Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init prior DRAM init
*
@@ -131,7 +131,7 @@ PcieInitAtPostEarly (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -174,7 +174,7 @@ PcieInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -220,7 +220,7 @@ PcieInitAtPostS3 (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe S3 restore
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c
index 9944c19..c67f9a1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c
@@ -88,7 +88,7 @@ PcieLateInitCallback (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down inactive lanes
*
@@ -116,7 +116,7 @@ PciePwrPowerDownPllInL1 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Late Init.
*
@@ -139,7 +139,7 @@ PcieLateInitCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Late Init
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
index cd31d66..518b43a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
@@ -78,7 +78,7 @@ typedef struct {
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -122,7 +122,7 @@ PcieUtilGlobalGenCapabilityCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine global GEN capability
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c
index 4ddc0d0..cbc6316 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c
@@ -118,7 +118,7 @@ PCIE_PORT_REGISTER_ENTRY PortInitTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -160,7 +160,7 @@ PciePortInitCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -192,7 +192,7 @@ PciePortInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -232,7 +232,7 @@ PciePortPostInitCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -260,7 +260,7 @@ PciePortPostInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports on S3 resume path
*
@@ -304,7 +304,7 @@ PciePortPostS3InitCallback (
PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init port on S3 resume during destributed training
*
@@ -332,7 +332,7 @@ PciePortPostS3Init (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c
index befc8f5..cc8a76e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c
@@ -99,7 +99,7 @@ PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM
*
@@ -130,7 +130,7 @@ PcieEnableAspm (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slot power limit
*
@@ -168,7 +168,7 @@ PcieSlotPowerLimit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -199,7 +199,7 @@ PciePortLateInitCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c
index 70f00f4..1e48ecc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return whether the current configuration exceeds the capability.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c
index 41250ca..0a80d50 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -70,7 +70,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable config access to a non-coherent chain for the given bus range.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c
index 397e7f2..09cce1c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
@@ -142,7 +142,7 @@ Fam10NorthBridgeFreqMask (
return (Supported);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
index 2bdf406..76c55f4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
@@ -107,7 +107,7 @@ typedef union {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the traffic distribution register for the Links provided.
*
@@ -154,7 +154,7 @@ Fam10WriteTrafficDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write a link pair to the link pair distribution and fixups.
*
@@ -238,7 +238,7 @@ Fam10WriteLinkPairDistribution (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
@@ -319,7 +319,7 @@ Fam10BufferOptimizations (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c
index cb28b08..427d163 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -123,7 +123,7 @@ Fam10GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -176,7 +176,7 @@ Fam10RevDGetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the next link for iterating over the links on a node in the correct order.
*
@@ -267,7 +267,7 @@ Fam10GetNextLink (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Info about Module Type of this northbridge
*
@@ -307,7 +307,7 @@ Fam10GetModuleInfo (
*Module = (UINT8) IntNodeNum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -334,7 +334,7 @@ Fam10GetSocket (
return (Node);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -370,7 +370,7 @@ Fam10RevDGetSocket (
return ((UINT8) Socket);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post info to AP cores via a mailbox.
*
@@ -409,7 +409,7 @@ Fam10PostMailbox (
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrieve info from a node's mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c
index bb1b08f..47ba272 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c
@@ -70,7 +70,7 @@
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -103,7 +103,7 @@ Fam14GetNumCoresOnNode (
return (UINT8) (Cores + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.c
index f6b3a59..4f139f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -141,7 +141,7 @@ typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
*** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
***************************************************************************/
-/*-----------------------------------------------------------------------------------*/
+
/**
* Ensure a request / response route from target Node to bsp.
*
@@ -187,7 +187,7 @@ routeFromBSP (
State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test Compatibility of a new node, and handle failure.
*
@@ -261,7 +261,7 @@ CheckCompatible (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check the system MP capability with a new node and handle any failure.
*
@@ -315,7 +315,7 @@ CheckCapable (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make all the tests needed to determine if a link should be added to the system data structure.
*
@@ -380,7 +380,7 @@ IsLinkToAdd (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Explore for a new node over a link, handling whatever is found.
*
@@ -480,7 +480,7 @@ ExploreNode (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process all the saved new node info for the current processor.
*
@@ -537,7 +537,7 @@ ProcessSavedNodeInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create and add a new link to the system data structure.
*
@@ -585,7 +585,7 @@ AddLinkToSystem (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Start discovery from a new node.
*
@@ -630,7 +630,7 @@ StartFromANewNode (
State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Back up from exploring a one-deep internal node.
*
@@ -657,7 +657,7 @@ BackUpFromANode (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dynamically Discover all coherent devices in the system.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.c
index 236c1e5..b364e6f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.c
@@ -99,7 +99,7 @@ RDATA_GROUP (G1_PEICC)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.c
index b106113..655621c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process a non-coherent Link.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.c
index 65d6c27..7a69dac 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.c
@@ -108,7 +108,7 @@ extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Given the bits set in the register field, return the width it represents.
*
@@ -163,7 +163,7 @@ ConvertBitsToWidth (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Translate a desired width setting to the bits to set in the register field.
*
@@ -217,7 +217,7 @@ ConvertWidthToBits (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Access HT Link Control Register.
*
@@ -265,7 +265,7 @@ SetHtControlRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set HT Frequency register for IO Devices
*
@@ -312,7 +312,7 @@ SetHtIoFrequencyRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -409,7 +409,7 @@ GatherLinkData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Links.
*
@@ -549,7 +549,7 @@ SelectOptimalWidthAndFrequency (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
@@ -728,7 +728,7 @@ SetLinkData (
}
}
-/*------------------------------------------------------------------------------------------*/
+
/**
* Find a specific HT capability type.
*
@@ -794,7 +794,7 @@ DoesDeviceHaveHtSubtypeCap (
return IsFound;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.c
index 06629ea..051e511 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.c
@@ -107,7 +107,7 @@ typedef struct {
*** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link on source Node which connects to target Node
*
@@ -146,7 +146,7 @@ FindLinkToNode (
return TargetLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is graphA isomorphic to graphB?
*
@@ -215,7 +215,7 @@ IsIsomorphic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Topology List iterator context to the Beginning and provide the first topology.
*
@@ -247,7 +247,7 @@ BeginTopologies (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through available topologies.
*
@@ -284,7 +284,7 @@ GetNextTopology (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
@@ -439,7 +439,7 @@ LookupComputeAndLoadRoutingTables (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a Hop Count Table for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.c
index 06e60b5..f9086e3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.c
@@ -124,7 +124,7 @@ STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.c
index 98965c1..975f7eb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -97,7 +97,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Identify Links which can have traffic distribution.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
index 9b19010..f962d8c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
@@ -60,7 +60,7 @@ RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-/*-------------------------------------------------------------------------------------*/
+
/**
* Apply an IDS port override to the desired HT link.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c
index 7773f72..4e2a2bb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Establish a Temporary route from one Node to another.
*
@@ -128,7 +128,7 @@ WriteRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Modifies the NodeID register on the target Node
*
@@ -157,7 +157,7 @@ WriteNodeID (
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the Default Link
*
@@ -196,7 +196,7 @@ ReadDefaultLink (
return (UINT8)DefaultLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables on for a given Node
*
@@ -223,7 +223,7 @@ EnableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables off for a given Node
*
@@ -250,7 +250,7 @@ DisableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is coherent, connected, and ready
*
@@ -290,7 +290,7 @@ VerifyLinkIsCoherent (
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the token stored in the scratchpad register field.
*
@@ -329,7 +329,7 @@ ReadToken (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the token stored in the scratchpad register
*
@@ -365,7 +365,7 @@ WriteToken (
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Full Routing Table Register initialization
*
@@ -420,7 +420,7 @@ WriteFullRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
@@ -444,7 +444,7 @@ IsIllegalTypeMix (
return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fix (hopefully) exceptional conditions.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c
index f7775ee..b82f8ec 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -75,7 +75,7 @@ RDATA_GROUP (G1_PEICC)
*** Northbridge access routines ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link to the Southbridge
*
@@ -101,7 +101,7 @@ ReadSouthbridgeLink (
return (UINT8)Temp;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is non-coherent, connected, and ready
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbOptimization.c
index 5aeb3dd..7ea3343 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbOptimization.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbOptimization.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G1_PEICC)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -123,7 +123,7 @@ GatherLinkFeatures (
ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
@@ -154,7 +154,7 @@ SetLinkRegang (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for Unit Id Clumping.
@@ -190,7 +190,7 @@ SetLinkUnitIdClumping (
LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link frequency.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c
index 37b0b26..ec606a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the HT Host capability base PCI config address for a Link.
*
@@ -112,7 +112,7 @@ MakeLinkBase (
return LinkBase;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
@@ -184,7 +184,7 @@ ReadTrueLinkFailStatus (
return (BOOLEAN) ((After != 0) || (Unconnected != 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores and Nodes to the Node
*
@@ -224,7 +224,7 @@ SetTotalNodesAndCores (
LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -255,7 +255,7 @@ GetNodeCount (
return ((UINT8) (++Temp));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
@@ -283,7 +283,7 @@ LimitNodes (
LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, given the node and real link number.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c
index e54e53e..3e696e0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c
@@ -88,7 +88,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
index bcdfc13..f88d8e1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
@@ -56,7 +56,7 @@ RDATA_GROUP (G1_PEICC)
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the AGESA built in topology list
*
@@ -74,7 +74,7 @@ GetAmdTopolist (
*List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the number of Nodes in the compressed graph
*
@@ -90,7 +90,7 @@ GraphHowManyNodes (
return Graph[0];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns true if NodeA is directly connected to NodeB, false otherwise
*
@@ -117,7 +117,7 @@ GraphIsAdjacent (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route responses targeted at NodeB.
*
@@ -145,7 +145,7 @@ GraphGetRsp (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route requests targeted at NodeB.
*
@@ -173,7 +173,7 @@ GraphGetReq (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns a bit vector of Nodes that NodeA should forward a broadcast from
* NodeB towards
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c
index bae9cc7..9988f72 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c
@@ -188,7 +188,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -213,7 +213,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceCoherent.c
index 95d966d..372a985 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceCoherent.c
@@ -97,8 +97,8 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -168,7 +168,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -234,7 +234,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceGeneral.c
index 04807d1..2ab295d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceGeneral.c
@@ -102,7 +102,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -122,7 +122,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -202,7 +202,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -230,7 +230,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -281,7 +281,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -344,7 +344,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -444,7 +444,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -482,7 +482,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
index 43a0ba7..76592e2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -153,7 +153,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -270,7 +270,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -329,7 +329,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c
index 50281e1..d085c5b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c
@@ -88,7 +88,7 @@ IsBootCore (
IN STATE_DATA *State
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -194,7 +194,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -229,7 +229,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -299,7 +299,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -347,7 +347,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -386,7 +386,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -417,7 +417,7 @@ Tuning (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -450,7 +450,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -478,7 +478,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
index cc96906..0356dfb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
@@ -152,7 +152,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -190,7 +190,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c
index 593ab91..8ac5086 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -127,7 +127,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -160,7 +160,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -196,7 +196,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -231,7 +231,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -263,7 +263,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -304,7 +304,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -342,7 +342,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -377,7 +377,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -412,7 +412,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -447,7 +447,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -486,7 +486,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -525,7 +525,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -555,7 +555,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -591,7 +591,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -630,7 +630,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
index d15278f..5a2412e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
@@ -48,7 +48,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -168,7 +168,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c
index 3828ea9..e4d19b8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c
@@ -110,7 +110,7 @@ STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c
index 5a2abe9..38d3093 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -106,7 +106,7 @@ STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c
index a288ba3..91c979e9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR2 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c
index f9c2e51..8867831 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c
@@ -100,7 +100,7 @@ STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c
index 69c18ff..eed812e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c
index 5680279..5cdc6f4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c
@@ -111,7 +111,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR2 L1 system
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c
index 9de3fad..4141bf4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c
@@ -110,7 +110,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c
index bfc88cd..ccfb752 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c
index 2890d38..dc24626 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c
@@ -110,7 +110,7 @@ STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c
index fca2591..50229a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c
@@ -106,7 +106,7 @@ STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c
index f3b3535..30b2b7c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c
@@ -100,7 +100,7 @@ STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c
index 08505c2..307d88b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c
index bd0913c..4d5de11 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c
@@ -86,7 +86,7 @@ STATIC CONST UINT8 ROMDATA OnSDdr3CKETri[] = {0xFF, 0xFF};
STATIC CONST UINT8 ROMDATA OnSDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
STATIC CONST UINT8 ROMDATA OnSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for ON DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c
index b4c0b68..fa95a32 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c
@@ -85,7 +85,7 @@ STATIC CONST UINT8 ROMDATA OnUDdr3CKETri[] = {0xFF, 0xFF};
STATIC CONST UINT8 ROMDATA OnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
STATIC CONST UINT8 ROMDATA OnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for ON DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c
index 8894732..c08814c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c
@@ -100,7 +100,7 @@ STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c
index 0bbf440..b92680b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c
index 546fe51..f3d3b51 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c
@@ -99,7 +99,7 @@ STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c
index fefa048..fcc2373 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c
index eea9e94..e4d4516 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c
@@ -83,7 +83,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -107,7 +107,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c
index 19a2127..ae24025 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveChannels:
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 5e65b9b..bf60334 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -107,7 +107,7 @@ CsIntSwap (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -143,7 +143,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -202,7 +202,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -299,7 +299,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
index 2d7151d..d481a7c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
@@ -100,7 +100,7 @@ MemFDMISupport2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -368,7 +368,7 @@ MemFDMISupport3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
index 29a3736..cf4a556 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
@@ -104,7 +104,7 @@ InitECCOverriedeStruct (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -166,7 +166,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -291,7 +291,7 @@ InitECCOverriedeStruct (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
index b8cc066..20367a0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
@@ -94,7 +94,7 @@ IsPowerOfTwo (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -158,7 +158,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 872bd1e..77ac248 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -93,7 +93,7 @@ MemFRASExcludeDIMM (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 69bc8dd..2a34545 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -115,7 +115,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -208,7 +208,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -468,7 +468,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -500,7 +500,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index d834cc1..8c2c79d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveRegion:
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index 6382745..3f19e37 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 71c2219..412af11 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -83,7 +83,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -114,7 +114,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c
index 5f3be9c..67e91ff 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform a check to see if node interleaving can be enabled on each node.
@@ -127,7 +127,7 @@ MemFCheckInterleaveNodes (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Applies Node memory interleaving for each node.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index c543b82..2f0477e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c
index 5cacc1f..f919a37 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Enable online spare on current node if it is requested.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index d8b6859..f522e8b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -71,7 +71,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index 9bfadfc..e287fac 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -64,7 +64,7 @@ RDATA_GROUP (G1_PEICC)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
index a8a6d46..bb01ae8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
@@ -97,7 +97,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -154,7 +154,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -196,7 +196,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -293,7 +293,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -355,7 +355,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -405,7 +405,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -455,7 +455,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -505,7 +505,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -562,7 +562,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -681,7 +681,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c
index c604f4c..679c979 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c
@@ -95,7 +95,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c
index 860dfe8..a90eb72 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c
@@ -95,7 +95,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c
index d1bfe5c..01fdecf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c
@@ -95,7 +95,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c
index eeff9d4..6262c15 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c
@@ -95,7 +95,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
index dc9f723..c5b9e4b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
@@ -98,7 +98,7 @@ MemMFlowON (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c
index 0681fdf..e46cdff 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c
@@ -96,7 +96,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c
index 0f49811..3c2aa1f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c
@@ -96,7 +96,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
index 34254f8..42d215f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
@@ -88,7 +88,7 @@ MemMFlowDef (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -99,7 +99,7 @@ memDefRet (VOID)
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -111,7 +111,7 @@ memDefTrue (VOID)
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns FALSE.
@@ -122,7 +122,7 @@ memDefFalse (VOID)
{
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function for flow control
@@ -136,7 +136,7 @@ MemMFlowDef (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns AGESA_SUCCESS.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
index b2beeb1..162c92f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
@@ -91,7 +91,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
index 36c158a..5310de3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
@@ -91,7 +91,7 @@ extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c
index 4325d6d..ebdae77 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -128,7 +128,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -217,7 +217,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c
index 3e5c1aa..c7dfa64 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c
@@ -157,7 +157,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -430,7 +430,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -479,7 +479,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -518,7 +518,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -557,7 +557,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -601,7 +601,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -659,7 +659,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
index 6134395..e482977 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
@@ -79,7 +79,7 @@ MemMEcc (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
index f826f23..b071eaf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
@@ -78,7 +78,7 @@ MemMRASExcludeDIMM (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
index 5b3e4f0..571d28c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
@@ -77,7 +77,7 @@ MemMLvDdr3 (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
@@ -129,7 +129,7 @@ MemMLvDdr3 (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes, taken into account of the
@@ -193,7 +193,7 @@ MemMLvDdr3PerformanceEnhPre (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Finalize the VDDIO for the board for performance enhancement.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
index e8c12b8..b2f509c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
@@ -74,7 +74,7 @@ MemMMctMemClr (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
index 97320d9..2780ac2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
@@ -115,7 +115,7 @@ MemMContextRestore (
*/
extern MEM_NB_SUPPORT memNBInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -231,7 +231,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -285,7 +285,7 @@ MemMContextRestore (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices that contains DQS timings
*
@@ -448,7 +448,7 @@ MemMRestoreDqsTimings (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function filters out other settings and only restores DQS timings.
@@ -557,7 +557,7 @@ MemMSetCSRNb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
index 7b120f2..a749711 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
@@ -76,7 +76,7 @@ MemMInterleaveNodes (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
index 008d3f2..29ac39c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
@@ -74,7 +74,7 @@ MemMOnlineSpare (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
index b57723b..7e94887 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
@@ -88,7 +88,7 @@ MemMParallelTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
index 5978097..6c41eaa 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
@@ -77,7 +77,7 @@ MemMStandardTraining (
IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
index 19fdbbe..4a7ef55 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
@@ -95,7 +95,7 @@ MemMUmaAlloc (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
index 392b7fc..5f5ba76 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
@@ -106,7 +106,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -294,7 +294,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
index 88b85df..e295b27 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
@@ -164,7 +164,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -256,7 +256,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -286,7 +286,7 @@ MemUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -312,7 +312,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -333,7 +333,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -361,7 +361,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -391,7 +391,7 @@ MemUWait10ns (
} while (CurrentTsc < TargetTsc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -431,7 +431,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -469,7 +469,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -510,7 +510,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -548,7 +548,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -587,7 +587,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -625,7 +625,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
index 6175ea6..7145919 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -83,7 +83,7 @@ MemConstructRemoteNBBlockC32 (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c
index c3852f3..775b01f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c
@@ -461,7 +461,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -542,7 +542,7 @@ MemS3ResumeConstructNBBlockC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -593,7 +593,7 @@ MemNS3GetRegLstPtrC32 (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -622,7 +622,7 @@ MemNS3GetDeviceRegLstC32 (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -676,7 +676,7 @@ MemNS3SetSpecialPCIRegC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
index 8945652..171ffb2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
@@ -100,7 +100,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ MemConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -348,7 +348,7 @@ MemNInitNBDataC32 (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -416,7 +416,7 @@ MemNInitDefaultsC32 (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -439,7 +439,7 @@ MemNWritePatternC32 (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -461,7 +461,7 @@ MemNReadPatternC32 (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c
index e82e78a..13b51b4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -237,7 +237,7 @@ MemNAutoConfigC32 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -266,7 +266,7 @@ MemNSendMrsCmdC32 (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -293,7 +293,7 @@ MemNBeforeDramInitC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -327,7 +327,7 @@ MemNEnDLLShutDownC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
index 7fa502d..0b7c4c3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c
index ef1fbfb..6e3f55a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c
index 3e97c44..ef812fe 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -150,7 +150,7 @@ MemNFinalizeMctC32 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c
index 580ac68..08f0591 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c
@@ -101,7 +101,7 @@ MemNGetODTDelaysC32 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemNOtherTimingC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -164,7 +164,7 @@ MemNSetOtherTimingC32 (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -208,7 +208,7 @@ MemNGetODTDelaysC32 (
ODTDelays += Ld;
return ODTDelays;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c
index 029caa7..8743cda 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c
@@ -94,10 +94,10 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c
index c2d0e78..3aea2e0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -118,7 +118,7 @@ MemNIsIdSupportedC32 (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -142,7 +142,7 @@ MemNGetSocketRelativeChannelC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -280,7 +280,7 @@ MemNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
index 1140dcc..8c123d3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -86,7 +86,7 @@ MemConstructRemoteNBBlockDA (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c
index bf574d8..90908b1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c
@@ -479,7 +479,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -560,7 +560,7 @@ MemS3ResumeConstructNBBlockDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -611,7 +611,7 @@ MemNS3GetRegLstPtrDA (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -639,7 +639,7 @@ MemNS3GetDeviceRegLstDA (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -693,7 +693,7 @@ MemNS3SetSpecialPCIRegDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
index 17057ab..40bc990 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ MemConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -355,7 +355,7 @@ MemNInitNBDataDA (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -421,7 +421,7 @@ MemNInitDefaultsDA (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -444,7 +444,7 @@ MemNWritePatternDA (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -466,7 +466,7 @@ MemNReadPatternDA (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
index 9c40946..394cc81 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -137,7 +137,7 @@ MemNBeforeDramInitDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -242,7 +242,7 @@ memNAutoConfigDA (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -271,7 +271,7 @@ MemNSendMrsCmdDA (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -302,7 +302,7 @@ MemNBeforePlatformSpecDA (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -342,7 +342,7 @@ MemNChangeAvgValue8DA (
return FALSE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -374,7 +374,7 @@ MemNEnDLLShutDownDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemNCapSpeedBatteryLifeDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
index 11d0c2f..962e724 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c
index 1a13583..82cf9d8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c
index c4d669c..5b711c0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -154,7 +154,7 @@ MemNFinalizeMctDA (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
index 713bddf..b97d8f1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
@@ -103,7 +103,7 @@ MemNPowerDownCtlDA (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -142,7 +142,7 @@ MemNOtherTimingDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -165,7 +165,7 @@ MemNSetOtherTimingDA (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
index 8d4a742..f86c9ad 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
@@ -57,7 +57,7 @@ RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c
index e173bd7..f63fa7a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -127,7 +127,7 @@ MemNIsIdSupportedDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -254,7 +254,7 @@ MemNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
index bb261ea..3f64b6a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -86,7 +86,7 @@ MemConstructRemoteNBBlockDR (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c
index a20cc6c..e5039b1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c
@@ -446,7 +446,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -527,7 +527,7 @@ MemS3ResumeConstructNBBlockDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -578,7 +578,7 @@ MemNS3GetRegLstPtrDr (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -607,7 +607,7 @@ MemNS3GetDeviceRegLstDr (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -661,7 +661,7 @@ MemNS3SetSpecialPCIRegDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
index 085356b..cf54d19 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
@@ -107,7 +107,7 @@ extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -222,7 +222,7 @@ memNAutoConfigDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -239,7 +239,7 @@ MemNBeforeDramInitDr (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -285,7 +285,7 @@ MemNSendMrsCmdDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -316,7 +316,7 @@ MemNBeforePlatformSpecDr (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -349,7 +349,7 @@ MemTCtlOnDimmMirrorDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -371,7 +371,7 @@ MemNPFenceAdjustDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c
index 0dcd43c..fa5724d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c
@@ -105,7 +105,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -230,7 +230,7 @@ MemConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -346,7 +346,7 @@ MemNInitNBDataDr (
NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -414,7 +414,7 @@ MemNInitDefaultsDR (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -437,7 +437,7 @@ MemNWritePatternDr (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -459,7 +459,7 @@ MemNReadPatternDr (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
index c31913a..a01eb37 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c
index cb1db96..c904a41 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c
index cd48a90..d660dd7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemNFinalizeMctDr (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
index ce0eebb..3758f23 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
@@ -103,7 +103,7 @@ MemNPowerDownCtlDR (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemNOtherTimingDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -164,7 +164,7 @@ MemNSetOtherTimingDR (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
index 1b3af82..7c42872 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
@@ -77,7 +77,7 @@ MemNTrainFenceWHardCodeValDr (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -105,7 +105,7 @@ MemPPhyFenceTrainingDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemNTrainFenceWHardCodeValDr (
NBPtr->SwitchDCT (NBPtr, CurDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c
index 3983083..da81e69 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -128,7 +128,7 @@ MemNIsIdSupportedDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -255,7 +255,7 @@ MemNCmnGetSetFieldDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
index f2292d5..2192231 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -83,7 +83,7 @@ MemConstructRemoteNBBlockHY (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c
index be1f2d2..a49ca56 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c
@@ -470,7 +470,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -551,7 +551,7 @@ MemS3ResumeConstructNBBlockHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -602,7 +602,7 @@ MemNS3GetRegLstPtrHy (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -631,7 +631,7 @@ MemNS3GetDeviceRegLstHy (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -685,7 +685,7 @@ MemNS3SetSpecialPCIRegHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c
index de0c820..8ae2691 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c
@@ -96,7 +96,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -239,7 +239,7 @@ MemNAutoConfigHy (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -268,7 +268,7 @@ MemNSendMrsCmdHy (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -310,7 +310,7 @@ MemNSendMrsCmdPerCsHy (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -337,7 +337,7 @@ MemNBeforeDramInitHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -371,7 +371,7 @@ MemNEnDLLShutDownHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
index 1ac0db1..b25f14b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
index 6408058..e934416 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
@@ -102,7 +102,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -228,7 +228,7 @@ MemConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -351,7 +351,7 @@ MemNInitNBDataHy (
NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -418,7 +418,7 @@ MemNInitDefaultsHY (
// ECC
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -441,7 +441,7 @@ MemNWritePatternHy (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -463,7 +463,7 @@ MemNReadPatternHy (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c
index 4e74a1f..9cbe6cd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c
index 2fd6ce0..091ac2f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -150,7 +150,7 @@ MemNFinalizeMctHy (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c
index 4e54990..2c88a3b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c
@@ -101,7 +101,7 @@ MemNGetODTDelaysHy (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemNOtherTimingHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -164,7 +164,7 @@ MemNSetOtherTimingHY (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -208,7 +208,7 @@ MemNGetODTDelaysHy (
ODTDelays += Ld;
return ODTDelays;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c
index 6d68a2c..3836f44 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c
@@ -96,10 +96,10 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c
index b8ceff3..cfd1da3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -119,7 +119,7 @@ MemNIsIdSupportedHy (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -143,7 +143,7 @@ MemNGetSocketRelativeChannelHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -281,7 +281,7 @@ MemNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
index c8782bc..ec2ede4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
@@ -105,7 +105,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -230,7 +230,7 @@ MemConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -359,7 +359,7 @@ MemNInitNBDataNi (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -425,7 +425,7 @@ MemNInitDefaultsNi (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -448,7 +448,7 @@ MemNWritePatternNi (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -471,7 +471,7 @@ MemNReadPatternNi (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c
index 5cd6270..c9c5928 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c
@@ -478,7 +478,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -559,7 +559,7 @@ MemS3ResumeConstructNBBlockNi (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -610,7 +610,7 @@ MemNS3GetRegLstPtrNi (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -638,7 +638,7 @@ MemNS3GetDeviceRegLstNi (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -692,7 +692,7 @@ MemNS3SetSpecialPCIRegNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
index fdabf0f..9dd577d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
index aebec59..d5da7e1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
@@ -328,7 +328,7 @@ VOID *MemS3RegListON[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -406,7 +406,7 @@ MemS3ResumeConstructNBBlockON (
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -447,7 +447,7 @@ MemNS3GetConPCIMaskON (
DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -498,7 +498,7 @@ MemNS3GetRegLstPtrON (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -527,7 +527,7 @@ MemNS3GetDeviceRegLstON (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -554,7 +554,7 @@ MemNS3SetDfltPllLockTimeON (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to call a CPU routine to change NB P-state and
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
index 00817b9..4dcd08a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
@@ -97,7 +97,7 @@
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -187,7 +187,7 @@ MemNAutoConfigON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -216,7 +216,7 @@ MemNSendMrsCmdON (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -299,7 +299,7 @@ MemNStitchMemoryON (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -351,7 +351,7 @@ MemNSetMaxLatencyON (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, N);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -418,7 +418,7 @@ MemNGetMaxLatParamsClientON (
MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to call a CPU routine to change NB P-state and
@@ -465,7 +465,7 @@ MemNChangeNbFrequencyWrapON (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets Dqs Odt for ON
@@ -489,7 +489,7 @@ MemNSetDqsODTON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
index 334942b..925c5b6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
@@ -92,7 +92,7 @@
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -129,7 +129,7 @@ MemNPlatformSpecificFormFactorInitON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
index 2d000d4..71ef214 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
@@ -98,7 +98,7 @@ MemNIdentifyDimmConstructorON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c
index c631fc4..c7f5f7a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c
@@ -89,7 +89,7 @@
*----------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function create the HT memory map
@@ -156,7 +156,7 @@ MemNHtMemMapInitON (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -191,7 +191,7 @@ MemNGetUmaSizeON (
return SizeOfUma;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
index a0703cc..26888c6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
@@ -98,7 +98,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -329,7 +329,7 @@ MemConstructNBBlockON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default values in the MEM_DATA_STRUCT
@@ -393,7 +393,7 @@ MemNInitDefaultsON (
RefPtr->EnableEccFeature = FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -416,7 +416,7 @@ MemNWritePatternON (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -439,7 +439,7 @@ MemNReadPatternON (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Client NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c
index 1847a1d..9926825 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c
@@ -99,7 +99,7 @@ MemNPowerDownCtlON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the non-SPD timings
@@ -127,7 +127,7 @@ MemNOtherTimingON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the non-SPD timings into the PCI registers
@@ -204,7 +204,7 @@ MemNSetOtherTimingON (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, 4);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables power down mode
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c
index 244ec86..967bbbf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c
@@ -89,7 +89,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -124,7 +124,7 @@ MemNBeforeDQSTrainingON (
MemTEndTraining (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ MemNAfterDQSTrainingON (
MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel of Ontario.
@@ -169,7 +169,7 @@ MemNCSPerChannelON (
return MAX_CS_PER_CHANNEL_ON;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based RcvEn training of Ontario.
@@ -196,7 +196,7 @@ MemNOverrideRcvEnSeedON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function force the Rd Dqs Delay to phase B (0x20)
@@ -219,7 +219,7 @@ MemNForceRdDqsPhaseBON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets RxFifo pointer during Read DQS training
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
index 8f28990..f9907d5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
@@ -85,7 +85,7 @@ MemNInitEarlySampleSupportON (
IN OUT MEM_NB_BLOCK *NBPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes early sample support for Ontario
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
index e92dec0..c578e9f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
@@ -93,7 +93,7 @@ STATIC CONST UINT8 InstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1};
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -119,7 +119,7 @@ MemNIsIdSupportedON (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -151,7 +151,7 @@ MemNBrdcstCheckON (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -319,7 +319,7 @@ MemNCmnGetSetFieldON (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
index 40a1dd6..12e4210 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
@@ -105,7 +105,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -230,7 +230,7 @@ MemConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -358,7 +358,7 @@ MemNInitNBDataPh (
NBPtr->IsSupported[CheckDllRegDis] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -424,7 +424,7 @@ MemNInitDefaultsPh (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -447,7 +447,7 @@ MemNWritePatternPh (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -470,7 +470,7 @@ MemNReadPatternPh (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c
index 3d99836..5ecf928 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c
@@ -479,7 +479,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -507,7 +507,7 @@ MemNIsIdSupportedPh (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -588,7 +588,7 @@ MemS3ResumeConstructNBBlockPh (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -639,7 +639,7 @@ MemNS3GetRegLstPtrPh (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -667,7 +667,7 @@ MemNS3GetDeviceRegLstPh (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -721,7 +721,7 @@ MemNS3SetSpecialPCIRegPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
index 59a46dc..f26eac3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c
index 978ee66..cce62c0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
index 69e111e..0923a5b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
@@ -105,7 +105,7 @@ RDATA_GROUP (G1_PEICC)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -230,7 +230,7 @@ MemConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -358,7 +358,7 @@ MemNInitNBDataRb (
NBPtr->IsSupported[CheckDllRegDis] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -424,7 +424,7 @@ MemNInitDefaultsRb (
RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -447,7 +447,7 @@ MemNWritePatternRb (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -470,7 +470,7 @@ MemNReadPatternRb (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c
index b0e3427..0c5da17 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c
@@ -479,7 +479,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -507,7 +507,7 @@ MemNIsIdSupportedRb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -588,7 +588,7 @@ MemS3ResumeConstructNBBlockRb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -639,7 +639,7 @@ MemNS3GetRegLstPtrRb (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -667,7 +667,7 @@ MemNS3GetDeviceRegLstRb (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -721,7 +721,7 @@ MemNS3SetSpecialPCIRegRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
index 38e5812..50720d2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c
index 893db0b..ff62772 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c
index 6afc3d0..3be9c64 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c
@@ -98,7 +98,7 @@ extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -137,7 +137,7 @@ MemNInitNBDataNb (
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -219,7 +219,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -245,7 +245,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -289,7 +289,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -310,7 +310,7 @@ MemNTrainingFlowNb (
return TRUE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -332,7 +332,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -483,7 +483,7 @@ MemNInsDlyCompareTestPatternNb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow for UNB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
index 7fb195d..e64a4b1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
@@ -106,7 +106,7 @@ MemNS3GetDummyReadAddr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemNS3ResumeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -268,7 +268,7 @@ MemNS3ResumeClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -363,7 +363,7 @@ MemNS3GetConPCIMaskNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -409,7 +409,7 @@ MemNS3GetCSRNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -470,7 +470,7 @@ MemNS3SetCSRNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -493,7 +493,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -516,7 +516,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -540,7 +540,7 @@ MemNS3RestoreScrubNb (
MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -570,7 +570,7 @@ MemNS3DisNbPsDbgNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -601,7 +601,7 @@ MemNS3EnNbPsDbg1Nb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -629,7 +629,7 @@ MemNS3SetDynModeChangeNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -677,7 +677,7 @@ MemNS3DisableChannelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -704,7 +704,7 @@ MemNS3SetDisAutoCompUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -736,7 +736,7 @@ MemNS3SetPreDriverCalUnb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -818,7 +818,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
index 00024e2..d003e4d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
@@ -121,7 +121,7 @@ MemNQuarterMemClk2NClkNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -359,7 +359,7 @@ MemNPlatformSpecNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -436,7 +436,7 @@ MemNPlatformSpecUnb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -463,7 +463,7 @@ MemNDisableDCTNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -496,7 +496,7 @@ MemNDisableDCTClientNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -534,7 +534,7 @@ MemNStartupDCTNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -600,7 +600,7 @@ MemNStartupDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemNChangeFrequencyHy:
@@ -736,7 +736,7 @@ MemNChangeFrequencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency the next level if it have not reached
@@ -799,7 +799,7 @@ MemNRampUpFrequencyNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -912,7 +912,7 @@ MemNProgramCycTimingsNb (
MemNSetBitFieldNb (NBPtr, BFASR, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1020,7 +1020,7 @@ MemNProgramCycTimingsClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1048,7 +1048,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1082,7 +1082,7 @@ MemNGetMaxLatParamsNb (
*DlyBiasPtr += 1; // add 1 NCLK
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1142,7 +1142,7 @@ MemNSetMaxLatencyNb (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1177,7 +1177,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1207,7 +1207,7 @@ MemNAfterStitchMemNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1229,7 +1229,7 @@ MemNGet1KTFawTkNb (
return Tab1KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1251,7 +1251,7 @@ MemNGet2KTFawTkNb (
return Tab2KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1281,7 +1281,7 @@ MemNQuarterMemClk2NClkNb (
*SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1327,7 +1327,7 @@ MemNTotalSyncComponentsNb (
return SubTotal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1355,7 +1355,7 @@ MemNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1404,7 +1404,7 @@ MemNSwapBitsUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -1488,7 +1488,7 @@ MemNProgramPlatformSpecNb (
MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1528,7 +1528,7 @@ MemNGetTrdrdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1563,7 +1563,7 @@ MemNGetTwrwrNb (
return DCTPtr->Timings.Twrwr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1608,7 +1608,7 @@ MemNGetTwrrdNb (
return DCTPtr->Timings.Twrrd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1649,7 +1649,7 @@ MemNGetTrwtTONb (
return DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1673,7 +1673,7 @@ MemNGetTrwtWBNb (
return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1693,7 +1693,7 @@ MemNGetMemClkFreqIdNb (
return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1734,7 +1734,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1754,7 +1754,7 @@ MemNGetMemClkFreqIdClientNb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1774,7 +1774,7 @@ MemNGetMemClkFreqIdUnb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1802,7 +1802,7 @@ MemNGetMemClkFreqUnb (
return MemClkFreq;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -1934,7 +1934,7 @@ MemNChangeFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -1989,7 +1989,7 @@ MemNProgramNbPstateDependentRegistersUnb (
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
@@ -2138,7 +2138,7 @@ MemNProgramNbPstateDependentRegistersClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2215,7 +2215,7 @@ MemNTotalSyncComponentsClientNb (
return (((P * MemClkPeriod + 1) / 2) + T);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2257,7 +2257,7 @@ MemNPhyPowerSavingClientNb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2299,7 +2299,7 @@ MemNSetASRSRTNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency as below:
@@ -2402,7 +2402,7 @@ MemNBeforePhyFenceTrainingClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency foras below:
@@ -2472,7 +2472,7 @@ MemNChangeNbFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2500,7 +2500,7 @@ MemNGetDramTermNb (
return DramTerm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2520,7 +2520,7 @@ MemNGetDynDramTermNb (
return (NBPtr->PsPtr->DynamicDramTerm);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2544,7 +2544,7 @@ MemNGetMR0CLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2566,7 +2566,7 @@ MemNGetMR0WRNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2588,7 +2588,7 @@ MemNGetMR2CWLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
index 0bec481..6113ba2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
@@ -234,7 +234,7 @@ MemNInitCPGUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -252,7 +252,7 @@ MemNInitCPGNb (
NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions of HW Rx En Training.
@@ -268,7 +268,7 @@ MemNInitDqsTrainRcvrEnHwNb (
{
NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables member functions of Hw Rx En Training.
@@ -291,7 +291,7 @@ MemNDisableDqsTrainRcvrEnHwNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes 9 or 18 cache lines continuously using GH CPG engine
@@ -340,7 +340,7 @@ MemNContWritePatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -432,7 +432,7 @@ MemNContReadPatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemNGenHwRcvEnReadsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes cache lines continuously using TCB CPG engine
@@ -535,7 +535,7 @@ MemNContWritePatternClientNb (
MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -591,7 +591,7 @@ MemNContReadPatternClientNb (
MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -616,7 +616,7 @@ MemNGenHwRcvEnReadsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -639,7 +639,7 @@ MemNInitCPGClientNb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -665,7 +665,7 @@ MemNCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -690,7 +690,7 @@ MemNInsDlyCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -804,7 +804,7 @@ MemNPrepareRcvrEnDlySeedNb (
);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of MEMCLKs
@@ -822,7 +822,7 @@ MemNWaitXMemClksNb (
MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Issues dummy TCB write read to zero out CL that is used for MemClr
@@ -850,7 +850,7 @@ MemNBeforeMemClrClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Activate command
@@ -885,7 +885,7 @@ MemNRrwActivateCmd (
NBPtr->WaitXMemClks (NBPtr, 75);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Precharge
@@ -926,7 +926,7 @@ MemNRrwPrechargeCmd (
// Wait 25 MEMCLKs
NBPtr->WaitXMemClks (NBPtr, 25);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -952,7 +952,7 @@ MemNGenHwRcvEnReadsUnb (
NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of reads from DRAM using the
@@ -1066,7 +1066,7 @@ MemNContReadPatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1165,7 +1165,7 @@ MemNContWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results
@@ -1224,7 +1224,7 @@ MemNCompareTestPatternUnb (
return Pass;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for offset comparison results
@@ -1266,7 +1266,7 @@ MemNInsDlyCompareTestPatternUnb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
index 245943f..a7ab1f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
@@ -103,7 +103,7 @@ MemNCleanupDctRegsNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -169,7 +169,7 @@ MemNInitMCTNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -218,7 +218,7 @@ MemNInitDCTNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
@@ -245,7 +245,7 @@ MemNTechBlockSwitchNb (
TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
index a9b21b2..fd7b9d7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
@@ -111,7 +111,7 @@ MemNC6AdjustMSRs (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -246,7 +246,7 @@ MemNSyncTargetSpeedNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -276,7 +276,7 @@ MemNSyncDctsReadyNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -397,7 +397,7 @@ MemNHtMemMapInitNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -441,7 +441,7 @@ MemNSyncAddrMapToAllNodesNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -472,7 +472,7 @@ MemNPowerDownCtlNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -538,7 +538,7 @@ MemNGetOptimalCGDDNb (
return CGDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -601,7 +601,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -656,7 +656,7 @@ GetTrainDlyFromHeapNb (
return TrainDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -769,7 +769,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -830,7 +830,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -925,7 +925,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -985,7 +985,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1003,7 +1003,7 @@ MemNGetUmaSizeNb (
return 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1036,7 +1036,7 @@ MemNAllocateC6StorageClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1109,7 +1109,7 @@ MemNAllocateC6StorageUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function readjusts TOPMEM and MTRRs after allocating storage for C6
@@ -1159,7 +1159,7 @@ MemNC6AdjustMSRs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Family-specific hook to override the DdrMaxRate value for families with a
@@ -1182,7 +1182,7 @@ MemNGetMaxDdrRateUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c
index 4045289..23670a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c
@@ -103,7 +103,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -127,7 +127,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -152,7 +152,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -170,7 +170,7 @@ MemNPhyFenceTrainingNb (
NBPtr->MemPPhyFenceTrainingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -273,7 +273,7 @@ MemNPhyFenceTrainingUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -353,7 +353,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -437,7 +437,7 @@ MemNInitPhyCompNb (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -491,7 +491,7 @@ MemNBeforeDQSTrainingNb (
MemTEndTraining (NBPtr->TechPtr);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -527,7 +527,7 @@ MemNGetTrainDlyParmsNb (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -557,7 +557,7 @@ MemNGetTrainDlyParmsClientNb (
Parms->Mask = 0x03E;
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -592,7 +592,7 @@ MemNGetTrainDlyParmsUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -736,7 +736,7 @@ MemNcmnGetSetTrainDlyNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -859,7 +859,7 @@ MemNcmnGetSetTrainDlyClientNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -946,7 +946,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determined the settings for the Reliable Read/Write engine
@@ -1011,7 +1011,7 @@ MemNSetupHwTrainingEngineUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1039,7 +1039,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1065,7 +1065,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel.
@@ -1083,7 +1083,7 @@ MemNCSPerChannelNb (
return MAX_CS_PER_CHANNEL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -1102,7 +1102,7 @@ MemNCSPerDelayNb (
return MAX_CS_PER_DELAY;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -1128,7 +1128,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -1155,7 +1155,7 @@ MemNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1174,7 +1174,7 @@ MemNPFenceAdjustUnb (
*Value16 += 2; //for LN,ON,and OR, the Avg PRE value is subtracted by 6 only.
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
index 101c3ec..a1117e8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -123,7 +123,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -155,7 +155,7 @@ MemNDctCfgSelectUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -178,7 +178,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -203,7 +203,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -263,7 +263,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -293,7 +293,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -313,7 +313,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c
index 7902e36..f840e4d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain2.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c
index 175bd27..372fee2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mntrain3.c
@@ -96,7 +96,7 @@ MemNHwWlPart2Nb (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -129,7 +129,7 @@ MemNDQSTiming3Nb (
}
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
@@ -193,7 +193,7 @@ memNSequenceDDR3Nb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c
index 37fd7f0..69a4fb0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c
@@ -168,7 +168,7 @@ STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
@@ -205,7 +205,7 @@ MemPConstructPsRC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 C32 DDR3
@@ -262,7 +262,7 @@ MemPDoPsRC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 C32 DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c
index 17dd40d..d92fd14 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
@@ -140,7 +140,7 @@ MemPConstructPsUC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 C32 DDR3
@@ -165,7 +165,7 @@ MemPDoPsUC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 C32
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
index 8009a65..9118b7c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
@@ -96,7 +96,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
{DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
{DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR2
@@ -134,7 +134,7 @@ MemPConstructPsSDA2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c
index 22e6169..29d44b0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c
@@ -110,7 +110,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR3
@@ -148,7 +148,7 @@ MemPConstructPsSDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR3
@@ -197,7 +197,7 @@ MemPDoPsSDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c
index 812330d..d16d486 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c
@@ -105,7 +105,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
@@ -143,7 +143,7 @@ MemPConstructPsUDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DA DDR3
@@ -168,7 +168,7 @@ MemPDoPsUDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
index cfc00bc..111a098 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
@@ -139,7 +139,7 @@ MemPConstructPsRDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
index 38a83b0..fc0d292 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
@@ -116,7 +116,7 @@ STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
{DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
{DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
@@ -154,7 +154,7 @@ MemPConstructPsRDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
index b9e914a..d4c69c9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
@@ -141,7 +141,7 @@ MemPConstructPsSDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
index dfa4bd2..9c12cde 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
@@ -101,7 +101,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
@@ -139,7 +139,7 @@ MemPConstructPsUDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
index 53e962d..6122232 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
@@ -97,7 +97,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
@@ -134,7 +134,7 @@ MemPConstructPsUDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c
index 2f867d2..4055bc3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c
@@ -167,7 +167,7 @@ STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
@@ -205,7 +205,7 @@ MemPConstructPsRHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 HY DDR3
@@ -261,7 +261,7 @@ MemPDoPsRHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c
index 3cd133b..a949416 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c
@@ -109,7 +109,7 @@ STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
@@ -146,7 +146,7 @@ MemPConstructPsSHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 HY DDR3
@@ -195,7 +195,7 @@ MemPDoPsSHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c
index 8c5665e..675e6d8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
@@ -141,7 +141,7 @@ MemPConstructPsUHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 HY DDR3
@@ -166,7 +166,7 @@ MemPDoPsUhy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c
index c2645d6..a7608a7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c
@@ -111,7 +111,7 @@ STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
@@ -149,7 +149,7 @@ MemPConstructPsSNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ni DDR3
@@ -198,7 +198,7 @@ MemPDoPsSNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c
index a2ea14b..e1e9529 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c
@@ -106,7 +106,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
@@ -144,7 +144,7 @@ MemPConstructPsUNi3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ni DDR3
@@ -169,7 +169,7 @@ MemPDoPsUNi3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ni
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
index f2f71a4..b6b7f97 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
@@ -98,7 +98,7 @@ MemPGetPORFreqLimitSON3 (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 ON DDR3
@@ -142,7 +142,7 @@ MemPConstructPsSON3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 ON DDR3
@@ -166,7 +166,7 @@ MemPDoPsSON3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for Sodimm DDR3 of ON
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
index d12a6d1..653300c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
@@ -99,7 +99,7 @@ STATIC CONST DRAM_TERM_ENTRY OnUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 ON DDR3
@@ -143,7 +143,7 @@ MemPConstructPsUON3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 ON DDR3
@@ -167,7 +167,7 @@ MemPDoPsUON3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 of ON
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c
index 8e03e0b..1e0396d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c
@@ -111,7 +111,7 @@ STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ph DDR3
@@ -149,7 +149,7 @@ MemPConstructPsSPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ph DDR3
@@ -198,7 +198,7 @@ MemPDoPsSPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c
index c0f4fc2..88ff981 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c
@@ -106,7 +106,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3
@@ -144,7 +144,7 @@ MemPConstructPsUPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ph DDR3
@@ -169,7 +169,7 @@ MemPDoPsUPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c
index 3206502..7a0c706 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c
@@ -111,7 +111,7 @@ STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM RB DDR3
@@ -149,7 +149,7 @@ MemPConstructPsSRb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM RB DDR3
@@ -198,7 +198,7 @@ MemPDoPsSRb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c
index 32540eb..84595a9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c
@@ -106,7 +106,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
@@ -144,7 +144,7 @@ MemPConstructPsURb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 RB DDR3
@@ -169,7 +169,7 @@ MemPDoPsURb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
index 1b40102..68adb16 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
@@ -100,7 +100,7 @@ MemPPSCGen (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -124,7 +124,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -172,7 +172,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -228,7 +228,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
@@ -245,7 +245,7 @@ MemPGetPORFreqLimitDef (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -292,7 +292,7 @@ MemPPSCFlow (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -344,7 +344,7 @@ MemPConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -380,7 +380,7 @@ MemPIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -418,7 +418,7 @@ MemPGetPsRankType (
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs the action for the rest of platform specific configuration such as
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c
index 5a6a3c3..46263f1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c
index 35b80ed..dc3e3f0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c
index 7bde435..e73da12 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c
index dc9775f..bb74d33 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c
@@ -104,7 +104,7 @@ typedef struct {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts the value of max frequency supported from a input table and
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c
index f366aee..c3c979f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c
index 87da14d..af7eda9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c
index 23b84ee..a6e6769 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC10 operating speed value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c
index 8f0084e..60be152 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c
index e8ea388..68c6563 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c
index 4627834..302b654 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
index 5bdc190..39e57ef 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
@@ -96,7 +96,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
index 99799d8..4fa5bf5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR2.
@@ -112,7 +112,7 @@ MemTAdjustTwrwr2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR2.
@@ -137,7 +137,7 @@ MemTAdjustTwrrd2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c
index 0e53984..1259265 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c
@@ -133,7 +133,7 @@ MemTGetBankAddr2 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -152,7 +152,7 @@ MemTSetDramMode2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -386,7 +386,7 @@ MemTDIMMPresence2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
@@ -502,7 +502,7 @@ MemTSPDGetTargetSpeed2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -586,7 +586,7 @@ MemTSPDCalcWidth2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -773,7 +773,7 @@ MemTAutoCycTiming2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -887,7 +887,7 @@ MemTSPDSetBanks2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -919,7 +919,7 @@ MemTGetCSIntLvAddr2 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency.
@@ -937,7 +937,7 @@ MemTSPDGetTCL2 (
return TechPtr->NBPtr->DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -969,7 +969,7 @@ MemTSysCapability2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine whether dimm(b,i) supports CL(j) and F(k)
@@ -1027,7 +1027,7 @@ MemTDimmSupports2 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the cycle time
@@ -1048,7 +1048,7 @@ MemTGetTk2 (
return TableTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1074,7 +1074,7 @@ MemTGetBankAddr2 (
return TabBankAddr[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
index 64099f2..3d4663d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index d556549..d924235 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -176,7 +176,7 @@ MemTLrdimmSyncTrainedDlys (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes LRDIMM functions.
@@ -206,7 +206,7 @@ MemTLrdimmConstructor3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a Control word command to an LRDIMM Memory Buffer
@@ -248,7 +248,7 @@ MemTSendMBCtlWord3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the value of special RCW
@@ -415,7 +415,7 @@ MemTGetSpecialMBCtlWord3 (
return Value8;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -575,7 +575,7 @@ MemTLrDimmControlRegInit3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -683,7 +683,7 @@ MemTWLPrepareLrdimm3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to all physical ranks of an LRDIMM
@@ -777,7 +777,7 @@ MemTSendAllMRCmdsLR3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value for an LRDIMM
@@ -842,7 +842,7 @@ MemTEMRS1Lr3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value for an LRDIMM
@@ -973,7 +973,7 @@ MemTLrdimmRankMultiplication (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs buffer to DRAM training for LRDIMMs
@@ -1052,7 +1052,7 @@ MemTLrdimmBuf2DramTrain3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function copies trained delays of the first rank of a QR LRDIMM to the third rank
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c
index a211c23..7fbff36 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -115,7 +115,7 @@ MemTAdjustTwrwr3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -141,7 +141,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
index 85d052c..e6e61d4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -149,7 +149,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -209,7 +209,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -246,7 +246,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c
index 1a8763f..dd68d11 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G1_PEICC)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -206,7 +206,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -325,7 +325,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -378,7 +378,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -406,7 +406,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -454,7 +454,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
index ea9cabc..9412622 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -115,7 +115,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -135,7 +135,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -418,7 +418,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -496,7 +496,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -574,7 +574,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -743,7 +743,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -879,7 +879,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -912,7 +912,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -955,7 +955,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1074,7 +1074,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1109,7 +1109,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c
index aba3282..3de2d5e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
index 8d8b6b6..4f22195 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -133,7 +133,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -153,7 +153,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -177,7 +177,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -200,7 +200,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -234,7 +234,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -288,7 +288,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -340,7 +340,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -387,7 +387,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -526,7 +526,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -640,7 +640,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c
index 9e1b7bc..314e26e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c
@@ -93,7 +93,7 @@ MemTDefaultTechnologyHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -108,7 +108,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -136,7 +136,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -170,7 +170,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -200,7 +200,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c
index 1ccab8f..502220b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
index f1fa73e..4f018ca 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
@@ -177,7 +177,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -224,7 +224,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -368,7 +368,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -615,7 +615,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -680,7 +680,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -708,7 +708,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -778,7 +778,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -822,7 +822,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c
index 3ae3f10..c76b984 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c
@@ -219,7 +219,7 @@ MemTLoadInitialRcvEnDlyOptByte (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -310,7 +310,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -339,7 +339,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -365,7 +365,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -402,7 +402,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -461,7 +461,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -539,7 +539,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -598,7 +598,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -625,7 +625,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -655,7 +655,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -679,7 +679,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -694,7 +694,7 @@ MemTMaxByteLanesByte (VOID)
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -709,7 +709,7 @@ MemTDlyTableWidthByte (VOID)
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -747,7 +747,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -799,7 +799,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -869,7 +869,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -930,7 +930,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1086,7 +1086,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1120,7 +1120,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1253,7 +1253,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c
index cdb921e..aaf3f9a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttecc.c
@@ -96,7 +96,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -145,7 +145,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c
index 2640689..1b70e22 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mtthrc.c
@@ -105,7 +105,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -126,7 +126,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -157,7 +157,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -238,7 +238,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c
index e3069f2..0b4d019 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c
index bda316a..2b14763 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c
@@ -105,7 +105,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -130,7 +130,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
index be647ea..758ac29 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
@@ -98,7 +98,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -129,7 +129,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
index e25c938..3ef75ed 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
@@ -154,7 +154,7 @@ TableName[BitFieldIndex] = ( \
#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
index 523c8e6..43b8fc7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
@@ -75,7 +75,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c
index 86d1d6e..a184cc5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c
@@ -70,7 +70,7 @@ extern OPTION_GFX_RECOVERY_CONFIGURATION OptionGfxRecoveryConfiguration; // glo
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs Gfx related initialization at the recovery entry point
*
@@ -89,7 +89,7 @@ AmdGfxRecovery (
return ((*(OptionGfxRecoveryConfiguration.GfxRecoveryFeature)) (StdHeader));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will called if OPTION_GfxRecovery is true
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
index 8339fb6..8938e8e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs Gnb Recovery related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c
index ffbd01f..95070c8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c
@@ -92,7 +92,7 @@ CONST NB_REGISTER_RECOVERY_ENTRY NbMiscInitRecoveryTable [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB at Power On
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
index 6ead2a1..d8c0f3e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
@@ -56,7 +56,7 @@ RDATA_GROUP (G2_PEI)
#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get new Socket and Node Maps.
*
@@ -111,7 +111,7 @@ NewNodeAndSocketTablesRecovery (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitReset.c
index f0a53ff..310ea96 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitReset.c
@@ -114,7 +114,7 @@ typedef struct {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Routing Tables.
*
@@ -140,7 +140,7 @@ HtrEnableRoutingTables (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process the SouthBridge Link.
*
@@ -296,7 +296,7 @@ AmdHtResetConstructor (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize HT for Reset, Boot Blocks.
*
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c
index 1e48377..3f05bb1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c
@@ -138,7 +138,7 @@ MemRecNSwitchNodeC32 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -263,7 +263,7 @@ MemRecConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -289,7 +289,7 @@ MemRecNSwitchNodeC32 (
MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -314,7 +314,7 @@ MemRecNSwitchDctC32 (
MemRecNSwitchChannelC32 (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -342,7 +342,7 @@ MemRecNSwitchChannelC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -472,7 +472,7 @@ MemRecNcmnGetSetTrainDlyC32 (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -580,7 +580,7 @@ MemRecNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -683,7 +683,7 @@ MemRecNInitNBRegTableC32 (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
index c2dc4ea..ccd4159 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -124,7 +124,7 @@ MemRecNFinalizeMctC32 (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c
index 5de3621..94fff0f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c
@@ -129,7 +129,7 @@ MemRecNIsIdSupportedDA (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -251,7 +251,7 @@ MemRecConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -275,7 +275,7 @@ MemRecNSwitchDctDA (
MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -302,7 +302,7 @@ MemRecNSwitchChannelDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -417,7 +417,7 @@ MemRecNcmnGetSetTrainDlyDA (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -520,7 +520,7 @@ MemRecNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -625,7 +625,7 @@ MemRecNInitNBRegTableDA (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c
index c9cb3f7..41cf5d2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -127,7 +127,7 @@ MemRecNFinalizeMctDA (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c
index ddce00c..109b320 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c
@@ -129,7 +129,7 @@ MemRecNIsIdSupportedDr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -251,7 +251,7 @@ MemRecConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -276,7 +276,7 @@ MemRecNSwitchDctDR (
MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -303,7 +303,7 @@ MemRecNSwitchChannelDR (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -418,7 +418,7 @@ MemRecNcmnGetSetTrainDlyDR (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -521,7 +521,7 @@ MemRecNCmnGetSetFieldDR (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -627,7 +627,7 @@ MemRecNInitNBRegTableDR (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
index d3c1bb4..33c210f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -129,7 +129,7 @@ MemRecNFinalizeMctDR (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c
index 33d3162..20d1567 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c
@@ -137,7 +137,7 @@ MemRecNSwitchNodeHy (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -262,7 +262,7 @@ MemRecConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -288,7 +288,7 @@ MemRecNSwitchNodeHy (
MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -313,7 +313,7 @@ MemRecNSwitchDctHy (
MemRecNSwitchChannelHy (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -341,7 +341,7 @@ MemRecNSwitchChannelHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -471,7 +471,7 @@ MemRecNcmnGetSetTrainDlyHy (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -579,7 +579,7 @@ MemRecNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -682,7 +682,7 @@ MemRecNInitNBRegTableHy (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
index 1e37938..88dbadb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -124,7 +124,7 @@ MemRecNFinalizeMctHy (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c
index 4f22f36..6d1fef8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c
@@ -130,7 +130,7 @@ MemRecNIsIdSupportedNi (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -251,7 +251,7 @@ MemRecConstructNBBlockNi (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -275,7 +275,7 @@ MemRecNSwitchDctNi (
MemRecNSwitchChannelNi (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -302,7 +302,7 @@ MemRecNSwitchChannelNi (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -417,7 +417,7 @@ MemRecNcmnGetSetTrainDlyNi (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -520,7 +520,7 @@ MemRecNCmnGetSetFieldNi (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -625,7 +625,7 @@ MemRecNInitNBRegTableNi (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedNi
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
index d11fad8..06fcf89 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
@@ -100,7 +100,7 @@
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -170,7 +170,7 @@ MemRecNPlatformSpecON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -213,7 +213,7 @@ MemRecNSetMaxLatencyON (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -280,7 +280,7 @@ MemRecNSetDramOdtON (
MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
@@ -394,7 +394,7 @@ MemRecNAutoConfigON (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based RcvEn training of Ontario.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c
index 95eefe0..adadb0a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c
@@ -92,7 +92,7 @@ MemRecNFinalizeMctON (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for ON DDR3
@@ -143,7 +143,7 @@ MemRecNMemInitON (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final values for specific registers
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c
index cc4cca6..49829f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c
@@ -134,7 +134,7 @@ STATIC CONST UINT32 RecModeDefRegArrayON[] = {
BFPhyFence, 0x000056B5,
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -258,7 +258,7 @@ MemRecConstructNBBlockON (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -418,7 +418,7 @@ MemRecNCmnGetSetFieldON (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -588,7 +588,7 @@ MemRecNInitNBRegTableON (
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c
index 5b32e40..2d90dcb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c
@@ -130,7 +130,7 @@ MemRecNIsIdSupportedPh (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -252,7 +252,7 @@ MemRecConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -276,7 +276,7 @@ MemRecNSwitchDctPh (
MemRecNSwitchChannelPh (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -303,7 +303,7 @@ MemRecNSwitchChannelPh (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -418,7 +418,7 @@ MemRecNcmnGetSetTrainDlyPh (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -521,7 +521,7 @@ MemRecNCmnGetSetFieldPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -626,7 +626,7 @@ MemRecNInitNBRegTablePh (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c
index 2ffbdb4..6011a93 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c
@@ -130,7 +130,7 @@ MemRecNIsIdSupportedRb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -251,7 +251,7 @@ MemRecConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -275,7 +275,7 @@ MemRecNSwitchDctRb (
MemRecNSwitchChannelRb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -302,7 +302,7 @@ MemRecNSwitchChannelRb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -417,7 +417,7 @@ MemRecNcmnGetSetTrainDlyRb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -520,7 +520,7 @@ MemRecNCmnGetSetFieldRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -625,7 +625,7 @@ MemRecNInitNBRegTableRb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
index cc9741d..e7d7a08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
@@ -93,7 +93,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a bit field from PCI register
@@ -115,7 +115,7 @@ MemRecNGetBitFieldNb (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets a bit field from PCI register
@@ -136,7 +136,7 @@ MemRecNSetBitFieldNb (
NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
@@ -159,7 +159,7 @@ MemRecNGetTrainDlyNb (
return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c
index 10bcbe3..b3db387 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c
@@ -132,7 +132,7 @@ MemRecNTrainPhyFenceNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
@@ -241,7 +241,7 @@ MemRecNAutoConfigNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -273,7 +273,7 @@ MemRecNPlatformSpecNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function reads MemClkFreqVal bit to see if the DIMMs are present in this node.
@@ -318,7 +318,7 @@ MemRecNStartupDCTNb (
while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DRAM devices on all DCTs at the same time
@@ -361,7 +361,7 @@ MemRecNStartupDCTClientNb (
IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", DDR800_FREQUENCY);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -429,7 +429,7 @@ MemRecNSetMaxLatencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -471,7 +471,7 @@ MemRecNSetDramOdtNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -521,7 +521,7 @@ MemRecNSendMrsCmdNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends the ZQCL command
@@ -549,7 +549,7 @@ MemRecNSendZQCmdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -581,7 +581,7 @@ MemRecTCtlOnDimmMirrorNb (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -610,7 +610,7 @@ MemRecNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -668,7 +668,7 @@ MemRecNTotalSyncComponentsClientNb (
return ((P * MemClkPeriod + 1) / 2) + T;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -698,7 +698,7 @@ MemRecNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -779,7 +779,7 @@ MemRecNPhyFenceTrainingNb (
MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -845,7 +845,7 @@ MemRecNTrainPhyFenceNb (
MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -944,7 +944,7 @@ MemRecNProgNbPstateDependentRegClientNb (
MemRecNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -989,7 +989,7 @@ MemRecNContReadPatternClientNb (
MemRecNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with UDIMMs configuration
@@ -1074,7 +1074,7 @@ MemRecNGetPsCfgUDIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with SODIMMs configuration
@@ -1162,7 +1162,7 @@ MemRecNGetPsCfgSODIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with RDIMMs configuration
@@ -1325,7 +1325,7 @@ MemRecNGetPsCfgRDIMM3Nb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1361,7 +1361,7 @@ RecGetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -1385,7 +1385,7 @@ MemRecNGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c
index 3615e9a..0de8a0b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c
@@ -89,7 +89,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for Nb DDR3
@@ -150,7 +150,7 @@ MemRecNMemInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a physical address of a corresponding Chip select
@@ -172,7 +172,7 @@ MemRecNGetMCTSysAddrNb (
return CSBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
@@ -237,7 +237,7 @@ MemRecNCPUMemRecTypingNb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
index 3ebc581..9079232 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -83,7 +83,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -103,7 +103,7 @@ MemNRecTrainingFlowNb (
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the client training control flow
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c
index 1fcfc14..715f422 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -137,7 +137,7 @@ MemPRecPSCFlow (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -189,7 +189,7 @@ MemPRecConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -225,7 +225,7 @@ MemPRecIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c
index 9d85199..eb7e6cc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c
index 1481316..c3ac68d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c
index d2f778c..7ac8f9f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c
index f66b9fb..afe2531 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c
index e57b93f..d319530 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c
index 8a34498..03453d9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c
index aef4e75..6b8d92c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c
index a5902d0..a594951 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
index c061958..d2aed1d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
@@ -122,7 +122,7 @@ MemRecConstructTechBlock3 (
TechPtr->DimmPresence = MemRecTDIMMPresence3;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -153,7 +153,7 @@ MemRecTBeginTraining (
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
index f6fe272..5d5848f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
@@ -104,7 +104,7 @@ MemRecTSendCtlWord3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -148,7 +148,7 @@ MemRecTDramControlRegInit3 (
MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -197,7 +197,7 @@ MemRecTGetCtlWord3 (
return (Data&0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
index de750c5..47abdfd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init
@@ -183,7 +183,7 @@ MemRecTDramInitSw3 (
IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -239,7 +239,7 @@ MemRecTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -286,7 +286,7 @@ MemRecTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -315,7 +315,7 @@ MemRecTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MSS value
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
index 6797c22..5dcd133 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -113,7 +113,7 @@ MemRecTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
index 0e1fb53..11f8274 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
@@ -111,7 +111,7 @@ MemRecTBeginWLTrain3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -178,7 +178,7 @@ MemRecTTrainDQSWriteHw3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -235,7 +235,7 @@ MemRecTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function configures the DIMMS for Write Levelization
@@ -306,7 +306,7 @@ MemRecTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
index ab4bcc7..7016e56 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -107,7 +107,7 @@ MemRecTProgramRcvrEnDly (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -179,7 +179,7 @@ MemRecTTrainRcvrEnHw (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -273,7 +273,7 @@ MemRecTPrepareRcvrEnDlySeed (
);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
index bc20486..bca91a1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function hard-codes DQS position delays for all bytes
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c
index dd4e716..a8af19b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c
@@ -125,7 +125,7 @@ MemRecTCompare1ClPattern (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for BSP
@@ -233,7 +233,7 @@ MemRecTTrainRcvrEnSw (
MemRecTEndTraining (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* If WrDatDly is 0, this function sets the DQS Positions in preparation
@@ -268,7 +268,7 @@ MemRecTSetWrDatRdDqs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -296,7 +296,7 @@ MemRecTSetRcvrEnDly (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -345,7 +345,7 @@ MemRecTCompare1ClPattern (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -399,7 +399,7 @@ MemRecTSaveRcvrEnDly (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
index ca0a8ba..0bdd102 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
@@ -82,7 +82,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -93,7 +93,7 @@ MemRecDefRet ()
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -106,7 +106,7 @@ MemRecDefTrue ()
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the DCT with initial values
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrinit.c
index 5a5b279..aded775 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrinit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrinit.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
extern MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default parameter, function pointers, build options
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c
index bde9fe5..04d7ff5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c
@@ -99,7 +99,7 @@ MemRecSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for HY DDR3
@@ -203,7 +203,7 @@ AmdMemRecovery (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
index 6d1ee80..2e73d08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
@@ -101,7 +101,7 @@ MemRecUSetTargetWTIO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (Index)th UINT8
@@ -127,7 +127,7 @@ MemRecUFillTrainPattern (
LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -154,7 +154,7 @@ MemRecUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -172,7 +172,7 @@ MemRecUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -199,7 +199,7 @@ MemRecUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // ;64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -223,7 +223,7 @@ MemRecUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
diff --git a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
index cb7e7f2..a893b1e 100644
--- a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
@@ -184,7 +184,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
index f6f1285..3b17b0e 100644
--- a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
@@ -113,7 +113,7 @@ GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset Stub
*
@@ -132,7 +132,7 @@ GnbInitAtReset (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Stub
*
@@ -150,7 +150,7 @@ GnbInitAtEarly (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -168,7 +168,7 @@ GnbInitDataStructAtEnvDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
@@ -187,7 +187,7 @@ GnbInitAtEnv (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -206,7 +206,7 @@ GnbInitAtPost (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
@@ -225,7 +225,7 @@ GnbInitAtMid (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
@@ -244,7 +244,7 @@ GnbInitAtLate (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AmdGnbRecovery
*
@@ -261,7 +261,7 @@ AmdGnbRecovery (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
@@ -279,7 +279,7 @@ GnbInitAtPostAfterDram (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early Before CPU Stub
*
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
index 24c1ae8..30de138 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
@@ -81,7 +81,7 @@ BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
index ef43ff5..8475558 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
@@ -62,7 +62,7 @@ RDATA_GROUP (G2_PEI)
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -128,7 +128,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
index 6c95861..2c30065 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
@@ -81,7 +81,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -108,7 +108,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -133,7 +133,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -156,7 +156,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -181,7 +181,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -205,7 +205,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -229,7 +229,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -253,7 +253,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -277,7 +277,7 @@ AgesaHookBeforeDramInitRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -300,7 +300,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -323,7 +323,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -346,7 +346,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -372,7 +372,7 @@ AgesaGetIdsData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
@@ -395,7 +395,7 @@ AgesaPcieSlotResetControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* OEM callout function for FCH data override
*
@@ -412,7 +412,7 @@ AgesaFchOemCallout (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Optional call to the host environment interface to change the external Vref for training.
*
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
index e9ca22a..593ab83 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -261,7 +261,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
index cb9e062..ae245d0 100644
--- a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
@@ -473,7 +473,7 @@ LibAmdCLFlush (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -511,7 +511,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -549,7 +549,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -579,7 +579,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -612,7 +612,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -650,7 +650,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -688,7 +688,7 @@ LibAmdMemWrite (
break;
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -718,7 +718,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -751,7 +751,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -802,7 +802,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -853,7 +853,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -883,7 +883,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -916,7 +916,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -951,7 +951,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -984,7 +984,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1024,7 +1024,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1098,7 +1098,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1124,7 +1124,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1152,7 +1152,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1188,7 +1188,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1238,7 +1238,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1260,7 +1260,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1305,7 +1305,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
index 4128769..c3cc443 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
@@ -97,7 +97,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
index 29eddf1..1ab9718 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
@@ -90,7 +90,7 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 10h CPU.
*
@@ -131,7 +131,7 @@ F10InitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 10h core.
*
@@ -150,7 +150,7 @@ F10InitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -172,7 +172,7 @@ F10GetAcpiCstObj (
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -248,7 +248,7 @@ F10CreateAcpiCstObj (
*PstateAcpiBufferPtr = CstBodyPtr;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether IO Cstate should be supported.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index d9fd330..33764fb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -86,7 +86,7 @@ SetAsymBoost (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Asymmetric Boost
* Configuration" algorithm.
@@ -139,7 +139,7 @@ F10PmAsymBoostInit (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set Asymmetric Boost.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index 672d3bb..82ab36e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -87,7 +87,7 @@ SetPstateMSR (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
*
@@ -190,7 +190,7 @@ F10PmDualPlaneOnlySupport (
}
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set P-State MSR.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 009d6a0..82baa65 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -101,7 +101,7 @@ PmNbCofVidInitWarmCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
@@ -222,7 +222,7 @@ F10PmNbCofVidInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
@@ -256,7 +256,7 @@ PmNbCofVidInitP0P1Core (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index 3642444..2cc6942 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -91,7 +91,7 @@ PmNbPstateInitCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
@@ -149,7 +149,7 @@ F10PmNbPstateInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmNbPstateInit.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
index 5d64ed4..1123515 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -90,7 +90,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable BL-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 6113956..5ee81aca 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -76,7 +76,7 @@ STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 19b390e..20e4f92 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -76,7 +76,7 @@ extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
index f373d12..115e828 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -91,7 +91,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index 190d371..dea2cef 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -77,7 +77,7 @@ STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index e66ae10..3962daa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -76,7 +76,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
index b4cb9a4..0fa9e24 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -82,7 +82,7 @@ F10InitializeHwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -118,7 +118,7 @@ F10IsHwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h CPU.
*
@@ -165,7 +165,7 @@ F10InitializeHwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
index f55c117..bec232a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
@@ -80,7 +80,7 @@ F10InitializeSwC1eOnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -100,7 +100,7 @@ F10IsSwC1eSupported (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h CPU.
*
@@ -141,7 +141,7 @@ F10InitializeSwC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e on a family 10h core.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 9aeac7b..6bb3760 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -79,7 +79,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision C processor.
*
@@ -165,7 +165,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision C processor.
*
@@ -246,7 +246,7 @@ F10CommonRevCGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -277,7 +277,7 @@ F10CommonRevCGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -348,7 +348,7 @@ F10CommonRevCGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -422,7 +422,7 @@ F10RevCGetMinMaxNbFrequency (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -462,7 +462,7 @@ F10CommonRevCIsNbPstateEnabled (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index 7756489..7498208 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -79,7 +79,7 @@ STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index 5eff60f..a7c67a1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -76,7 +76,7 @@ extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
index d16b4e7..bb4e4bc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
@@ -114,7 +114,7 @@ F10IsNonOptimalConfig (
*
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports L3 dependent features.
*
@@ -160,7 +160,7 @@ F10IsL3FeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports HT Assist.
*
@@ -203,7 +203,7 @@ F10IsHtAssistSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the Probe filter feature.
*
@@ -252,7 +252,7 @@ F10HtAssistInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save the current settings of the scrubbers, and disabled them.
*
@@ -307,7 +307,7 @@ F10GetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restore the initial settings for the scrubbers.
*
@@ -355,7 +355,7 @@ F10SetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set MSR bits required for L3 dependent features on each core.
*
@@ -380,7 +380,7 @@ F10HookDisableCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Hook before L3 features initialization sequence.
*
@@ -436,7 +436,7 @@ F10HookBeforeInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU is running in the optimal configuration.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
index 05619b1..6d360d9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -93,7 +93,7 @@ IsDramScrubberEnabled (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -118,7 +118,7 @@ F10IsMsgBasedC1eSupported (
return ((BOOLEAN) (((LogicalId.Revision) & AMD_F10_GT_D0) != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
@@ -211,7 +211,7 @@ F10InitializeMsgBasedC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable message-based C1e on a family 10h core.
*
@@ -244,7 +244,7 @@ F10InitializeMsgBasedC1eOnCore (
LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 304e870..6bdc2da 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -133,7 +133,7 @@ F10CommonRevDGetNumberOfPhysicalCores (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision D processor.
*
@@ -228,7 +228,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
F10CommonRevDSetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision D processor.
*
@@ -297,7 +297,7 @@ F10CommonRevDGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -323,7 +323,7 @@ F10CommonRevDGetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -371,7 +371,7 @@ F10CommonRevDGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -407,7 +407,7 @@ F10RevDGetMinMaxNbFrequency (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index b56e2ff..b4101f9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -84,7 +84,7 @@ STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
index a2d67d5..289fc8c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -101,7 +101,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index bff320b..6b48917 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -84,7 +84,7 @@ GetF10HyMicroCodePatchesStruct (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
index ce4f9ad..375f6ab 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
@@ -79,7 +79,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on a revision E processor.
*
@@ -174,7 +174,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
F10CommonRevESetDownCoreRegister
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current on a revision E processor.
*
@@ -245,7 +245,7 @@ F10CommonRevEGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -293,7 +293,7 @@ F10CommonRevEGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -329,7 +329,7 @@ F10RevEGetMinMaxNbFrequency (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -360,7 +360,7 @@ F10CommonRevEGetNbCofVidUpdate (
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index 14724f8..9efb86d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -75,7 +75,7 @@ STATIC CONST UINT16 ROMDATA CpuF10PhMicrocodeEquivalenceTable[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index 315cb10..bd67b7e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -75,7 +75,7 @@ extern CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
index 746365e..e742ea0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -93,7 +93,7 @@ typedef union {
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -130,7 +130,7 @@ F10SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -162,7 +162,7 @@ F10GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -196,7 +196,7 @@ F10GetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the system AP core number in the AP's Mailbox.
*
@@ -234,7 +234,7 @@ F10SetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -261,7 +261,7 @@ F10GetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Move the AP's core number from the mailbox to hardware.
*
@@ -298,7 +298,7 @@ F10TransferApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
index d6798bc..c96d366 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -98,7 +98,7 @@ extern CONST UINT8 F10BrandIdString2TableCount;
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
@@ -126,7 +126,7 @@ GetF10BrandIdString1 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index a0e3e20..62e1300 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -101,7 +101,7 @@ CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
index bf06e70..fa82725 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -100,7 +100,7 @@ SetF10CacheFlushOnHaltRegister (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c
index c5b71b3..ad3d65e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -107,7 +107,7 @@ F10IsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 376ec63..5d4bacd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -110,7 +110,7 @@ F10Translate7BitVidTo6Bit (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetInfo
@@ -181,7 +181,7 @@ DmiF10GetInfo (
CpuInfoPtr->L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetVoltage
@@ -247,7 +247,7 @@ DmiF10GetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMaxSpeed
@@ -277,7 +277,7 @@ DmiF10GetMaxSpeed (
return ((UINT16) P0Frequency);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetExtClock
@@ -297,7 +297,7 @@ DmiF10GetExtClock (
return (EXTERNAL_CLOCK_DFLT);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF10GetMemInfo
@@ -489,7 +489,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* F10Translate7BitVidTo6Bit
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index ae00571..f615159 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -107,7 +107,7 @@ WaitForCpuFidAndDidToMatch (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -223,7 +223,7 @@ F10PmAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
@@ -397,7 +397,7 @@ F10PmAfterResetCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
* match a specific P-state.
@@ -428,7 +428,7 @@ WaitForCpuFidAndDidToMatch (
(((COFVID_STS_MSR *) &CurrentStatus)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10PmAfterReset to Core P-State Voltage Alignment for CPB on all
* cores of a family 10h socket.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index b3c8180..055f19e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -88,7 +88,7 @@ updateCpuFeatureList (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function get features which CPU supports.
@@ -207,7 +207,7 @@ F10SaveFeatures (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function set features which All CPUs support.
@@ -314,7 +314,7 @@ F10WriteFeatures (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* cpuFeatureListNeedUpdate
@@ -355,7 +355,7 @@ cpuFeatureListNeedUpdate (
return flag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* updateCpuFeatureList
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index adbf777..2748ce5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -95,7 +95,7 @@ F10PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing the family 10h Processor-
* Systemboard Power Delivery Check.
@@ -294,7 +294,7 @@ F10PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -382,7 +382,7 @@ F10PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
index 033a0a3..4609d81 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -90,7 +90,7 @@ GetF10SysPmTable (
*/
/* Family 10h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
{
IDS_INITIAL_F10_PM_STEP
@@ -152,7 +152,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
index d81d511..49d7505 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -142,7 +142,7 @@ F10PmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
@@ -302,7 +302,7 @@ F10CpuAmdPmPwrPlaneInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F10CpuAmdPmPwrPlaneInit.
*
@@ -340,7 +340,7 @@ F10PmPwrPlaneInitPviCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded altvid voltage stabilization slam time for the executing
* family 10h core.
@@ -408,7 +408,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
index 242c5a8..12c2ba2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -156,7 +156,7 @@ F10GetFrequencyXlatRegInfo (
*/
extern BUILD_OPT_CFG UserOptions;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -225,7 +225,7 @@ F10SetTscFreqSel (
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -334,7 +334,7 @@ F10GetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -391,7 +391,7 @@ F10GetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer.
*
@@ -539,7 +539,7 @@ F10PstateLevelingCoreMsrModify (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -631,7 +631,7 @@ F10GetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -665,7 +665,7 @@ F10GetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
@@ -809,7 +809,7 @@ F10GetPllValueInTime (
*PllLockTimePtr = 0;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
index c01d580..e05470c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
index 2098464..f9579ca 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -97,7 +97,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated CPU
* Voltage Transitions.'
@@ -130,7 +130,7 @@ F10PmSwVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the necessary steps for the 'Software Initiated NB
* Voltage Transitions.'
@@ -180,7 +180,7 @@ F10PmSwVoltageTransitionServerNb (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current VsSlamTime in microseconds.
*
@@ -216,7 +216,7 @@ F10GetCurrentVsTimeInUsecs (
*VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until VsSlamTime microseconds have expired.
*
@@ -237,7 +237,7 @@ F10WaitOutVoltageTransition (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Code required to be run on every local core in order to perform
* the steps necessary for 'Software Initiated NB Voltage
@@ -282,7 +282,7 @@ F10SwVoltageTransitionServerNbCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
*
@@ -366,7 +366,7 @@ F10ProgramVSSlamTimeOnSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the encoded voltage stabilization slam time for the executing
* family 10h core.
@@ -427,7 +427,7 @@ F10GetSlamTimeEncoding (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -455,7 +455,7 @@ F10DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -491,7 +491,7 @@ F10TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -526,7 +526,7 @@ F10GetTscRate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -569,7 +569,7 @@ F10GetCurrentNbFrequency (
return ReturnCode;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -690,7 +690,7 @@ F10LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU Specific Platform Type Info.
*
@@ -714,7 +714,7 @@ F10GetPlatformTypeSpecificInfo (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the next HT link.
*
@@ -839,7 +839,7 @@ F10GetNextHtLinkFeatures (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -1065,7 +1065,7 @@ F10NextLinkHasHtPhyFeats (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
@@ -1132,7 +1132,7 @@ F10SetHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the number of core performance boost states.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
index aae47ea..3f8f982 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -99,7 +99,7 @@ AMD_WHEA_INIT_DATA F10WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
index 919973e..f9f632b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
@@ -71,7 +71,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to sync internal node 1 SbiAddr setting.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c
index d872346..1b85a98 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* entry point for enabling High Performance Computing.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c
index 42d92ec..b998593 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c
@@ -89,7 +89,7 @@ F15OrReloadMicrocodePatchAfterMemInit (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -121,7 +121,7 @@ F15OrIsC6Supported (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C6 on a family 15h CPU.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c
index 07cdf34..3cd3349 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c
@@ -79,7 +79,7 @@ extern F15_OR_ES_CPB_SUPPORT F15OrEarlySampleCpbSupport;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -120,7 +120,7 @@ F15OrIsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
index 4b47e0f..2e658aa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
@@ -503,7 +503,7 @@ CONST UINT32 ROMDATA F15OrB0WeightsTable [] = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Early sample hook point during HTC initialization
*
@@ -533,7 +533,7 @@ F15OrHtcInitEarlySampleHook (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is CPB supported on this CPU
*
@@ -556,7 +556,7 @@ F15OrIsCpbDisabledEarlySample (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -579,7 +579,7 @@ F15OrIsC6DisabledEarlySample (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update the weights for affected OR B0 CPUs.
*
@@ -615,7 +615,7 @@ F15OrB0WeightsInit (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Workaround to avoid patch loading from causing NB cycles
*
@@ -644,7 +644,7 @@ F15OrEarlySamplesAvoidNbCyclesStart (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Workaround to avoid patch loading from causing NB cycles
*
@@ -670,7 +670,7 @@ F15OrEarlySamplesAvoidNbCyclesEnd (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Workaround for Ax processors after patch is loaded.
*
@@ -714,7 +714,7 @@ F15OrEarlySamplesAfterPatchLoaded (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -768,7 +768,7 @@ F15OrEarlySamplesLoadMicrocodePatch (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* F15OrEarlySamplesLoadMicrocode
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
index 0474f74..2e68a2c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
@@ -97,7 +97,7 @@ STATIC CONST UINT16 ROMDATA CpuF15OrUnEncryptedMicrocodeEquivalenceTable[] =
0x6000, 0x6800
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c
index 074a950..a338ce1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c
@@ -108,7 +108,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15OrEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
@@ -132,7 +132,7 @@ GetF15OrEarlyInitOnCoreTable (
*Table = F15OrEarlyInitOnCoreTable;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor for Family15h OR.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c
index 0b259d4..5883694 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c
@@ -92,7 +92,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 15h Orochi CPU.
* Implement BIOS Requirements for Initialization of C-states
@@ -147,7 +147,7 @@ F15OrInitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 15h Orochi core.
*
@@ -166,7 +166,7 @@ F15OrInitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -210,7 +210,7 @@ F15OrGetAcpiCstObj (
return CStateAcpiObjSize;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -339,7 +339,7 @@ F15OrCreateAcpiCstObj (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c
index 1c3b0bd..692fd6d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c
@@ -117,7 +117,7 @@ F15OrIsNonOptimalConfig (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports L3 dependent features.
*
@@ -161,7 +161,7 @@ F15OrIsL3FeatureSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the Probe filter feature
*
@@ -227,7 +227,7 @@ F15OrHtAssistInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the ATM Mode feature.
*
@@ -267,7 +267,7 @@ F15OrAtmModeInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save the current settings of the scrubbers, and disabled them.
*
@@ -322,7 +322,7 @@ F15OrGetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restore the initial settings for the scrubbers.
*
@@ -370,7 +370,7 @@ F15OrSetL3ScrubCtrl (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set MSR bits required for L3 feature support on each core.
*
@@ -398,7 +398,7 @@ F15OrHookDisableCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU is running in the optimal configuration.
*
@@ -459,7 +459,7 @@ F15OrIsNonOptimalConfig (
return IsNonOptimal;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports HT Assist.
*
@@ -501,7 +501,7 @@ F15OrIsHtAssistSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the input CPU supports ATM Mode.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c
index d95422b..bac89c5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G3_DXE)
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine will be run by every cores for enabling low power Pstate.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
index 2e90160..fbeff40 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
@@ -82,7 +82,7 @@ GetF15OrMicroCodePatchesStruct (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c
index 391c485..591d1c9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c
@@ -96,7 +96,7 @@ IsDramScrubberEnabled (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -121,7 +121,7 @@ F15OrIsMsgBasedC1eSupported (
return ((BOOLEAN) ((LogicalId.Revision & AMD_F15_ALL) != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core 0 task to enable message-based C1e on a family 15h CPU.
*
@@ -237,7 +237,7 @@ F15OrInitializeMsgBasedC1e (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable message-based C1e on a family 15h Orochi core.
*
@@ -267,7 +267,7 @@ F15OrInitializeMsgBasedC1eOnCore (
LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
index b47a2d9..f894304 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
@@ -197,7 +197,7 @@ CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable = {
(TABLE_ENTRY_FIELDS *) &F15OrAM3MsrWorkarounds,
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to disable the microcode workaround for Erratum #671
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c
index 044ffdc..5a64431 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c
@@ -88,7 +88,7 @@ F15OrPmNbCofVidInitOnCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Orochi core 0 entry point for performing the "Mixed Northbridge Frequency
* Configuration Sequence"
@@ -232,7 +232,7 @@ F15OrPmNbCofVidInit (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmNbCofVidInit to perform the actual NB P-state transition
* to the leveled NB P-state settings on one core of each die in a family 15h socket.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c
index 4a66926..b68a0bb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c
@@ -89,7 +89,7 @@ GetF15OrSysPmTable (
*/
/* Family 15h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF15OrSysPmTableArray[] =
{
@@ -147,7 +147,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF15OrSysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c
index 7c32ca3..1444375 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c
@@ -93,7 +93,7 @@ F15OrPmVrmLowPowerModeEnable (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h core 0 entry point for performing power plane initialization.
*
@@ -159,7 +159,7 @@ F15OrPmPwrPlaneInit (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
index 7646cb9..1670a67 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
@@ -334,7 +334,7 @@ CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update the FP_CFG MSR in current processor for Family15h OR.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
index 1df53e0..d2c5d62 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
@@ -113,7 +113,7 @@ F15OrSetDownCoreRegister (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current.
*
@@ -174,7 +174,7 @@ F15OrGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on Orochi
*
@@ -336,7 +336,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -371,7 +371,7 @@ F15OrGetCurrentNbFrequency (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -449,7 +449,7 @@ F15OrGetMinMaxNbFrequency (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -506,7 +506,7 @@ F15OrGetNbPstateInfo (
return PstateIsValid;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
@@ -547,7 +547,7 @@ F15OrGetNumberOfPhysicalCores (
return ((UINT8) CmpCap);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -581,7 +581,7 @@ F15OrGetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the system AP core number in the AP's Mailbox.
*
@@ -619,7 +619,7 @@ F15OrSetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -646,7 +646,7 @@ F15OrGetApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Move the AP's core number from the mailbox to hardware.
*
@@ -683,7 +683,7 @@ F15OrTransferApCoreNumber (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state.
* - clear F5x1[6C:64]
@@ -757,7 +757,7 @@ F15OrNbPstateDis (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state on core.
* - clear MSRC001_00[6B:64][NbPstate].
@@ -783,7 +783,7 @@ F15OrNbPstateDisCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to override CPU TDP Limit 2 setting.
*
@@ -824,7 +824,7 @@ F15OrOverrideNodeTdpLimit (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to override CPU Node TDP Accumulator Throttle Threshold setting.
*
@@ -871,7 +871,7 @@ F15OrOverrideNodeTdpAccumulatorThrottleThreshold (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to sync internal node 1 SbiAddr setting.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c
index 511b56a..d57e759 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c
@@ -103,7 +103,7 @@ SetF15OrCacheFlushOnHaltRegister (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c
index d44f1b0..56e0536 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c
@@ -93,7 +93,7 @@ F15OrPmCoreAfterResetPhase2OnCore (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Orochi core 0 entry point for performing the necessary steps for core
* P-states after a warm reset has occurred.
@@ -160,7 +160,7 @@ F15OrPmCoreAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all
* cores of a family 15h socket.
@@ -199,7 +199,7 @@ F15OrPmCoreAfterResetPhase1OnCore (
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all
* cores of a family 15h socket.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c
index 2f2ba94..72e6011 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c
@@ -133,7 +133,7 @@ DmiF15OrGetExtClock (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15OrGetInfo
@@ -207,7 +207,7 @@ DmiF15OrGetInfo (
CpuInfoPtr->L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15OrGetT4ProcFamily
@@ -269,7 +269,7 @@ DmiF15OrGetT4ProcFamily (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15OrGetVoltage
@@ -314,7 +314,7 @@ DmiF15OrGetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15OrGetMemInfo
@@ -374,7 +374,7 @@ DmiF15OrGetMemInfo (
CpuGetMemInfoPtr->PartitionRowPosition = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15OrGetExtClock
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
index c7357dc..b3d6a04 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
@@ -88,7 +88,7 @@ updateCpuFeatureList (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function get features which CPU supports.
@@ -221,7 +221,7 @@ F15OrSaveFeatures (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function set features which All CPUs support.
@@ -343,7 +343,7 @@ F15OrWriteFeatures (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* cpuFeatureListNeedUpdate
@@ -384,7 +384,7 @@ cpuFeatureListNeedUpdate (
return flag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* updateCpuFeatureList
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c
index 1a74b20..6df7578 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c
@@ -109,7 +109,7 @@ WaitForNbTransitionToComplete (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Orochi core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -179,7 +179,7 @@ F15OrPmNbAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
@@ -246,7 +246,7 @@ F15OrPmNbAfterResetOnCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmNbAfterResetOnCore to transition to the low NB P-state.
*
@@ -279,7 +279,7 @@ TransitionToNbLow (
WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmNbAfterResetOnCore to transition to the high NB P-state.
*
@@ -310,7 +310,7 @@ TransitionToNbHigh (
WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15OrPmAfterResetCore to wait for NB FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
index c926f11..feb91fb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
@@ -159,7 +159,7 @@ F15OrGetPstateRegisterInfo (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -202,7 +202,7 @@ F15OrIsPstatePsdNeeded (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -260,7 +260,7 @@ F15OrSetTscFreqSel (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -369,7 +369,7 @@ F15OrGetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -426,7 +426,7 @@ F15OrGetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer.
*
@@ -577,7 +577,7 @@ F15OrPstateLevelingCoreMsrModify (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -638,7 +638,7 @@ F15OrGetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -683,7 +683,7 @@ F15OrGetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
@@ -835,7 +835,7 @@ F15OrGetPllValueInTime (
*PllLockTimePtr = 0;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c
index 4ab163f..661981f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c
@@ -82,7 +82,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
index b94f066..02af13f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -116,7 +116,7 @@ F15SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -148,7 +148,7 @@ F15GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
index 5bce8ca..0c127da 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Application Power Management
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
index 56b65da..e620d2d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -113,7 +113,7 @@ CONST CPU_F15_EXCEPTION_BRAND ROMDATA CpuF15ExceptionBrandIdString[] =
{str_Exception_0}
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the Processor Name String register based on F5x194/198
*
@@ -189,7 +189,7 @@ F15SetBrandIdRegistersAtEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check if it's an exception
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
index 712b5a4..12926ec 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -116,7 +116,7 @@ CONST CACHE_INFO ROMDATA CpuF15CacheInfoCP =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
index 1eb82f2..0a69767 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
@@ -78,7 +78,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15GetMaxSpeed
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
index ffedd5a..bc49e50 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
@@ -108,7 +108,7 @@ F15PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h core 0 entry point for performing the family 15h Processor-
* Systemboard Power Delivery Check.
@@ -311,7 +311,7 @@ F15PmPwrCheck (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* First phase core-level error handler called if any p-states were determined
* to be out of range for the mother board.
@@ -344,7 +344,7 @@ F15PwrCheckAllCoresGoToLegalPstate (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -379,7 +379,7 @@ F15PwrCheckPrimaryCoresAdjustPstates (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Second phase core-level error handler called if any p-states were determined
* to be out of range for the mother board.
@@ -412,7 +412,7 @@ F15PwrCheckAllCoresGoToCurrentPs (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
index 630ad5a..b403679 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
@@ -160,7 +160,7 @@ CONST STATIC HT_PHY_DLL_COMP_LOOKUP_TABLE ROMDATA HtPhyDllCompLookupTable[] = {
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -188,7 +188,7 @@ F15DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -224,7 +224,7 @@ F15TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -267,7 +267,7 @@ F15GetTscRate (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -435,7 +435,7 @@ F15LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the next HT link.
*
@@ -560,7 +560,7 @@ F15GetNextHtLinkFeatures (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -786,7 +786,7 @@ F15NextLinkHasHtPhyFeats (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
@@ -853,7 +853,7 @@ F15SetHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy write to a specified Phy register.
*
@@ -913,7 +913,7 @@ F15WriteOnlyHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the value of an HT PHY register.
*
@@ -973,7 +973,7 @@ F15GetHtPhyRegister (
return Temp;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to override HT DLL Compensation.
*
@@ -1100,7 +1100,7 @@ F15HtPhyOverrideDllCompensation (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -1126,7 +1126,7 @@ F15CommonGetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
index 5239723..6516474 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
@@ -98,7 +98,7 @@ AMD_WHEA_INIT_DATA F15WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c
index eb66145..0edad8f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c
@@ -83,7 +83,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The contents of the mailbox registers should always be preserved.
*
@@ -103,7 +103,7 @@ IsPreserveAroundMailboxEnabled (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c
index c7e22d9..cc89a55 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c
@@ -82,7 +82,7 @@ EnableApmOnSocket (
*/
extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Application Power Management (APM) be enabled
*
@@ -120,7 +120,7 @@ IsApmFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Application Power Management (APM)
*
@@ -169,7 +169,7 @@ InitializeApmFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable APM
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h
index 1964cef..d667d4d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Application Power Management (APM) is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_APM_IS_SUPPORTED (
/// Reference to a Method.
typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable APM.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c
index 249199e..f4e5307 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c
@@ -90,7 +90,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -128,7 +128,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -203,7 +203,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
@@ -232,7 +232,7 @@ EnableC6OnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h
index 01e65d5..24ac2fc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
@@ -104,7 +104,7 @@ typedef AGESA_STATUS F_C6_INIT (
/// Reference to a Method.
typedef F_C6_INIT *PF_C6_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to reload microcode patch after memory is initialized.
*
@@ -133,7 +133,7 @@ struct _C6_FAMILY_SERVICES {
PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index f2c2dec..3267bd3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -107,7 +107,7 @@ InitializeCacheFlushOnHaltFeature (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -127,7 +127,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
@@ -164,7 +164,7 @@ InitializeCacheFlushOnHaltFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
index ca60b2b..0beec2e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
@@ -143,7 +143,7 @@ IsPowerOfTwo (
IN UINT32 TestNumber
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -429,7 +429,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -522,7 +522,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -547,7 +547,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
@@ -595,7 +595,7 @@ CalculateOccupiedExeCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function compares two memory regions for overlap and returns the combined
* Base,Size to describe the new combined region.
@@ -723,7 +723,7 @@ CompareRegions (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This local function tests the parameter for being an even power of two
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
index f2c2bbc..138ec75 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -99,7 +99,7 @@ CoreLevelingAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -127,7 +127,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c
index 49e15a1..0b2756a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should CPB be enabled
*
@@ -116,7 +116,7 @@ IsCpbFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable core performance boost
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h
index ad24e97..3114e57 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if CPB is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_CPB_IS_SUPPORTED (
/// Reference to a Method.
typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable CPB.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
index 9fbf7e4..88852a6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
@@ -119,7 +119,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -146,7 +146,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -172,7 +172,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -397,7 +397,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -606,7 +606,7 @@ GetType4Type7Info (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* DmiGetT4ProcFamilyFromBrandId
*
@@ -645,7 +645,7 @@ DmiGetT4ProcFamilyFromBrandId (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetNameString
@@ -680,7 +680,7 @@ GetNameString (
String[StringIndex] = '\0';
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IsSourceStrContainTargetStr
@@ -737,7 +737,7 @@ IsSourceStrContainTargetStr (
return IsContained;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -772,7 +772,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -793,7 +793,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -816,7 +816,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c
index b97d3e2..4b3b0e4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -112,7 +112,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -188,7 +188,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -213,7 +213,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -238,7 +238,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h
index 2c94a42..bbb9623 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h
@@ -182,7 +182,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -201,7 +201,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c
index 4d027f6..c0db85c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -131,7 +131,7 @@ IsHwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h
index d662052..8d9b03b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if hardware C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c
index b9439e6..6a761eb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c
@@ -86,7 +86,7 @@ EnableIoCstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should IO Cstate be enabled
* If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
@@ -133,7 +133,7 @@ IsIoCstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate feature
*
@@ -169,7 +169,7 @@ InitializeIoCstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable IO Cstate on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h
index 42c861e..e57da06 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h
@@ -166,7 +166,7 @@ typedef struct _ACPI_CST_GET_INPUT {
} ACPI_CST_GET_INPUT ;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if IO Cstate is supported.
*
@@ -184,7 +184,7 @@ typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable IO Cstate.
*
@@ -203,7 +203,7 @@ typedef AGESA_STATUS F_IO_CSTATE_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to return the size of ACPI C-State Objects
*
@@ -220,7 +220,7 @@ typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to create ACPI C-State Objects
*
@@ -237,7 +237,7 @@ typedef VOID F_IO_CSTATE_CREATE_CST (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c
index 8096e2b..d91e228 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should L3 features be enabled
*
@@ -130,7 +130,7 @@ IsL3FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable L3 dependent features.
*
@@ -278,7 +278,7 @@ InitializeL3Feature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Disable all the caches on current core.
@@ -311,7 +311,7 @@ DisableAllCaches (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Enable all the caches on current core.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h
index 983dc79..e95b06c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h
@@ -64,7 +64,7 @@ AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES);
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if L3 Features are supported.
*
@@ -87,7 +87,7 @@ typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before L3 features are initialized.
*
@@ -105,7 +105,7 @@ typedef VOID F_L3_FEATURE_BEFORE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -123,7 +123,7 @@ typedef VOID F_L3_FEATURE_DISABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -141,7 +141,7 @@ typedef VOID F_L3_FEATURE_ENABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize L3 Features
*
@@ -159,7 +159,7 @@ typedef VOID F_L3_FEATURE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook after L3 Features are initialized.
*
@@ -177,7 +177,7 @@ typedef VOID F_L3_FEATURE_AFTER_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -197,7 +197,7 @@ typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -217,7 +217,7 @@ typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -238,7 +238,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize HT Assist
*
@@ -256,7 +256,7 @@ typedef VOID F_HT_ASSIST_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to provide non_optimal HT Assist support
*
@@ -277,7 +277,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if ATM Mode is supported.
*
@@ -298,7 +298,7 @@ typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize ATM mode
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c
index cde1cba..977058c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c
@@ -85,7 +85,7 @@ EnableLowPwrPstateOnCore (
*/
extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Low Power P-state be enabled
* If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
@@ -131,7 +131,7 @@ IsLowPwrPstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable low power P-state
*
@@ -187,7 +187,7 @@ InitializeLowPwrPstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable low power P-state
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h
index 4433db8..cb7bf8f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Low Power P-state is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable Low Power P-state
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c
index 315882a..e598624 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -87,7 +87,7 @@ EnableMsgC1eOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -135,7 +135,7 @@ IsMsgBasedC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Message-based C1e
*
@@ -173,7 +173,7 @@ InitializeMsgBasedC1eFeature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable message-based C1e on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h
index c7e186f..ca7f77e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c
index 6e8536c..8843025 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c
@@ -85,7 +85,7 @@ EnablePstateHpcModeOnAps (
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateHpcModeFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should P-state HPC mode be enabled
* If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE
@@ -127,7 +127,7 @@ IsPstateHpcModeFeatureSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable high performance computing (HPC mode)
*
@@ -183,7 +183,7 @@ InitializePstateHpcModeFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable Pstate HPC mode
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h
index 37e22ef..e07fbb4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h
@@ -57,7 +57,7 @@ AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable P-state HPC mode
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c
index 3c2d7cd..40d74fb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -963,7 +963,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h
index ce4487f..cbef07e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h
@@ -99,7 +99,7 @@ typedef struct {
IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
} S_CPU_AMD_PSTATE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -121,7 +121,7 @@ typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c
index e938528..d63b870 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c
@@ -134,7 +134,7 @@ ReleaseSlitBuffer (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -158,7 +158,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -183,7 +183,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -319,7 +319,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -347,7 +347,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -368,7 +368,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
index 1ad033c..392228a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
@@ -142,7 +142,7 @@ STATIC
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -165,7 +165,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -188,7 +188,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -299,7 +299,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -510,7 +510,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -546,7 +546,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c
index 926ffdd..ae590d2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -131,7 +131,7 @@ IsSwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h
index 04ea50a..b1687ea 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if software C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
/// Reference to a Method
typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable software C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
index fa62864..244608f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
@@ -97,7 +97,7 @@ GetAcpiWheaMain (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -119,7 +119,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -145,7 +145,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -243,7 +243,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c
index d95e115..f1b7d30 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c
@@ -150,7 +150,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -183,7 +183,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -280,7 +280,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -372,7 +372,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -467,7 +467,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -510,7 +510,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -556,7 +556,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -640,7 +640,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -701,7 +701,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -761,7 +761,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -867,7 +867,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -975,7 +975,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -1028,7 +1028,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1084,7 +1084,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1105,7 +1105,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1129,7 +1129,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1154,7 +1154,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1178,7 +1178,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1202,7 +1202,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c
index 7a0009e..5f9d73c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c
@@ -92,7 +92,7 @@ SetRegistersFromTablesAtEarly (
extern BUILD_OPT_CFG UserOptions;
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -153,7 +153,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -184,7 +184,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -257,7 +257,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -288,7 +288,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -339,7 +339,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Family Specific Workaround Register Entry.
*
@@ -368,7 +368,7 @@ SetRegisterForFamSpecificWorkaroundEntry (
Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers using BKDG values.
*
@@ -423,7 +423,7 @@ SetRegisterForHtPhyEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program a range of HT Phy PCI registers using BKDG values.
*
@@ -488,7 +488,7 @@ SetRegisterForHtPhyRangeEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -509,7 +509,7 @@ IsDeemphasisLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, for the current node and real link number.
*
@@ -558,7 +558,7 @@ LookupPackageLink (
return PackageLink;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the platform's specified deemphasis levels for the current link.
*
@@ -614,7 +614,7 @@ GetLinkDeemphasis (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program Deemphasis registers using BKDG values, for the platform specified levels.
*
@@ -705,7 +705,7 @@ SetRegisterForDeemphasisEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers which have complex frequency dependencies.
*
@@ -813,7 +813,7 @@ SetRegisterForHtPhyFreqEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -851,7 +851,7 @@ SetRegisterForPerformanceProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Phy Performance Profile Register Entry.
*
@@ -887,7 +887,7 @@ SetRegisterForHtPhyProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host PCI Register Entry.
*
@@ -946,7 +946,7 @@ SetRegisterForHtHostEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host Performance PCI Register Entry.
*
@@ -988,7 +988,7 @@ SetRegisterForHtHostPerfEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the HT Link Token Count registers.
*
@@ -1067,7 +1067,7 @@ SetRegisterForHtLinkTokenEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -1108,7 +1108,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -1149,7 +1149,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts PCI Register Entry.
*
@@ -1190,7 +1190,7 @@ SetRegisterForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts MSR Register Entry.
*
@@ -1223,7 +1223,7 @@ SetMsrForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Token Counts PCI Register Entry.
*
@@ -1272,7 +1272,7 @@ SetRegisterForTokenPciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link Feature PCI Register Entry.
*
@@ -1345,7 +1345,7 @@ SetRegisterForHtFeaturePciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link PCI Register Entry.
*
@@ -1402,7 +1402,7 @@ SetRegisterForHtLinkPciEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -1496,7 +1496,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -1544,7 +1544,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -1588,7 +1588,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -1623,7 +1623,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -1706,7 +1706,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
index 16c3baa..6ca8fe7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
@@ -121,11 +121,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -163,11 +163,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -623,11 +623,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -898,11 +898,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -952,11 +952,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -983,11 +983,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -1049,11 +1049,11 @@ typedef struct {
FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c
index 329abf3..fc6615c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c
@@ -198,7 +198,7 @@ ExecuteFinalHltInstruction (
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -282,7 +282,7 @@ LocalApicInitialization (
LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -306,7 +306,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -454,7 +454,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -483,7 +483,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -508,7 +508,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -532,7 +532,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -553,7 +553,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -659,7 +659,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -711,7 +711,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -778,7 +778,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -824,7 +824,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -899,7 +899,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -980,7 +980,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1127,7 +1127,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1165,7 +1165,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1213,7 +1213,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1242,7 +1242,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1273,7 +1273,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1295,7 +1295,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1328,7 +1328,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1353,7 +1353,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1395,7 +1395,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c
index fef9d48..15da6f3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c
@@ -73,7 +73,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -146,7 +146,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c
index aa9bcf9..43a8a87 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c
@@ -90,7 +90,7 @@ SetBrandIdRegistersAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
@@ -285,7 +285,7 @@ SetBrandIdRegisters (
HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c
index 1cfb827..45a4a1d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c
@@ -94,7 +94,7 @@ McaInitializationAtEarly (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
@@ -117,7 +117,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -278,7 +278,7 @@ AmdCpuEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -323,7 +323,7 @@ McaInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -345,7 +345,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
@@ -381,7 +381,7 @@ ApUtilRunCodeOnAllLocalCoresAtEarly (
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c
index 2e39af2..339ba0b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c
@@ -95,7 +95,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -132,7 +132,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -169,7 +169,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -247,7 +247,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -301,7 +301,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -363,7 +363,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c
index 02e6966..b9c5904 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c
@@ -128,7 +128,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -167,7 +167,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -190,7 +190,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -262,7 +262,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -289,7 +289,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -315,7 +315,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -338,7 +338,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -363,7 +363,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -390,7 +390,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -414,7 +414,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -457,7 +457,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
index 9e4f01c..6105f48 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
@@ -805,7 +805,7 @@ typedef enum {
} FAMILY_CACHE_INIT_POLICY;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuGeneralServices.c
index 2ce8ae5..786d3fd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuGeneralServices.c
@@ -185,7 +185,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -229,7 +229,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -273,7 +273,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -315,7 +315,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -334,7 +334,7 @@ GetPlatformNumberOfSockets ( VOID )
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -352,7 +352,7 @@ GetPlatformNumberOfModules ( VOID )
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -396,7 +396,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -439,7 +439,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -484,7 +484,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -527,7 +527,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -549,7 +549,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -571,7 +571,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -650,7 +650,7 @@ GetNumberOfCompUnitsInCurrentModule (
return ComputeUnitCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -689,7 +689,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -736,7 +736,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -775,7 +775,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -798,7 +798,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -832,7 +832,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -872,7 +872,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -915,7 +915,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -949,7 +949,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -978,7 +978,7 @@ GetSystemDegree (
return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -1008,7 +1008,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1037,7 +1037,7 @@ IsBsp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the compute unit mapping algorithm.
*
@@ -1103,7 +1103,7 @@ GetComputeUnitMapping (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is current core the primary core of its compute unit?
*
@@ -1151,7 +1151,7 @@ IsCorePairPrimary (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Are the two specified cores shared in a compute unit?
*
@@ -1200,7 +1200,7 @@ AreCoresPaired (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c
index c0d5c6c..85aff35 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c
@@ -96,7 +96,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c
index a82625d..43a24d8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c
@@ -78,7 +78,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -113,7 +113,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CpuLateInitApTask
@@ -209,7 +209,7 @@ CpuLateInitApTask (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -252,7 +252,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -283,7 +283,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -338,7 +338,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c
index 8d93aec..0168cd8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c
@@ -95,7 +95,7 @@ LoadMicrocodePatchAtEarly (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -154,7 +154,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -198,7 +198,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -257,7 +257,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -366,7 +366,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -394,7 +394,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c
index 7db09ba..457eb8b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c
@@ -105,7 +105,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -181,7 +181,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -208,7 +208,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -235,7 +235,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -353,7 +353,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -393,7 +393,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
@@ -414,7 +414,7 @@ FinalizeAtPost (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection.
*
@@ -440,7 +440,7 @@ SetTscFreqSel (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection to all cores.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c
index dba6079..d0d6d25 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c
@@ -100,7 +100,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -157,7 +157,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -196,7 +196,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -223,7 +223,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c
index 09e31fc..849a452 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -86,7 +86,7 @@ GetNextEvent (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -131,7 +131,7 @@ RunCodeOnAllSystemCore0sMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -171,7 +171,7 @@ GetNumberOfSystemPmStepsPtrMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the frequency that the northbridges must run.
*
@@ -270,7 +270,7 @@ GetSystemNbCofMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -319,7 +319,7 @@ GetSystemNbCofVidUpdateMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -457,7 +457,7 @@ GetMinNbCofMulti (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get PCI Config Space Address for the current running core.
*
@@ -500,7 +500,7 @@ GetCurrPciAddrMulti (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
@@ -544,7 +544,7 @@ ModifyCurrSocketPciMulti (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to return the next event log entry to the BSC.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c
index d153742..3759d16 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -100,7 +100,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -125,7 +125,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -174,7 +174,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -203,7 +203,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -269,7 +269,7 @@ GetMinNbCofSingle (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get PCI Config Space Address for the current running core.
*
@@ -290,7 +290,7 @@ GetCurrPciAddrSingle (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
index e7e82fd..4069c2a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -99,7 +99,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -144,7 +144,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
@@ -194,7 +194,7 @@ IsWarmReset (
return WarmReset;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
index 88c3fb3..402154d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
@@ -104,7 +104,7 @@ InsertFreeSpaceNode (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -233,7 +233,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -426,7 +426,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -558,7 +558,7 @@ HeapDeallocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -666,7 +666,7 @@ HeapLocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the heap base address
*
@@ -728,7 +728,7 @@ HeapGetBaseAddress (
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DeleteFreeSpaceNode
@@ -787,7 +787,7 @@ DeleteFreeSpaceNode (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InsertFreeSpaceNode
@@ -840,7 +840,7 @@ InsertFreeSpaceNode (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c
index 0ce6237..adb1888 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c
@@ -99,7 +99,7 @@ AllocateExecutionCacheInitializer (
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -119,7 +119,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -147,7 +147,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -182,7 +182,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
index 89862f4..eb2d9a2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
@@ -113,7 +113,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
index d270e46..64e486e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
@@ -90,7 +90,7 @@ AmdLatePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -186,7 +186,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
index ae849c4..7aee791 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
@@ -110,7 +110,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
index c04f8d2..6bb2812 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
@@ -91,7 +91,7 @@ AmdPostPlatformConfigInit (
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -199,7 +199,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitRecovery.c
index 009cca4..830980e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitRecovery.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
@@ -124,7 +124,7 @@ AmdInitRecovery (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initialize defaults and options for Amd Init Reset.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
index 5a140ae..5983f1f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
@@ -90,7 +90,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -114,7 +114,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -218,7 +218,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c
index 0ac156a..4bc1462 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -167,7 +167,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -198,7 +198,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
index 4bd7e5c..2d61ca9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G3_DXE)
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -123,7 +123,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c
index 1a2ebe2..8bf9bf0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c
@@ -85,7 +85,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -160,7 +160,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -192,7 +192,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3LateRestore stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c
index 8706af8..1347c67 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c
@@ -102,7 +102,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -283,7 +283,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -316,7 +316,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -362,7 +362,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
index f4c8e31..d85bb9d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
@@ -74,7 +74,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
index 9ddce12..47e4d03 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
@@ -77,7 +77,7 @@ FchTaskDummy (
IN VOID *DataPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return TRUE.
*
@@ -90,7 +90,7 @@ CommonReturnTrue ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -102,7 +102,7 @@ CommonReturnFalse ( VOID )
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -115,7 +115,7 @@ CommonReturnZero8 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -128,7 +128,7 @@ CommonReturnZero32 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -141,7 +141,7 @@ CommonReturnZero64 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -153,7 +153,7 @@ CommonReturnNULL ( VOID )
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -166,7 +166,7 @@ CommonReturnAgesaSuccess ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -176,7 +176,7 @@ CommonVoid ( VOID )
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
@@ -188,7 +188,7 @@ CommonAssert ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c
index c99658a..ca422ba 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c
@@ -78,7 +78,7 @@ extern CONST UINTN InitializerCount;
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -223,7 +223,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
index 5000617..3c0adc9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
@@ -83,7 +83,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -100,7 +100,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -117,7 +117,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -143,7 +143,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
index 216cd2a..c85e2d2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
@@ -78,7 +78,7 @@ S3SaveStateExtendTableLenth (
IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -94,7 +94,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -110,7 +110,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -138,7 +138,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -192,7 +192,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -220,7 +220,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -284,7 +284,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -358,7 +358,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -434,7 +434,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 info opcode
*
@@ -490,7 +490,7 @@ S3SaveStateSaveInfoOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 dispatch opcode
*
@@ -554,7 +554,7 @@ S3SaveStateSaveDispatchOp (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
@@ -599,7 +599,7 @@ S3SaveDebugOpcodeString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c
index aeee0e3..fa20fcb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return whether the current configuration exceeds the capability.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c
index 4f852ec..f7a8038 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -70,7 +70,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable config access to a non-coherent chain for the given bus range.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c
index c7b138e..f57612b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
@@ -142,7 +142,7 @@ Fam10NorthBridgeFreqMask (
return (Supported);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
index ed921a2..bcf7101 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
@@ -107,7 +107,7 @@ typedef union {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the traffic distribution register for the Links provided.
*
@@ -154,7 +154,7 @@ Fam10WriteTrafficDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write a link pair to the link pair distribution and fixups.
*
@@ -238,7 +238,7 @@ Fam10WriteLinkPairDistribution (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
@@ -319,7 +319,7 @@ Fam10BufferOptimizations (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 10h specific tunings.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c
index 8241a63..8ae333c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -123,7 +123,7 @@ Fam10GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -176,7 +176,7 @@ Fam10RevDGetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the next link for iterating over the links on a node in the correct order.
*
@@ -267,7 +267,7 @@ Fam10GetNextLink (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Info about Module Type of this northbridge
*
@@ -307,7 +307,7 @@ Fam10GetModuleInfo (
*Module = (UINT8) IntNodeNum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -334,7 +334,7 @@ Fam10GetSocket (
return (Node);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -370,7 +370,7 @@ Fam10RevDGetSocket (
return ((UINT8) Socket);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post info to AP cores via a mailbox.
*
@@ -409,7 +409,7 @@ Fam10PostMailbox (
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrieve info from a node's mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c
index 11083e8..0e3cab0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c
@@ -71,7 +71,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return whether the current configuration exceeds the capability.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c
index a383492..2f2a75e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable config access to a non-coherent chain for the given bus range.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c
index 75595c4..786f6b6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c
@@ -68,7 +68,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge specific Frequency limit.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
index 251fc9b..dfe09cd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
@@ -106,7 +106,7 @@ typedef union {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the traffic distribution register for the Links provided.
*
@@ -153,7 +153,7 @@ Fam15WriteTrafficDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set the victim distribution register for the Links provided.
*
@@ -206,7 +206,7 @@ Fam15WriteVictimDistribution (
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write a link pair to the link pair distribution and fixups.
*
@@ -290,7 +290,7 @@ Fam15WriteLinkPairDistribution (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family 15h specific tunings.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c
index ec47b36..df97a78 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -123,7 +123,7 @@ Fam15GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the next link for iterating over the links on a node in the correct order.
*
@@ -213,7 +213,7 @@ Fam15GetNextLink (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Info about Module Type of this northbridge
*
@@ -253,7 +253,7 @@ Fam15GetModuleInfo (
*Module = (UINT8) IntNodeNum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -280,7 +280,7 @@ Fam15GetSocket (
return (Node);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
@@ -316,7 +316,7 @@ Fam15StrappedGetSocket (
return ((UINT8) Socket);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the enable compute unit status for this node.
*
@@ -347,7 +347,7 @@ Fam15GetEnabledComputeUnits (
return ((UINT8) Enabled);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the dual core compute unit status for this node.
*
@@ -378,7 +378,7 @@ Fam15GetDualcoreComputeUnits (
return ((UINT8) Dual);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post info to AP cores via a mailbox.
*
@@ -417,7 +417,7 @@ Fam15PostMailbox (
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrieve info from a node's mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c
index c42697a..9a5d38f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -141,7 +141,7 @@ typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
*** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
***************************************************************************/
-/*-----------------------------------------------------------------------------------*/
+
/**
* Ensure a request / response route from target Node to bsp.
*
@@ -187,7 +187,7 @@ routeFromBSP (
State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test Compatibility of a new node, and handle failure.
*
@@ -261,7 +261,7 @@ CheckCompatible (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check the system MP capability with a new node and handle any failure.
*
@@ -315,7 +315,7 @@ CheckCapable (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make all the tests needed to determine if a link should be added to the system data structure.
*
@@ -380,7 +380,7 @@ IsLinkToAdd (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Explore for a new node over a link, handling whatever is found.
*
@@ -480,7 +480,7 @@ ExploreNode (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process all the saved new node info for the current processor.
*
@@ -537,7 +537,7 @@ ProcessSavedNodeInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create and add a new link to the system data structure.
*
@@ -585,7 +585,7 @@ AddLinkToSystem (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Start discovery from a new node.
*
@@ -630,7 +630,7 @@ StartFromANewNode (
State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Back up from exploring a one-deep internal node.
*
@@ -657,7 +657,7 @@ BackUpFromANode (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dynamically Discover all coherent devices in the system.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c
index 533d376..2dcf871 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c
@@ -99,7 +99,7 @@ RDATA_GROUP (G2_PEI)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c
index bde99c8..55934bf 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c
@@ -103,7 +103,7 @@ RDATA_GROUP (G2_PEI)
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process a non-coherent Link.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c
index c1e20bd..5a776f3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c
@@ -108,7 +108,7 @@ extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Given the bits set in the register field, return the width it represents.
*
@@ -163,7 +163,7 @@ ConvertBitsToWidth (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Translate a desired width setting to the bits to set in the register field.
*
@@ -217,7 +217,7 @@ ConvertWidthToBits (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Access HT Link Control Register.
*
@@ -265,7 +265,7 @@ SetHtControlRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set HT Frequency register for IO Devices
*
@@ -312,7 +312,7 @@ SetHtIoFrequencyRegisterBits (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -409,7 +409,7 @@ GatherLinkData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Links.
*
@@ -549,7 +549,7 @@ SelectOptimalWidthAndFrequency (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
@@ -732,7 +732,7 @@ SetLinkData (
}
}
-/*------------------------------------------------------------------------------------------*/
+
/**
* Find a specific HT capability type.
*
@@ -798,7 +798,7 @@ DoesDeviceHaveHtSubtypeCap (
return IsFound;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c
index 5d34153..d212dfb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c
@@ -107,7 +107,7 @@ typedef struct {
*** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link on source Node which connects to target Node
*
@@ -146,7 +146,7 @@ FindLinkToNode (
return TargetLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is graphA isomorphic to graphB?
*
@@ -215,7 +215,7 @@ IsIsomorphic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Topology List iterator context to the Beginning and provide the first topology.
*
@@ -247,7 +247,7 @@ BeginTopologies (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through available topologies.
*
@@ -284,7 +284,7 @@ GetNextTopology (
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
@@ -439,7 +439,7 @@ LookupComputeAndLoadRoutingTables (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a Hop Count Table for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c
index 194861a..79e211b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c
@@ -124,7 +124,7 @@ STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
index 5e9fe0e..f58775e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -119,7 +119,7 @@ UINT8 VictimedLinkFromNodeBToNodeA; ///< Victimed Link from Node B
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Identify Links which can have traffic distribution.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
index 05028db..b69b640 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
@@ -58,7 +58,7 @@ RDATA_GROUP (G2_PEI)
#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-/*-------------------------------------------------------------------------------------*/
+
/**
* Apply an IDS port override to the desired HT link.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c
index 4eca9e9..b621c71 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Establish a Temporary route from one Node to another.
*
@@ -128,7 +128,7 @@ WriteRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Modifies the NodeID register on the target Node
*
@@ -157,7 +157,7 @@ WriteNodeID (
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the Default Link
*
@@ -196,7 +196,7 @@ ReadDefaultLink (
return (UINT8)DefaultLink;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables on for a given Node
*
@@ -223,7 +223,7 @@ EnableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Turns routing tables off for a given Node
*
@@ -250,7 +250,7 @@ DisableRoutingTables (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is coherent, connected, and ready
*
@@ -290,7 +290,7 @@ VerifyLinkIsCoherent (
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read the token stored in the scratchpad register field.
*
@@ -329,7 +329,7 @@ ReadToken (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the token stored in the scratchpad register
*
@@ -365,7 +365,7 @@ WriteToken (
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Full Routing Table Register initialization
*
@@ -420,7 +420,7 @@ WriteFullRoutingTable (
LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
@@ -444,7 +444,7 @@ IsIllegalTypeMix (
return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Fix (hopefully) exceptional conditions.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c
index b563f3c..e83f44d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -75,7 +75,7 @@ RDATA_GROUP (G2_PEI)
*** Northbridge access routines ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the Link to the Southbridge
*
@@ -101,7 +101,7 @@ ReadSouthbridgeLink (
return (UINT8)Temp;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Verify that the Link is non-coherent, connected, and ready
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c
index 26aa038..6b2c904 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G2_PEI)
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Link features into system data structure.
*
@@ -123,7 +123,7 @@ GatherLinkFeatures (
ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
@@ -154,7 +154,7 @@ SetLinkRegang (
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for Unit Id Clumping.
@@ -190,7 +190,7 @@ SetLinkUnitIdClumping (
LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link frequency.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c
index 237cccc..0f98201 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the HT Host capability base PCI config address for a Link.
*
@@ -112,7 +112,7 @@ MakeLinkBase (
return LinkBase;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
@@ -184,7 +184,7 @@ ReadTrueLinkFailStatus (
return (BOOLEAN) ((After != 0) || (Unconnected != 0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores and Nodes to the Node
*
@@ -224,7 +224,7 @@ SetTotalNodesAndCores (
LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -255,7 +255,7 @@ GetNodeCount (
return ((UINT8) (++Temp));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
@@ -283,7 +283,7 @@ LimitNodes (
LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, given the node and real link number.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c
index 1ff0d66..afd0d95 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c
@@ -88,7 +88,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
index 1b9b094..192e283 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
@@ -56,7 +56,7 @@ RDATA_GROUP (G2_PEI)
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the AGESA built in topology list
*
@@ -74,7 +74,7 @@ GetAmdTopolist (
*List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the number of Nodes in the compressed graph
*
@@ -90,7 +90,7 @@ GraphHowManyNodes (
return Graph[0];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns true if NodeA is directly connected to NodeB, false otherwise
*
@@ -117,7 +117,7 @@ GraphIsAdjacent (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route responses targeted at NodeB.
*
@@ -145,7 +145,7 @@ GraphGetRsp (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns the graph Node used by NodeA to route requests targeted at NodeB.
*
@@ -173,7 +173,7 @@ GraphGetReq (
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Returns a bit vector of Nodes that NodeA should forward a broadcast from
* NodeB towards
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c
index f2cae04..c2ef628 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c
@@ -209,7 +209,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -234,7 +234,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c
index 87819dc..ada0023 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c
@@ -97,8 +97,8 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -168,7 +168,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -234,7 +234,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c
index 0e7c0d2..8d64b5e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c
@@ -102,7 +102,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -122,7 +122,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -202,7 +202,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -230,7 +230,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -281,7 +281,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -344,7 +344,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -444,7 +444,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -482,7 +482,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
index c075e15..1adc3d3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -153,7 +153,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -270,7 +270,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -329,7 +329,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c
index 43eb4f1..720f742 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c
@@ -88,7 +88,7 @@ IsBootCore (
IN STATE_DATA *State
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -194,7 +194,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -229,7 +229,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -299,7 +299,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -347,7 +347,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -386,7 +386,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -417,7 +417,7 @@ Tuning (
State->HtFeatures->TrafficDistribution (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -450,7 +450,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -478,7 +478,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
index 74d0c14..7d8c316 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
@@ -153,7 +153,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -191,7 +191,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c
index 990a67d..baf2127 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -127,7 +127,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -160,7 +160,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -196,7 +196,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -231,7 +231,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -263,7 +263,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -304,7 +304,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -342,7 +342,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -377,7 +377,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -412,7 +412,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -447,7 +447,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -486,7 +486,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -525,7 +525,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -555,7 +555,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -591,7 +591,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -630,7 +630,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
index 6507165..d25c4a7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
@@ -47,7 +47,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -167,7 +167,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c
index fa76b1f..9efd1ff 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c
@@ -109,7 +109,7 @@ STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c
index d53c41c..2706cdb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -105,7 +105,7 @@ STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c
index c1b6c3b..00b04a9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR2 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c
index 10ff5c8..8e8e981 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c
@@ -99,7 +99,7 @@ STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c
index 7498055..b07b6e6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c
index 5f8ad1a..b5509e1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c
@@ -110,7 +110,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR2 L1 system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c
index 9c7e82c..df7c0a4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c
@@ -109,7 +109,7 @@ STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c
index 203d64c..3e6e75b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c
index 3f37034..37ba182 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c
@@ -109,7 +109,7 @@ STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
// select of a single rank registered dimm
STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c
index d598392..4e9fa27 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c
@@ -105,7 +105,7 @@ STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for HY DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c
index c73f7ea..1c81c6f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G3_DXE)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for OR DDR3 L1 system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c
index 7c240a9..92b549d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c
@@ -80,7 +80,7 @@ RDATA_GROUP (G3_DXE)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for OR DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c
index bcecad9..df57011 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c
@@ -99,7 +99,7 @@ STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c
index c327655..a63832f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c
@@ -97,7 +97,7 @@ STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for PH DDR3 unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c
index ce80cae..19772af 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 SO-dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c
index 7fc27b5..e95dfc1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c
@@ -96,7 +96,7 @@ STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
// Bit 3: M[B,A]0_CS_H/L[3]
STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for RB DDR3 Unbuffered dimms
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c
index 2eea80e..1b76158 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -105,7 +105,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c
index 1c0d6a8..c4d5bf3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveChannels:
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 09ecd54..8b43f36 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -105,7 +105,7 @@ MemFUndoInterleaveBanks (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -200,7 +200,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -308,7 +308,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
index 3138f3f..7421551 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
@@ -98,7 +98,7 @@ MemFDMISupport2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -408,7 +408,7 @@ MemFDMISupport3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c
index cf4e329..fb7bac5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c
@@ -95,7 +95,7 @@ MemFCheckECC (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -161,7 +161,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c
index 0c71446..f10c539 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c
@@ -92,7 +92,7 @@ MemFInitEMP (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -156,7 +156,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 070ccd7..f0272ac 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -90,7 +90,7 @@ MemFRASExcludeDIMM (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 84f69ff..698da0f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -113,7 +113,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -206,7 +206,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -480,7 +480,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -522,7 +522,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index c707e6d..a0a0d41 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveRegion:
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index f914c9a..d872960 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index dc7f01b..f0c35e3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -112,7 +112,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c
index e827f17..a4cb857 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -95,7 +95,7 @@ MemFCheckInterleaveNodes (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform a check to see if node interleaving can be enabled on each node.
@@ -132,7 +132,7 @@ MemFCheckInterleaveNodes (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Applies Node memory interleaving for each node.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index 22a06f2..4091505 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c
index 55e038c..8d57ffc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Enable online spare on current node if it is requested.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index 271f12b..a258996 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -70,7 +70,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index 35681a1..8bce809 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -62,7 +62,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c
index 2449ff9..c623b04 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c
@@ -94,7 +94,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -198,7 +198,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -296,7 +296,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -358,7 +358,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -408,7 +408,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -508,7 +508,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -565,7 +565,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -689,7 +689,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c
index 9c295ed..2fe5903 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c
@@ -99,7 +99,7 @@ MemMFlowC32 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c
index 2ab0347..4aaf9d6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c
@@ -94,7 +94,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c
index 086daf4..c98b41a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c
@@ -94,7 +94,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c
index 915000c..f3918e7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c
@@ -99,7 +99,7 @@ MemMFlowHy (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c
index 090efa9..0e61945 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c
@@ -100,7 +100,7 @@ MemMFlowOr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c
index 2fe9984..0dfb3dc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c
@@ -94,7 +94,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c
index 0565de3..c34401e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c
@@ -94,7 +94,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c
index aa825e5..c89a253 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c
@@ -86,7 +86,7 @@ MemMFlowDef (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -97,7 +97,7 @@ memDefRet ( VOID )
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -109,7 +109,7 @@ memDefTrue ( VOID )
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns FALSE.
@@ -120,7 +120,7 @@ memDefFalse ( VOID )
{
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function for flow control
@@ -134,7 +134,7 @@ MemMFlowDef (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns AGESA_SUCCESS.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
index 924a5ae..6e5aa85 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
@@ -90,7 +90,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c
index 34fd929..00cc2bc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c
@@ -90,7 +90,7 @@ extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c
index 80df83a..cd60d1f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -127,7 +127,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -216,7 +216,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -237,7 +237,7 @@ SetMemError (
MCTPtr->ErrCode = Errorval;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c
index 2adc24a..0517d37 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c
@@ -156,7 +156,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -429,7 +429,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -478,7 +478,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -517,7 +517,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -556,7 +556,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -600,7 +600,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -658,7 +658,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c
index dbce871..d90ff1c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c
@@ -83,7 +83,7 @@ MemMEcc (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c
index 914d833..b8f1954 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c
@@ -82,7 +82,7 @@ MemMRASExcludeDIMM (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
index 2874f3f..5c8c6d8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
@@ -78,7 +78,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
@@ -138,7 +138,7 @@ MemMLvDdr3 (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes, taken into account of the
@@ -209,7 +209,7 @@ MemMLvDdr3PerformanceEnhPre (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Finalize the VDDIO for the board for performance enhancement.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c
index 4039ef6..f7e971b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c
@@ -78,7 +78,7 @@ MemMMctMemClr (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c
index df1c1d7..ebbecbf 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c
@@ -114,7 +114,7 @@ MemMContextRestore (
*/
extern MEM_NB_SUPPORT memNBInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -229,7 +229,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -283,7 +283,7 @@ MemMContextRestore (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices that contains DQS timings
*
@@ -446,7 +446,7 @@ MemMRestoreDqsTimings (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function filters out other settings and only restores DQS timings.
@@ -555,7 +555,7 @@ MemMSetCSRNb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c
index 52a3a96..f04d85e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c
@@ -79,7 +79,7 @@ MemMInterleaveNodes (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c
index e825192..2472e79 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c
@@ -76,7 +76,7 @@ MemMOnlineSpare (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c
index a596a5e..4a3640a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c
@@ -91,7 +91,7 @@ MemMParallelTraining (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
index b126dda..f2359d1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
@@ -90,7 +90,7 @@ MemMStandardTrainingUsingAdjacentDies (
*-----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
@@ -129,7 +129,7 @@ MemMStandardTraining (
return (BOOLEAN) (Die == mmPtr->DieCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTrainingUsingAdjacentDies
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
index 16f59ae..57b70c3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
@@ -93,7 +93,7 @@ MemMUmaAlloc (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c
index f202cf1..1fa89a2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c
@@ -105,7 +105,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -304,7 +304,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c
index 84a1c81..aac2098 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c
@@ -163,7 +163,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -255,7 +255,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -285,7 +285,7 @@ MemUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -311,7 +311,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -332,7 +332,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -360,7 +360,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -390,7 +390,7 @@ MemUWait10ns (
} while (CurrentTsc < TargetTsc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -480,7 +480,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -518,7 +518,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -559,7 +559,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -597,7 +597,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -636,7 +636,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -674,7 +674,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
@@ -701,7 +701,7 @@ GetVarMtrrHiMsk (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns number of memclk converted from ns
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c
index c044383..9ca2300 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -87,7 +87,7 @@ MemConstructRemoteNBBlockC32 (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c
index fda4f40..f2a3d06 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c
@@ -476,7 +476,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -557,7 +557,7 @@ MemS3ResumeConstructNBBlockC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -608,7 +608,7 @@ MemNS3GetRegLstPtrC32 (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -637,7 +637,7 @@ MemNS3GetDeviceRegLstC32 (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -691,7 +691,7 @@ MemNS3SetSpecialPCIRegC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
index 4df1a63..9906bc9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
@@ -99,7 +99,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -225,7 +225,7 @@ MemConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -352,7 +352,7 @@ MemNInitNBDataC32 (
NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -424,7 +424,7 @@ MemNInitDefaultsC32 (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -447,7 +447,7 @@ MemNWritePatternC32 (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -469,7 +469,7 @@ MemNReadPatternC32 (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c
index af946cc..42edcc0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c
@@ -97,7 +97,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -239,7 +239,7 @@ MemNAutoConfigC32 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -268,7 +268,7 @@ MemNSendMrsCmdC32 (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -295,7 +295,7 @@ MemNBeforeDramInitC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -329,7 +329,7 @@ MemNEnDLLShutDownC32 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -360,7 +360,7 @@ MemNBeforePlatformSpecC32 (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initializes extended MMIO address space
@@ -406,7 +406,7 @@ MemNInitExtMMIOAddrC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Force LvDimm voltage to 1.5V for D0 part
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
index f479ce0..eecbd43 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c
index 434e30e..a29ab4d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c
index 1790a09..b16372e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -169,7 +169,7 @@ MemNFinalizeMctC32 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c
index c2c0ffb..8b77986 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c
@@ -102,7 +102,7 @@ MemNGetODTDelaysC32 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemNOtherTimingC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -165,7 +165,7 @@ MemNSetOtherTimingC32 (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -212,7 +212,7 @@ MemNGetODTDelaysC32 (
}
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c
index 74317d7..2555278 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c
@@ -93,10 +93,10 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -165,7 +165,7 @@ MemNInitPhyCompC32 (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c
index 90baa82..2b6767b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -117,7 +117,7 @@ MemNIsIdSupportedC32 (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -141,7 +141,7 @@ MemNGetSocketRelativeChannelC32 (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -279,7 +279,7 @@ MemNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c
index 1511594..2a4f772 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -85,7 +85,7 @@ MemConstructRemoteNBBlockDA (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c
index 4ab4b80..c1f4890 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c
@@ -478,7 +478,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -559,7 +559,7 @@ MemS3ResumeConstructNBBlockDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -610,7 +610,7 @@ MemNS3GetRegLstPtrDA (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -638,7 +638,7 @@ MemNS3GetDeviceRegLstDA (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -692,7 +692,7 @@ MemNS3SetSpecialPCIRegDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
index 296f1cd..2b5ba59 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
@@ -102,7 +102,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -225,7 +225,7 @@ MemConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -356,7 +356,7 @@ MemNInitNBDataDA (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -429,7 +429,7 @@ MemNInitDefaultsDA (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -452,7 +452,7 @@ MemNWritePatternDA (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -474,7 +474,7 @@ MemNReadPatternDA (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c
index 5f26743..c6d0b89 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c
@@ -102,7 +102,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -136,7 +136,7 @@ MemNBeforeDramInitDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -241,7 +241,7 @@ memNAutoConfigDA (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -270,7 +270,7 @@ MemNSendMrsCmdDA (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -301,7 +301,7 @@ MemNBeforePlatformSpecDA (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -341,7 +341,7 @@ MemNChangeAvgValue8DA (
return FALSE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -373,7 +373,7 @@ MemNEnDLLShutDownDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -457,7 +457,7 @@ MemNCapSpeedBatteryLifeDA (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
index 3163533..54256ce 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c
index 97434ed..c61e559 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c
index c22d2c7..ddc1cb8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -163,7 +163,7 @@ MemNFinalizeMctDA (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
index a107cd8..f21fa8d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
@@ -102,7 +102,7 @@ MemNPowerDownCtlDA (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemNOtherTimingDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -164,7 +164,7 @@ MemNSetOtherTimingDA (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
index 19e47f9..f9b3bc5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
@@ -56,7 +56,7 @@ RDATA_GROUP (G2_PEI)
#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c
index ab7a51a..5c809a6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -126,7 +126,7 @@ MemNIsIdSupportedDA (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -253,7 +253,7 @@ MemNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c
index 7fd4483..95a3188 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -85,7 +85,7 @@ MemConstructRemoteNBBlockDR (
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c
index 99799c0..667506d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c
@@ -445,7 +445,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -526,7 +526,7 @@ MemS3ResumeConstructNBBlockDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -577,7 +577,7 @@ MemNS3GetRegLstPtrDr (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -606,7 +606,7 @@ MemNS3GetDeviceRegLstDr (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -660,7 +660,7 @@ MemNS3SetSpecialPCIRegDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
index 7e8e210..bdb2023 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
@@ -106,7 +106,7 @@ extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -221,7 +221,7 @@ memNAutoConfigDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -238,7 +238,7 @@ MemNBeforeDramInitDr (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -284,7 +284,7 @@ MemNSendMrsCmdDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -315,7 +315,7 @@ MemNBeforePlatformSpecDr (
MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -348,7 +348,7 @@ MemTCtlOnDimmMirrorDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -370,7 +370,7 @@ MemNPFenceAdjustDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c
index f21e1d3..59abf12 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c
@@ -104,7 +104,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -229,7 +229,7 @@ MemConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -348,7 +348,7 @@ MemNInitNBDataDr (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -423,7 +423,7 @@ MemNInitDefaultsDR (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -446,7 +446,7 @@ MemNWritePatternDr (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -468,7 +468,7 @@ MemNReadPatternDr (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
index 6970f5b..cd3722f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c
index 2cf2c1a..5269199 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c
index 497ba9c..b2fbd99 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -149,7 +149,7 @@ MemNFinalizeMctDr (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
index 5227e06..d9bad83 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
@@ -102,7 +102,7 @@ MemNPowerDownCtlDR (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -140,7 +140,7 @@ MemNOtherTimingDr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -163,7 +163,7 @@ MemNSetOtherTimingDR (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
index 68c31ee..c5c322d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
@@ -76,7 +76,7 @@ MemNTrainFenceWHardCodeValDr (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -104,7 +104,7 @@ MemPPhyFenceTrainingDr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -139,7 +139,7 @@ MemNTrainFenceWHardCodeValDr (
NBPtr->SwitchDCT (NBPtr, CurDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c
index 61bd44b..14e1873 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -127,7 +127,7 @@ MemNIsIdSupportedDr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -254,7 +254,7 @@ MemNCmnGetSetFieldDr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c
index fca7a61..a4ea627 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -87,7 +87,7 @@ MemConstructRemoteNBBlockHY (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c
index 3d6ec1d..f75eef1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c
@@ -476,7 +476,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -557,7 +557,7 @@ MemS3ResumeConstructNBBlockHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -608,7 +608,7 @@ MemNS3GetRegLstPtrHy (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -637,7 +637,7 @@ MemNS3GetDeviceRegLstHy (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -691,7 +691,7 @@ MemNS3SetSpecialPCIRegHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c
index f808280..03382d2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c
@@ -96,7 +96,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -239,7 +239,7 @@ MemNAutoConfigHy (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -268,7 +268,7 @@ MemNSendMrsCmdHy (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -310,7 +310,7 @@ MemNSendMrsCmdPerCsHy (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -337,7 +337,7 @@ MemNBeforeDramInitHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -371,7 +371,7 @@ MemNEnDLLShutDownHy (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -403,7 +403,7 @@ MemNBeforePlatformSpecHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initializes extended MMIO address space
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
index 588f27a..17a3ef4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
index 16f6b13..ea471e9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
@@ -101,7 +101,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -227,7 +227,7 @@ MemConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -353,7 +353,7 @@ MemNInitNBDataHy (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrHy;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -427,7 +427,7 @@ MemNInitDefaultsHY (
//Training Mode
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -450,7 +450,7 @@ MemNWritePatternHy (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -472,7 +472,7 @@ MemNReadPatternHy (
Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c
index fdfa5ea..d138ace 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c
index 91580b7..6efc936 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -168,7 +168,7 @@ MemNFinalizeMctHy (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c
index 1c6cab0..e2dfc1e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c
@@ -102,7 +102,7 @@ MemNGetODTDelaysHy (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemNOtherTimingHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -165,7 +165,7 @@ MemNSetOtherTimingHY (
MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -212,7 +212,7 @@ MemNGetODTDelaysHy (
}
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c
index d7b587b..7b22a25 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c
@@ -95,10 +95,10 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -181,7 +181,7 @@ MemNInitPhyCompHy (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c
index 3b8eda1..6df05a6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -118,7 +118,7 @@ MemNIsIdSupportedHy (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -142,7 +142,7 @@ MemNGetSocketRelativeChannelHy (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -280,7 +280,7 @@ MemNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c
index 5283ecd..d548b6c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c
@@ -109,7 +109,7 @@ MemNTotalSyncComponentsOr (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -286,7 +286,7 @@ MemNAutoConfigOr (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -356,7 +356,7 @@ MemNCapSpeedBatteryLifeOr (
NBPtr->NbPsCtlReg = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -416,7 +416,7 @@ MemNGetMaxLatParamsOr (
*DlyBiasPtr = (UINT16) N;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -601,7 +601,7 @@ MemNBeforeSetCsTriOr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -646,7 +646,7 @@ MemNTotalSyncComponentsOr (
return P;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -831,7 +831,7 @@ MemNProgOdtControlOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -878,7 +878,7 @@ MemNBeforeDramInitOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -904,7 +904,7 @@ MemNReleaseNbPstateOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
index 563c5e8..953f225 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
@@ -94,7 +94,7 @@ extern MEM_TECH_LRDIMM memLrdimmSupported;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
index 26ec28d..e8f0160 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
@@ -107,7 +107,7 @@ MemNFixupSysAddrOr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -157,7 +157,7 @@ MemNIdentifyDimmConstructorOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used to workaround erratum 637
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c
index 0948081..8d7bd77 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G3_DXE)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -279,7 +279,7 @@ MemNScrubberErratumOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c
index 4715de6..60adff1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c
@@ -107,7 +107,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -240,7 +240,7 @@ MemConstructNBBlockOR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -448,7 +448,7 @@ MemNInitNBDataOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -522,7 +522,7 @@ MemNInitDefaultsOR (
//Training Mode
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -545,7 +545,7 @@ MemNWritePatternOr (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -568,7 +568,7 @@ MemNReadPatternOr (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Unified NB
@@ -590,7 +590,7 @@ memNEnableTrainSequenceOr (
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c
index ef7934c..75e565a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c
@@ -97,7 +97,7 @@ MemNSetOtherTimingOR (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -132,7 +132,7 @@ MemNOtherTimingOr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c
index eb5ccb3..7718fad 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c
@@ -87,7 +87,7 @@ MemConstructRemoteNBBlockOR (
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
index d154e2f..c0bf2ff 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
@@ -120,10 +120,10 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -315,7 +315,7 @@ MemNInitPhyCompOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -351,7 +351,7 @@ MemNBeforeDQSTrainingOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -433,7 +433,7 @@ MemNAfterDQSTrainingOr (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based RcvEn training of Orochi.
@@ -461,7 +461,7 @@ MemNOverrideRcvEnSeedOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for Pass N hardware based RcvEn training of Orochi.
@@ -500,7 +500,7 @@ MemNOverrideRcvEnSeedPassNOr (
*(UINT16*) SeedTotal = ((UINT16) (((UINT32) SeedTotalPreScaling * NBPtr->DCTPtr->Timings.Speed) / NBPtr->TechPtr->PrevSpeed)) + RegisterDelay;
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for write leveing training of Orochi.
@@ -546,7 +546,7 @@ MemNOverrideWLSeedOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables nibble based training for Write Levelization for Orochi.
@@ -585,7 +585,7 @@ MemNTrainWlPerNibbleOr (
return TRUE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the WL DQS Delay based on nibble traning results for Orochi.
@@ -623,7 +623,7 @@ MemNTrainWlPerNibbleAdjustWLDlyOr (
return TRUE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the correct seed for Nibble based Write Levelization.
@@ -648,7 +648,7 @@ MemNTrainWlPerNibbleSeedOr (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes nibble based Receiver Enable Training for Orochi.
@@ -670,7 +670,7 @@ MemNInitPerNibbleTrnOr (
NBPtr->SetBitField (NBPtr, BFTrNibbleSel, NIBBLE_0);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables nibble based Receiver Enable Training for Orochi.
@@ -700,7 +700,7 @@ MemNTrainRxEnPerNibbleOr (
return TRUE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the RxEn Delay based on nibble traning results for Orochi.
@@ -740,7 +740,7 @@ MemNTrainRxEnAdjustDlyPerNibbleOr (
return TRUE;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the average nibble based Receiver Enable Training for Orochi.
@@ -775,7 +775,7 @@ MemNTrainRxEnGetAvgDlyPerNibbleOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns false if nibble training is being used and nibble 1
@@ -802,7 +802,7 @@ MemNTrainingNibbleZeroOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -824,7 +824,7 @@ MemNPFenceAdjustOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts WrDqsBias before seed scaling
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
index 65addd5..dd570db 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
@@ -71,7 +71,7 @@ MemNInitEarlySampleSupportOr (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes early sample support for Orochi
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c
index 7ba37f6..bc1b4da 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c
@@ -95,7 +95,7 @@ STATIC CONST UINT8 InstancesPerTypeOR[8] = {9, 3, 1, 0, 2, 0, 1, 1};
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedOr
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -122,7 +122,7 @@ MemNIsIdSupportedOr (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -146,7 +146,7 @@ MemNGetSocketRelativeChannelOr (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -318,7 +318,7 @@ MemNCmnGetSetFieldOr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c
index ee6b714..3f9abc6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c
@@ -789,7 +789,7 @@ VOID *MemS3RegListOr[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -874,7 +874,7 @@ MemS3ResumeConstructNBBlockOr (
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -925,7 +925,7 @@ MemNS3GetRegLstPtrOr (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -954,7 +954,7 @@ MemNS3GetDeviceRegLstOr (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -981,7 +981,7 @@ MemNS3SetDfltPllLockTimeOr (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1023,7 +1023,7 @@ MemNS3SetDynModeChangeOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1141,7 +1141,7 @@ MemNS3RestoreMR0SetPPDOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1191,7 +1191,7 @@ MemNS3GetCSROr (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
index 17ff526..32d5b4a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
@@ -104,7 +104,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -229,7 +229,7 @@ MemConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -360,7 +360,7 @@ MemNInitNBDataPh (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -433,7 +433,7 @@ MemNInitDefaultsPh (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -456,7 +456,7 @@ MemNWritePatternPh (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -479,7 +479,7 @@ MemNReadPatternPh (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c
index 33bfd26..3f77fcd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c
@@ -478,7 +478,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -506,7 +506,7 @@ MemNIsIdSupportedPh (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -587,7 +587,7 @@ MemS3ResumeConstructNBBlockPh (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -638,7 +638,7 @@ MemNS3GetRegLstPtrPh (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -666,7 +666,7 @@ MemNS3GetDeviceRegLstPh (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -720,7 +720,7 @@ MemNS3SetSpecialPCIRegPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
index d95e210..968c205 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c
index d6ac7d3..924baa1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c
index c47e09a..77ddbfa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
index cec68c1..1261c3b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
@@ -104,7 +104,7 @@ RDATA_GROUP (G2_PEI)
extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -229,7 +229,7 @@ MemConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -360,7 +360,7 @@ MemNInitNBDataRb (
NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -433,7 +433,7 @@ MemNInitDefaultsRb (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -456,7 +456,7 @@ MemNWritePatternRb (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -479,7 +479,7 @@ MemNReadPatternRb (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c
index 6e57723..4ff8c12 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c
@@ -478,7 +478,7 @@ CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = {
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -506,7 +506,7 @@ MemNIsIdSupportedRb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -587,7 +587,7 @@ MemS3ResumeConstructNBBlockRb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -638,7 +638,7 @@ MemNS3GetRegLstPtrRb (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -666,7 +666,7 @@ MemNS3GetDeviceRegLstRb (
ASSERT(FALSE); // Device register list error
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -720,7 +720,7 @@ MemNS3SetSpecialPCIRegRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
index 99bf9bd..75090b4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c
index d29ec7b..d62c75f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c
index dafff2d..f5d3027 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c
@@ -97,7 +97,7 @@ extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -140,7 +140,7 @@ MemNInitNBDataNb (
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -222,7 +222,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -248,7 +248,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -292,7 +292,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -313,7 +313,7 @@ MemNTrainingFlowNb (
return TRUE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -335,7 +335,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -486,7 +486,7 @@ MemNInsDlyCompareTestPatternNb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow for UNB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c
index aa1b6f5..43505c9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c
@@ -105,7 +105,7 @@ MemNS3GetDummyReadAddr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -214,7 +214,7 @@ MemNS3ResumeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -266,7 +266,7 @@ MemNS3ResumeClientNb (
// Errata After S3 resume sequence
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -320,7 +320,7 @@ MemNS3ResumeUNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -415,7 +415,7 @@ MemNS3GetConPCIMaskNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -486,7 +486,7 @@ MemNS3GetConPCIMaskUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -532,7 +532,7 @@ MemNS3GetCSRNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -593,7 +593,7 @@ MemNS3SetCSRNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -616,7 +616,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -639,7 +639,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -663,7 +663,7 @@ MemNS3RestoreScrubNb (
MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -693,7 +693,7 @@ MemNS3DisNbPsDbgNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -724,7 +724,7 @@ MemNS3EnNbPsDbg1Nb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -752,7 +752,7 @@ MemNS3SetDynModeChangeNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -800,7 +800,7 @@ MemNS3DisableChannelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -827,7 +827,7 @@ MemNS3SetDisAutoCompUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -854,7 +854,7 @@ MemNS3SetPreDriverCalUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -880,7 +880,7 @@ MemNS3DctCfgSelectUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -928,7 +928,7 @@ MemNS3GetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -976,7 +976,7 @@ MemNS3SetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1016,7 +1016,7 @@ MemNS3SaveNBRegiserUnb (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1061,7 +1061,7 @@ MemNS3RestoreNBRegiserUnb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1144,7 +1144,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1253,7 +1253,7 @@ MemNS3GetDummyReadAddr (
return AddrFound;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1287,7 +1287,7 @@ MemNS3SetMemClkFreqValUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1327,7 +1327,7 @@ MemNS3ChangeMemPStateContextNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
index 666e7fd..f8554f8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
@@ -121,7 +121,7 @@ MemNQuarterMemClk2NClkNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -360,7 +360,7 @@ MemNPlatformSpecNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -440,7 +440,7 @@ MemNPlatformSpecUnb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -467,7 +467,7 @@ MemNDisableDCTNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -500,7 +500,7 @@ MemNDisableDCTClientNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -535,7 +535,7 @@ MemNDisableDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -573,7 +573,7 @@ MemNStartupDCTNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -653,7 +653,7 @@ MemNStartupDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemNChangeFrequencyHy:
@@ -791,7 +791,7 @@ MemNChangeFrequencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency the next level if it have not reached
@@ -854,7 +854,7 @@ MemNRampUpFrequencyNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency to target frequency
@@ -893,7 +893,7 @@ MemNRampUpFrequencyUnb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1006,7 +1006,7 @@ MemNProgramCycTimingsNb (
MemNSetBitFieldNb (NBPtr, BFASR, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1114,7 +1114,7 @@ MemNProgramCycTimingsClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1221,7 +1221,7 @@ MemNProgramCycTimingsUnb (
MemNSetBitFieldNb (NBPtr, BFTzqoper, MIN (0xC, (MAX (256, MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 320)) + 31) / 32));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1249,7 +1249,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1283,7 +1283,7 @@ MemNGetMaxLatParamsNb (
*DlyBiasPtr += 1; // add 1 NCLK
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1343,7 +1343,7 @@ MemNSetMaxLatencyNb (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1378,7 +1378,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1408,7 +1408,7 @@ MemNAfterStitchMemNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1430,7 +1430,7 @@ MemNGet1KTFawTkNb (
return Tab1KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1452,7 +1452,7 @@ MemNGet2KTFawTkNb (
return Tab2KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1482,7 +1482,7 @@ MemNQuarterMemClk2NClkNb (
*SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1528,7 +1528,7 @@ MemNTotalSyncComponentsNb (
return SubTotal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1556,7 +1556,7 @@ MemNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1605,7 +1605,7 @@ MemNSwapBitsUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -1691,7 +1691,7 @@ MemNProgramPlatformSpecNb (
MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1731,7 +1731,7 @@ MemNGetTrdrdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1766,7 +1766,7 @@ MemNGetTwrwrNb (
return DCTPtr->Timings.Twrwr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1811,7 +1811,7 @@ MemNGetTwrrdNb (
return DCTPtr->Timings.Twrrd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1852,7 +1852,7 @@ MemNGetTrwtTONb (
return DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1876,7 +1876,7 @@ MemNGetTrwtWBNb (
return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1896,7 +1896,7 @@ MemNGetMemClkFreqIdNb (
return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1937,7 +1937,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1957,7 +1957,7 @@ MemNGetMemClkFreqIdClientNb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1977,7 +1977,7 @@ MemNGetMemClkFreqIdUnb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2005,7 +2005,7 @@ MemNGetMemClkFreqUnb (
return MemClkFreq;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2150,7 +2150,7 @@ MemNChangeFrequencyClientNb (
MemFInitTableDrive (NBPtr, MTAfterFreqChg);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2304,7 +2304,7 @@ MemNChangeFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -2352,7 +2352,7 @@ MemNProgramNbPstateDependentRegistersUnb (
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
@@ -2503,7 +2503,7 @@ MemNProgramNbPstateDependentRegistersClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2580,7 +2580,7 @@ MemNTotalSyncComponentsClientNb (
return (((P * MemClkPeriod + 1) / 2) + T);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2622,7 +2622,7 @@ MemNPhyPowerSavingClientNb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2693,7 +2693,7 @@ MemNPhyPowerSavingUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2735,7 +2735,7 @@ MemNSetASRSRTNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency as below:
@@ -2840,7 +2840,7 @@ MemNBeforePhyFenceTrainingClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency foras below:
@@ -2908,7 +2908,7 @@ MemNChangeNbFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2936,7 +2936,7 @@ MemNGetDramTermNb (
return DramTerm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2959,7 +2959,7 @@ MemNGetDramTermTblDrvNb (
return RttNom;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2979,7 +2979,7 @@ MemNGetDynDramTermNb (
return (NBPtr->PsPtr->DynamicDramTerm);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3002,7 +3002,7 @@ MemNGetDynDramTermTblDrvNb (
return RttWr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3026,7 +3026,7 @@ MemNGetMR0CLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3048,7 +3048,7 @@ MemNGetMR0WRNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3066,7 +3066,7 @@ MemNGetMR0WRTblDrvNb (
return (UINT32) (NBPtr->PsPtr->MR0WR << 9);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3088,7 +3088,7 @@ MemNGetMR2CWLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns MR2[CWL] value for UNB
@@ -3109,7 +3109,7 @@ MemNGetMR2CWLUnb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets Txp and Txpdll
@@ -3175,7 +3175,7 @@ MemNAdjustTxpdllClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to handle or switch NB Pstate for UNB
@@ -3285,7 +3285,7 @@ MemNChangeNbFrequencyWrapUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3315,7 +3315,7 @@ MemNSendMrsCmdUnb (
MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3333,7 +3333,7 @@ MemNGetMR0CLTblDrvNb (
return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3391,7 +3391,7 @@ MemNSlot1MaxRdLatTrainClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3432,7 +3432,7 @@ MemNDramPowerMngTimingNb (
MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3] - 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets Rcv Fifo
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c
index 0a58085..9263af6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c
@@ -228,7 +228,7 @@ MemNInitCPGUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -246,7 +246,7 @@ MemNInitCPGNb (
NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions of HW Rx En Training.
@@ -262,7 +262,7 @@ MemNInitDqsTrainRcvrEnHwNb (
{
NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables member functions of Hw Rx En Training.
@@ -285,7 +285,7 @@ MemNDisableDqsTrainRcvrEnHwNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes 9 or 18 cache lines continuously using GH CPG engine
@@ -334,7 +334,7 @@ MemNContWritePatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -426,7 +426,7 @@ MemNContReadPatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -452,7 +452,7 @@ MemNGenHwRcvEnReadsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes cache lines continuously using TCB CPG engine
@@ -529,7 +529,7 @@ MemNContWritePatternClientNb (
MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -585,7 +585,7 @@ MemNContReadPatternClientNb (
MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -610,7 +610,7 @@ MemNGenHwRcvEnReadsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -633,7 +633,7 @@ MemNInitCPGClientNb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -659,7 +659,7 @@ MemNCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -684,7 +684,7 @@ MemNInsDlyCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -802,7 +802,7 @@ MemNPrepareRcvrEnDlySeedNb (
NBPtr->FamilySpecificHook[RegAccessFence] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of MEMCLKs
@@ -820,7 +820,7 @@ MemNWaitXMemClksNb (
MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Issues dummy TCB write read to zero out CL that is used for MemClr
@@ -848,7 +848,7 @@ MemNBeforeMemClrClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Activate command
@@ -882,7 +882,7 @@ MemNRrwActivateCmd (
NBPtr->WaitXMemClks (NBPtr, 75);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Precharge
@@ -922,7 +922,7 @@ MemNRrwPrechargeCmd (
// Wait 25 MEMCLKs
NBPtr->WaitXMemClks (NBPtr, 25);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -948,7 +948,7 @@ MemNGenHwRcvEnReadsUnb (
NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of reads from DRAM using the
@@ -1063,7 +1063,7 @@ MemNContReadPatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1163,7 +1163,7 @@ MemNContWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results
@@ -1222,7 +1222,7 @@ MemNCompareTestPatternUnb (
return Pass;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for offset comparison results
@@ -1264,7 +1264,7 @@ MemNInsDlyCompareTestPatternUnb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -1290,7 +1290,7 @@ MemNInitCPGUnb (
NBPtr->DisableInfiniteWritePattern = MemNDisableInfiniteWritePatternUnb;
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes infinite writes to DRAM using the
@@ -1389,7 +1389,7 @@ MemNEnableInfiniteWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables the infinite stream of writes to DRAM using the
@@ -1439,7 +1439,7 @@ MemNDisableInfiniteWritePatternUnb (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the 180 Error status bits for RD DQS training
@@ -1463,7 +1463,7 @@ MemN180CompareRdDqs__PatternUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the In Phase Error status bits for comparison results for RDDQS training
@@ -1486,7 +1486,7 @@ MemNInPhaseCompareRdDqs__PatternUnb (
{
return NBPtr->GetBitField (NBPtr, BFNibbleErrSts);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function starts the Victim for RdDqs Training Continuous Writes
@@ -1526,7 +1526,7 @@ MemNStartRdDqs__VictimContinuousWritesUnb (
//}
NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim chipSelects for RdDqs Training Continuous Writes
@@ -1542,7 +1542,7 @@ MemNInitializeRdDqs__VictimChipSelContinuousWritesUnb (
NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, NBPtr->TechPtr->ChipSel);
NBPtr->SetBitField (NBPtr, BFResetAllErr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the Victim for RdDqs Training
@@ -1570,7 +1570,7 @@ MemNFinalizeRdDqs__VictimContinuousWritesUnb (
// Turn Off the RRW Engine
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim for RdDqs Training
@@ -1634,7 +1634,7 @@ MemNInitializeRdDqs__VictimContinuousWritesUnb (
}
NBPtr->SetBitField (NBPtr, BFReserved003, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables continuous writes on unused channels
@@ -1658,7 +1658,7 @@ MemNGetPrbs__RdDqsSeedUnb (
return PrbsSeed;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables/disables continuous writes on unused agressor channels
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c
index c2ec011..6c7526a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c
@@ -109,7 +109,7 @@ MemNGetPORFreqLimitTblDrvNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -171,7 +171,7 @@ MemNInitMCTNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -201,7 +201,7 @@ MemNPlatformSpecificFormFactorInitTblDrvNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
@@ -234,7 +234,7 @@ MemNTechBlockSwitchNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -283,7 +283,7 @@ MemNInitDCTNb (
return FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
@@ -304,7 +304,7 @@ MemNCleanupDctRegsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c
index 378575e..5c0a764 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c
@@ -104,7 +104,7 @@ MemNSetMTRRrangeNb (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -242,7 +242,7 @@ MemNSyncTargetSpeedNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -272,7 +272,7 @@ MemNSyncDctsReadyNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -408,7 +408,7 @@ MemNHtMemMapInitNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -454,7 +454,7 @@ MemNSyncAddrMapToAllNodesNb (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -485,7 +485,7 @@ MemNPowerDownCtlNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -551,7 +551,7 @@ MemNGetOptimalCGDDNb (
return CGDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -614,7 +614,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -689,7 +689,7 @@ GetTrainDlyFromHeapNb (
return TrainDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -805,7 +805,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -866,7 +866,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -961,7 +961,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1021,7 +1021,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1039,7 +1039,7 @@ MemNGetUmaSizeNb (
return 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1073,7 +1073,7 @@ MemNAllocateC6StorageClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1143,7 +1143,7 @@ MemNAllocateC6StorageUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function readjusts TOPMEM and MTRRs after allocating storage for C6
@@ -1194,7 +1194,7 @@ MemNC6AdjustMSRs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Family-specific hook to override the DdrMaxRate value for families with a
@@ -1224,7 +1224,7 @@ MemNGetMaxDdrRateUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1249,7 +1249,7 @@ MemNAfterSaveRestoreUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c
index 532c040..c02b804 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c
@@ -102,7 +102,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -126,7 +126,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -169,7 +169,7 @@ MemNPhyFenceTrainingNb (
NBPtr->MemPPhyFenceTrainingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -277,7 +277,7 @@ MemNPhyFenceTrainingUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -357,7 +357,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -441,7 +441,7 @@ MemNInitPhyCompNb (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -495,7 +495,7 @@ MemNBeforeDQSTrainingNb (
MemTEndTraining (NBPtr->TechPtr);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -531,7 +531,7 @@ MemNGetTrainDlyParmsNb (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -561,7 +561,7 @@ MemNGetTrainDlyParmsClientNb (
Parms->Mask = 0x03E;
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -593,7 +593,7 @@ MemNGetTrainDlyParmsUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -737,7 +737,7 @@ MemNcmnGetSetTrainDlyNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -859,7 +859,7 @@ MemNcmnGetSetTrainDlyClientNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1030,7 +1030,7 @@ MemNcmnGetSetTrainDlyUnb (
}
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -1117,7 +1117,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determined the settings for the Reliable Read/Write engine
@@ -1182,7 +1182,7 @@ MemNSetupHwTrainingEngineUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1210,7 +1210,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1236,7 +1236,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of chipselects per channel.
@@ -1254,7 +1254,7 @@ MemNCSPerChannelNb (
return MAX_CS_PER_CHANNEL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -1273,7 +1273,7 @@ MemNCSPerDelayNb (
return MAX_CS_PER_DELAY;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -1316,7 +1316,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -1356,7 +1356,7 @@ MemNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1375,7 +1375,7 @@ MemNPFenceAdjustUnb (
*Value16 += 2; //The Avg PRE value is subtracted by 6 only.
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1663,7 +1663,7 @@ MemNSetSkewMemClkUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function masks the RdDqsDly Bit 0 before writing to register for UNB.
@@ -1683,7 +1683,7 @@ MemNAdjustRdDqsDlyOffsetUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1765,7 +1765,7 @@ MemNCalcWrDqDqsEarlyClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1857,7 +1857,7 @@ MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1995,7 +1995,7 @@ MemNPhyPowerSavingMPstateUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets RxFifo pointer during Read DQS training
@@ -2019,7 +2019,7 @@ MemNResetRxFifoPtrClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* This function adjusts the Phase Mask based on ECC.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c
index cbf2dc78..cf2f4fc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -124,7 +124,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -156,7 +156,7 @@ MemNDctCfgSelectUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -179,7 +179,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -204,7 +204,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -227,7 +227,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -264,7 +264,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -294,7 +294,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -314,7 +314,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
@@ -470,7 +470,7 @@ MemNPollBitFieldNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -510,7 +510,7 @@ MemNChangeMemPStateContextNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates buffer for NB register table
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c
index 92d500d..0cb58a5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c
index d124619..3c83e9d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c
@@ -95,7 +95,7 @@ MemNHwWlPart2Nb (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -128,7 +128,7 @@ MemNDQSTiming3Nb (
}
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
@@ -201,7 +201,7 @@ memNSequenceDDR3Nb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c
index 802a48e..862189d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c
@@ -167,7 +167,7 @@ STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
@@ -204,7 +204,7 @@ MemPConstructPsRC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 C32 DDR3
@@ -261,7 +261,7 @@ MemPDoPsRC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 C32 DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c
index 2dbc362..f9c32ae 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c
@@ -102,7 +102,7 @@ STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
@@ -139,7 +139,7 @@ MemPConstructPsUC32_3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 C32 DDR3
@@ -164,7 +164,7 @@ MemPDoPsUC32_3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 C32
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
index a3d90b8..92c8c2c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
@@ -95,7 +95,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
{DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
{DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR2
@@ -133,7 +133,7 @@ MemPConstructPsSDA2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c
index 96cc3b9..94e1979 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c
@@ -108,7 +108,7 @@ STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM DA DDR3
@@ -146,7 +146,7 @@ MemPConstructPsSDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM DA DDR3
@@ -195,7 +195,7 @@ MemPDoPsSDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c
index 4292142..1705c75 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
@@ -141,7 +141,7 @@ MemPConstructPsUDA3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DA DDR3
@@ -166,7 +166,7 @@ MemPDoPsUDA3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 DA
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
index 7b2d67f..65420e3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
@@ -100,7 +100,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
@@ -138,7 +138,7 @@ MemPConstructPsRDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
index 0ae2a7c..dcc0bb2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
@@ -115,7 +115,7 @@ STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
{DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
{DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
@@ -153,7 +153,7 @@ MemPConstructPsRDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
index 215072c..3f7ad0d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
@@ -140,7 +140,7 @@ MemPConstructPsSDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
index 9359e5c..d06ff36 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
@@ -100,7 +100,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
{DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
@@ -138,7 +138,7 @@ MemPConstructPsUDr2 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR2 DR DDR2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
index 84007fe..b8921b4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
@@ -96,7 +96,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
@@ -133,7 +133,7 @@ MemPConstructPsUDr3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 DR DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c
index 24d4384..60d67be 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c
@@ -166,7 +166,7 @@ STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
{SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
@@ -204,7 +204,7 @@ MemPConstructPsRHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for R-DDR3 HY DDR3
@@ -260,7 +260,7 @@ MemPDoPsRHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for R-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c
index 1059541..4c675f5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c
@@ -108,7 +108,7 @@ STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
@@ -145,7 +145,7 @@ MemPConstructPsSHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for S-DDR3 HY DDR3
@@ -194,7 +194,7 @@ MemPDoPsSHy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c
index 1aa9358..8bebc4f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c
@@ -103,7 +103,7 @@ STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
@@ -140,7 +140,7 @@ MemPConstructPsUHy3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 HY DDR3
@@ -165,7 +165,7 @@ MemPDoPsUhy3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 HY
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c
index c7bdbe2..10abb89 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c
@@ -109,7 +109,7 @@ STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM Ph DDR3
@@ -147,7 +147,7 @@ MemPConstructPsSPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM Ph DDR3
@@ -196,7 +196,7 @@ MemPDoPsSPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c
index 76b97bf..1f23577 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3
@@ -142,7 +142,7 @@ MemPConstructPsUPh3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 Ph DDR3
@@ -167,7 +167,7 @@ MemPDoPsUPh3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 Ph
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c
index c84e505..61fa813 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c
@@ -109,7 +109,7 @@ STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = {
{DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor the platform specific settings for SO-DIMM RB DDR3
@@ -147,7 +147,7 @@ MemPConstructPsSRb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for SO-DIMM RB DDR3
@@ -196,7 +196,7 @@ MemPDoPsSRb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for SO-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c
index d461c1e..d8503c6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c
@@ -104,7 +104,7 @@ STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
{DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
{DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
@@ -142,7 +142,7 @@ MemPConstructPsURb3 (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for U-DDR3 RB DDR3
@@ -167,7 +167,7 @@ MemPDoPsURb3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function gets the POR speed limit for U-DDR3 RB
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
index 9225069..31cf7fa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
@@ -168,7 +168,7 @@ MemPTblDrvOverrideMR10OpSpeed (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -192,7 +192,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -240,7 +240,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -296,7 +296,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
@@ -313,7 +313,7 @@ MemPGetPORFreqLimitDef (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the seed value of WL and HW RxEn pass 1 training.
@@ -347,7 +347,7 @@ MemPGetPSCPass1Seed (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -402,7 +402,7 @@ MemPPSCFlow (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -454,7 +454,7 @@ MemPConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -490,7 +490,7 @@ MemPIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -535,7 +535,7 @@ MemPGetPsRankType (
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs the action for the rest of platform specific configuration such as
@@ -633,7 +633,7 @@ MemPPSCGen (
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function proceeds Table Driven Overriding.
@@ -865,7 +865,7 @@ MemPProceedTblDrvOverride (
return RetVal16;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the speed limit.
@@ -893,7 +893,7 @@ MemPTblDrvOverrideSpeedLimit (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODTs (RttNom and RttWr).
@@ -941,7 +941,7 @@ MemPTblDrvOverrideODT (
return TgtCS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODT patterns.
@@ -981,7 +981,7 @@ MemPTblDrvOverrideODTPattern (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the Ctrl Word 2 and 8.
@@ -1025,7 +1025,7 @@ MemPTblDrvOverrideRC2IBT (
return TgtDimm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1055,7 +1055,7 @@ MemPTblDrvOverrideMR0WR (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1083,7 +1083,7 @@ MemPTblDrvOverrideMR0CL (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR10[OperatingSpeed].
@@ -1116,7 +1116,7 @@ MemPTblDrvOverrideMR10OpSpeed (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
@@ -1158,7 +1158,7 @@ MemPCheckTblDrvOverrideConfig (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c
index a8e43e3..4b956bb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c
@@ -97,7 +97,7 @@ MemPGetLRIBT (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c
index ed14c16..debe3ff 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c
@@ -94,7 +94,7 @@ MemPGetLRNLR (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c
index bef6eba..ac90201 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c
@@ -94,7 +94,7 @@ MemPGetLRNPR (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c
index 4c93c10..62bb482 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c
@@ -110,7 +110,7 @@ MemPGetMaxFreqSupported (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts the value of max frequency supported from a input table and
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c
index b9ce51d..cc40b90 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c
@@ -92,7 +92,7 @@ MemPGetMR0WrCL (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c
index ec00177..330faf9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c
@@ -97,7 +97,7 @@ MemPGetODTPattern (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c
index 662e99e..72a0847 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c
@@ -95,7 +95,7 @@ MemPGetRC10OpSpd (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC10 operating speed value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c
index ee67710..76853cf 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c
@@ -96,7 +96,7 @@ MemPGetRC2IBT (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c
index 73bb817..e282c42 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c
@@ -99,7 +99,7 @@ MemPGetRttNomWr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c
index 5d762a9..772e8b7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c
@@ -98,7 +98,7 @@ MemPGetS__ (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which determine if training should be run
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c
index b8cf2d9..609c7aa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c
@@ -98,7 +98,7 @@ MemPGetSAO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c
index c5450f1..6bc9eb1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c
@@ -98,7 +98,7 @@ MemPGetTrainingSeeds (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function extracts WL and HW RxEn seeds from PSCFG tables
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
index f2a5bc4..ccca1a6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
@@ -95,7 +95,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
index 8d4503b..902fc60 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR2.
@@ -111,7 +111,7 @@ MemTAdjustTwrwr2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR2.
@@ -136,7 +136,7 @@ MemTAdjustTwrrd2 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c
index b75f927..8dba68c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c
@@ -132,7 +132,7 @@ MemTGetBankAddr2 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -151,7 +151,7 @@ MemTSetDramMode2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -385,7 +385,7 @@ MemTDIMMPresence2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
@@ -501,7 +501,7 @@ MemTSPDGetTargetSpeed2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -585,7 +585,7 @@ MemTSPDCalcWidth2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -772,7 +772,7 @@ MemTAutoCycTiming2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -888,7 +888,7 @@ MemTSPDSetBanks2 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -920,7 +920,7 @@ MemTGetCSIntLvAddr2 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency.
@@ -938,7 +938,7 @@ MemTSPDGetTCL2 (
return TechPtr->NBPtr->DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -970,7 +970,7 @@ MemTSysCapability2 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine whether dimm(b,i) supports CL(j) and F(k)
@@ -1028,7 +1028,7 @@ MemTDimmSupports2 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the cycle time
@@ -1049,7 +1049,7 @@ MemTGetTk2 (
return TableTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1075,7 +1075,7 @@ MemTGetBankAddr2 (
return TabBankAddr[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c
index ffe6b3e..aed389a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index 3ae45e6..ec4d4b2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -208,7 +208,7 @@ MemTLrdimmInitHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes LRDIMM functions.
@@ -239,7 +239,7 @@ MemTLrdimmConstructor3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a Control word command to an LRDIMM Memory Buffer
@@ -279,7 +279,7 @@ MemTSendMBCtlWord3 (
MemTSendCtlWord3 (TechPtr, Rcw, Value);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a an Extended Control word command to an LRDIMM Memory Buffer
@@ -349,7 +349,7 @@ MemTSendExtMBCtlWord3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the value of special RCW
@@ -523,7 +523,7 @@ MemTGetSpecialMBCtlWord3 (
return Value8;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -743,7 +743,7 @@ MemTLrDimmControlRegInit3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -849,7 +849,7 @@ MemTWLPrepareLrdimm3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to all physical ranks of an LRDIMM
@@ -941,7 +941,7 @@ MemTSendAllMRCmdsLR3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value for an LRDIMM
@@ -1006,7 +1006,7 @@ MemTEMRS1Lr3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value for an LRDIMM
@@ -1235,7 +1235,7 @@ MemTLrdimmBuf2DramTrain3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function copies trained delays of the first rank of a QR LRDIMM to the third rank
@@ -1315,7 +1315,7 @@ MemTLrdimmSyncTrainedDlys (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs LRDIMM specific tasks during Dimm Presence detection
@@ -1349,7 +1349,7 @@ MemTLrdimmPresence (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns LRDIMM Buffer ID Info from the SPD
@@ -1378,7 +1378,7 @@ MemTLrDimmGetBufferID (
return BufferID;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function implements special case Initialization hooks for LRDIMMs
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c
index a938de6..0eb607e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -113,7 +113,7 @@ MemTAdjustTwrwr3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -139,7 +139,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
index 79fef4d..b6604a1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -149,7 +149,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -224,7 +224,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -261,7 +261,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c
index 6ce9256..147f90d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -204,7 +204,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -328,7 +328,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -381,7 +381,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -409,7 +409,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -460,7 +460,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
index d61c065..f06fd8f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -114,7 +114,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -134,7 +134,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -445,7 +445,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -523,7 +523,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -601,7 +601,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -770,7 +770,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -917,7 +917,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -950,7 +950,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -993,7 +993,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1112,7 +1112,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1147,7 +1147,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c
index 2bc3f37..ec837b9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c
index f98956f..36b0ed5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -134,7 +134,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -154,7 +154,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -178,7 +178,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -206,7 +206,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -240,7 +240,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -294,7 +294,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -346,7 +346,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -393,7 +393,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -542,7 +542,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -672,7 +672,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c
index de4a32f..efe87dc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c
@@ -91,7 +91,7 @@ MemTDefaultTechnologyHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -106,7 +106,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -134,7 +134,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -168,7 +168,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -198,7 +198,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c
index 51081ed..e54b833 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
index d78a3fc..6af8510 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
@@ -171,7 +171,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -218,7 +218,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -371,7 +371,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -626,7 +626,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -691,7 +691,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -720,7 +720,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -790,7 +790,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -834,7 +834,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c
index 1339bf5..f68e196 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c
@@ -222,7 +222,7 @@ MemTFindMinMaxGrossDlyByte (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -345,7 +345,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -374,7 +374,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -400,7 +400,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -437,7 +437,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -496,7 +496,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -574,7 +574,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -633,7 +633,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -660,7 +660,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -692,7 +692,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -716,7 +716,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -731,7 +731,7 @@ MemTMaxByteLanesByte ( VOID )
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -746,7 +746,7 @@ MemTDlyTableWidthByte ( VOID )
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -784,7 +784,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -836,7 +836,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -908,7 +908,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -969,7 +969,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay for UNB
@@ -1030,7 +1030,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the minimum or maximum gross dly among all the bytes.
@@ -1074,7 +1074,7 @@ MemTFindMinMaxGrossDlyByte (
return MinMaxGrossDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1230,7 +1230,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1264,7 +1264,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1398,7 +1398,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c
index a85c76a..3e0629f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c
@@ -94,7 +94,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -143,7 +143,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c
index 512c4b5..d36350d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c
@@ -106,7 +106,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -127,7 +127,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -158,7 +158,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -243,7 +243,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
index 044e0bf..700d2df 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -163,7 +163,7 @@ MemTTrackRxEnSeedlessRdWrSmallWindBLError (
TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE;
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the RxEn delay
@@ -185,7 +185,7 @@ MemTRdPosRxEnSeedSetDly3 (
TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel >> 1), ByteLane), RcvEnDly);
TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the currert RxEn delay settings have failed
@@ -205,7 +205,7 @@ MemTRdPosRxEnSeedCheckRxEndly3 (
TechPtr->DqsRdWrPosSaved = 0;
MemTTrainDQSEdgeDetect (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training and if fails adjusts the RxEn Gross results for
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c
index 4b16faa..b3abd73 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c
index aac8bb0..1395876 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c
@@ -104,7 +104,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -129,7 +129,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
index 696c46e..de0ff54 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
@@ -97,7 +97,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -128,7 +128,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
index 7b9a86e..f133d18 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
@@ -161,7 +161,7 @@ TableName[BitFieldIndex] = ( \
#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
index 35ee2a4..c3dc87a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
@@ -74,7 +74,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the recovery entry point
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
index 2fdce7b..4801a32 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
@@ -61,7 +61,7 @@ AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get new Socket and Node Maps.
*
@@ -116,7 +116,7 @@ NewNodeAndSocketTablesRecovery (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c
index 9e8b4ef..011b982 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c
@@ -114,7 +114,7 @@ typedef struct {
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Routing Tables.
*
@@ -140,7 +140,7 @@ HtrEnableRoutingTables (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process the SouthBridge Link.
*
@@ -296,7 +296,7 @@ AmdHtResetConstructor (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize HT for Reset, Boot Blocks.
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c
index 0532373..dd3123f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c
@@ -149,7 +149,7 @@ STATIC CONST UINT32 RecModeDefRegArrayC32[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -277,7 +277,7 @@ MemRecConstructNBBlockC32 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -303,7 +303,7 @@ MemRecNSwitchNodeC32 (
MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -328,7 +328,7 @@ MemRecNSwitchDctC32 (
MemRecNSwitchChannelC32 (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -356,7 +356,7 @@ MemRecNSwitchChannelC32 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -486,7 +486,7 @@ MemRecNcmnGetSetTrainDlyC32 (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -594,7 +594,7 @@ MemRecNCmnGetSetFieldC32 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -697,7 +697,7 @@ MemRecNInitNBRegTableC32 (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedC32
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
index 0216cd8..f01ca04 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -123,7 +123,7 @@ MemRecNFinalizeMctC32 (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c
index 0b8c076..b4c27b3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c
@@ -140,7 +140,7 @@ STATIC CONST UINT32 RecModeDefRegArrayDA[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -265,7 +265,7 @@ MemRecConstructNBBlockDA (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -289,7 +289,7 @@ MemRecNSwitchDctDA (
MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -316,7 +316,7 @@ MemRecNSwitchChannelDA (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -431,7 +431,7 @@ MemRecNcmnGetSetTrainDlyDA (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -534,7 +534,7 @@ MemRecNCmnGetSetFieldDA (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -639,7 +639,7 @@ MemRecNInitNBRegTableDA (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDA
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c
index b4ff99e..0c35528 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -126,7 +126,7 @@ MemRecNFinalizeMctDA (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c
index 97942b1..33a9e58 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c
@@ -140,7 +140,7 @@ STATIC CONST UINT32 RecModeDefRegArrayDR[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -265,7 +265,7 @@ MemRecConstructNBBlockDR (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -290,7 +290,7 @@ MemRecNSwitchDctDR (
MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -317,7 +317,7 @@ MemRecNSwitchChannelDR (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -432,7 +432,7 @@ MemRecNcmnGetSetTrainDlyDR (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -535,7 +535,7 @@ MemRecNCmnGetSetFieldDR (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -641,7 +641,7 @@ MemRecNInitNBRegTableDR (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedDr
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
index fdb7871..077cf97 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -128,7 +128,7 @@ MemRecNFinalizeMctDR (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c
index 365b7de..b09a469 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c
@@ -148,7 +148,7 @@ STATIC CONST UINT32 RecModeDefRegArrayHy[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -276,7 +276,7 @@ MemRecConstructNBBlockHY (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -302,7 +302,7 @@ MemRecNSwitchNodeHy (
MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -327,7 +327,7 @@ MemRecNSwitchDctHy (
MemRecNSwitchChannelHy (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -355,7 +355,7 @@ MemRecNSwitchChannelHy (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -485,7 +485,7 @@ MemRecNcmnGetSetTrainDlyHy (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -593,7 +593,7 @@ MemRecNCmnGetSetFieldHy (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -697,7 +697,7 @@ MemRecNInitNBRegTableHy (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedHy
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
index eb9a246..2ed537f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets final values in BUCFG and BUCFG2
@@ -123,7 +123,7 @@ MemRecNFinalizeMctHy (
LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets initial values in BUCFG and BUCFG2
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c
index e12d273..901ba26 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -195,7 +195,7 @@ MemRecNPlatformSpecOr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -230,7 +230,7 @@ MemRecNSetDramOdtOr (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DRAM devices on all DCTs at the same time
@@ -266,7 +266,7 @@ MemRecNStartupDCTOr (
NBPtr->TechPtr->DramInit (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c
index fc09d17..6ef599f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G3_DXE)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for OR DDR3
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
index 8fcfc96..e346139 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
@@ -157,7 +157,7 @@ STATIC CONST UINT32 RecModeDefRegArrayOR[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -290,7 +290,7 @@ MemRecConstructNBBlockOr (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -316,7 +316,7 @@ MemRecNSwitchNodeOr (
MemRecNSwitchDctOr (NBPtr, NBPtr->Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -341,7 +341,7 @@ MemRecNSwitchDctOr (
MemRecNSwitchChannelOr (NBPtr, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -369,7 +369,7 @@ MemRecNSwitchChannelOr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -484,7 +484,7 @@ MemRecNcmnGetSetTrainDlyOr (
return value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -598,7 +598,7 @@ MemRecNCmnGetSetFieldOr (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -768,7 +768,7 @@ MemRecNInitNBRegTableOr (
MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2202, _NOT_USED_, _NOT_USED_, BFClock2TxPreDriverCalPad0);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedOr
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c
index 724469b..7040270 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c
@@ -141,7 +141,7 @@ STATIC CONST UINT32 RecModeDefRegArrayPh[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -266,7 +266,7 @@ MemRecConstructNBBlockPh (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -290,7 +290,7 @@ MemRecNSwitchDctPh (
MemRecNSwitchChannelPh (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -317,7 +317,7 @@ MemRecNSwitchChannelPh (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -432,7 +432,7 @@ MemRecNcmnGetSetTrainDlyPh (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -535,7 +535,7 @@ MemRecNCmnGetSetFieldPh (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -640,7 +640,7 @@ MemRecNInitNBRegTablePh (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedPh
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c
index 5a74186..9fe1074 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c
@@ -141,7 +141,7 @@ STATIC CONST UINT32 RecModeDefRegArrayRb[] = {
NULL
};
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the northbridge block
@@ -265,7 +265,7 @@ MemRecConstructNBBlockRb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current DCT to work on.
@@ -289,7 +289,7 @@ MemRecNSwitchDctRb (
MemRecNSwitchChannelRb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the current channel to work on.
@@ -316,7 +316,7 @@ MemRecNSwitchChannelRb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -431,7 +431,7 @@ MemRecNcmnGetSetTrainDlyRb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or sets a value to a bit field in a PCI register.
@@ -534,7 +534,7 @@ MemRecNCmnGetSetFieldRb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes bit field translation table
@@ -639,7 +639,7 @@ MemRecNInitNBRegTableRb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemRecNIsIdSupportedRb
* This function matches the CPU_LOGICAL_ID with certain criteria to
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
index 44abf5e..d15fa03 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
@@ -92,7 +92,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a bit field from PCI register
@@ -114,7 +114,7 @@ MemRecNGetBitFieldNb (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets a bit field from PCI register
@@ -135,7 +135,7 @@ MemRecNSetBitFieldNb (
NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
@@ -158,7 +158,7 @@ MemRecNGetTrainDlyNb (
return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets a delay value a PCI register during training
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
index 2333be7..2e497fa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
@@ -133,7 +133,7 @@ MemRecNCommonReadWritePatternUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller with configuration parameters
@@ -228,7 +228,7 @@ MemRecNAutoConfigNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific config/timing values from the interface layer and
@@ -260,7 +260,7 @@ MemRecNPlatformSpecNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function reads MemClkFreqVal bit to see if the DIMMs are present in this node.
@@ -305,7 +305,7 @@ MemRecNStartupDCTNb (
while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DRAM devices on all DCTs at the same time
@@ -348,7 +348,7 @@ MemRecNStartupDCTClientNb (
IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", DDR800_FREQUENCY);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the maximum round-trip latency in the system from the processor to the DRAM
@@ -416,7 +416,7 @@ MemRecNSetMaxLatencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set Dram ODT for mission mode and write leveling mode.
@@ -458,7 +458,7 @@ MemRecNSetDramOdtNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends an MRS command
@@ -508,7 +508,7 @@ MemRecNSendMrsCmdNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends the ZQCL command
@@ -536,7 +536,7 @@ MemRecNSendZQCmdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
@@ -568,7 +568,7 @@ MemRecTCtlOnDimmMirrorNb (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -597,7 +597,7 @@ MemRecNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -655,7 +655,7 @@ MemRecNTotalSyncComponentsClientNb (
return ((P * MemClkPeriod + 1) / 2) + T;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -685,7 +685,7 @@ MemRecNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -751,7 +751,7 @@ MemRecNTrainPhyFenceNb (
MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -854,7 +854,7 @@ MemRecNProgNbPstateDependentRegClientNb (
MemRecNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -899,7 +899,7 @@ MemRecNContReadPatternClientNb (
MemRecNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with UDIMMs configuration
@@ -984,7 +984,7 @@ MemRecNGetPsCfgUDIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with SODIMMs configuration
@@ -1072,7 +1072,7 @@ MemRecNGetPsCfgSODIMM3Nb (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is function sets the platform specific settings for the systems with RDIMMs configuration
@@ -1235,7 +1235,7 @@ MemRecNGetPsCfgRDIMM3Nb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1271,7 +1271,7 @@ RecGetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -1295,7 +1295,7 @@ MemRecNGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -1438,7 +1438,7 @@ MemRecNcmnGetSetTrainDlyClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1462,7 +1462,7 @@ MemRecNContReadPatternUnb (
MemRecNCommonReadWritePatternUnb (NBPtr, CMD_TYPE_READ, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1486,7 +1486,7 @@ MemRecNContWritePatternUnb (
MemRecNCommonReadWritePatternUnb (NBPtr, CMD_TYPE_WRITE, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates either read or write DRAM cycles for training
@@ -1539,7 +1539,7 @@ MemRecNCommonReadWritePatternUnb (
MemRecNSetBitFieldNb (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results using PRBS
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c
index 314c7f4..dafd2c2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c
@@ -88,7 +88,7 @@
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for Nb DDR3
@@ -149,7 +149,7 @@ MemRecNMemInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a physical address of a corresponding Chip select
@@ -170,7 +170,7 @@ MemRecNGetMCTSysAddrNb ( VOID )
return CSBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
@@ -235,7 +235,7 @@ MemRecNCPUMemRecTypingNb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
index e102af4..5e991f9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -81,7 +81,7 @@
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -101,7 +101,7 @@ MemNRecTrainingFlowNb (
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the client training control flow
@@ -136,7 +136,7 @@ MemNRecTrainingFlowClientNb (
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c
index fe60068..ef1a757 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -134,7 +134,7 @@ MemPRecPSCFlow (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -186,7 +186,7 @@ MemPRecConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -222,7 +222,7 @@ MemPRecIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c
index eb930ff..2e9b64c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c
index da47839..2bd6913 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c
index 10d4b4f..2b0c8fa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c
index 4f85158..73f9067 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c
index 9b6b2f6..6f10fbd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c
index 3206a05..cb5ea5d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c
index 6417deb..3218932 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c
index 0f4c77a..abd91bc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
index 756b7be..34420a7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
@@ -121,7 +121,7 @@ MemRecConstructTechBlock3 (
TechPtr->DimmPresence = MemRecTDIMMPresence3;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -152,7 +152,7 @@ MemRecTBeginTraining (
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
index ba5b494..63d07bb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
@@ -103,7 +103,7 @@ MemRecTSendCtlWord3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -147,7 +147,7 @@ MemRecTDramControlRegInit3 (
MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -196,7 +196,7 @@ MemRecTGetCtlWord3 (
return (Data&0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
index 9224d18..a5593de 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G2_PEI)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init
@@ -181,7 +181,7 @@ MemRecTDramInitSw3 (
IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -237,7 +237,7 @@ MemRecTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -284,7 +284,7 @@ MemRecTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -313,7 +313,7 @@ MemRecTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MSS value
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
index f656a53..4031a9b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G2_PEI)
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -112,7 +112,7 @@ MemRecTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
index f2ceb2c..14f7a75 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
@@ -110,7 +110,7 @@ MemRecTBeginWLTrain3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -177,7 +177,7 @@ MemRecTTrainDQSWriteHw3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -234,7 +234,7 @@ MemRecTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function configures the DIMMS for Write Levelization
@@ -305,7 +305,7 @@ MemRecTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
index 84e7ab6..2fcd092 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -105,7 +105,7 @@ MemRecTProgramRcvrEnDly (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -177,7 +177,7 @@ MemRecTTrainRcvrEnHw (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -271,7 +271,7 @@ MemRecTPrepareRcvrEnDlySeed (
);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
index 2e0f1a4..e014b1d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
@@ -105,7 +105,7 @@ MemRecTProgramRcvrEnDly (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training without
@@ -232,7 +232,7 @@ MemRecTTrainRcvrEnHwSeedless (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -260,7 +260,7 @@ MemRecTPrepareRcvrEnDlySeed (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
index 7f53991..c3c73f1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function hard-codes DQS position delays for all bytes
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c
index 2594ecb..06b21a6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c
@@ -123,7 +123,7 @@ MemRecTCompare1ClPattern (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for BSP
@@ -231,7 +231,7 @@ MemRecTTrainRcvrEnSw (
MemRecTEndTraining (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* If WrDatDly is 0, this function sets the DQS Positions in preparation
@@ -268,7 +268,7 @@ MemRecTSetWrDatRdDqs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -296,7 +296,7 @@ MemRecTSetRcvrEnDly (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -345,7 +345,7 @@ MemRecTCompare1ClPattern (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -399,7 +399,7 @@ MemRecTSaveRcvrEnDly (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
index 7d270ec..5bb36f0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -92,7 +92,7 @@ MemRecDefRet ( VOID )
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -105,7 +105,7 @@ MemRecDefTrue ( VOID )
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the DCT with initial values
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrinit.c
index d3bb5de..7f798f1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrinit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrinit.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
extern MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the default parameter, function pointers, build options
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrm.c
index 9b3ac90..5d607c6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrm.c
@@ -98,7 +98,7 @@ MemRecSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the Recovery memory configuration function for HY DDR3
@@ -202,7 +202,7 @@ AmdMemRecovery (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
index e385b26..bb38af1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
@@ -100,7 +100,7 @@ MemRecUSetTargetWTIO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (Index)th UINT8
@@ -126,7 +126,7 @@ MemRecUFillTrainPattern (
LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -153,7 +153,7 @@ MemRecUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -171,7 +171,7 @@ MemRecUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -198,7 +198,7 @@ MemRecUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // ;64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -222,7 +222,7 @@ MemRecUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h
index cb7e7f2..a893b1e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h
@@ -184,7 +184,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
index 873ed8b..84481dd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
@@ -80,7 +80,7 @@ BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
index f234cf4..cc7bf01 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
@@ -61,7 +61,7 @@ RDATA_GROUP (G1_PEICC)
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -127,7 +127,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
index 896476f..09bf265 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
@@ -80,7 +80,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -107,7 +107,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -132,7 +132,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -155,7 +155,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -180,7 +180,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -204,7 +204,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -228,7 +228,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -252,7 +252,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -276,7 +276,7 @@ AgesaHookBeforeDramInitRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -299,7 +299,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -322,7 +322,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -345,7 +345,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -371,7 +371,7 @@ AgesaGetIdsData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
@@ -393,7 +393,7 @@ AgesaPcieSlotResetControl (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get VBIOS image
*
@@ -415,7 +415,7 @@ AgesaGetVbiosImage (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* OEM callout function for FCH data override
*
@@ -432,7 +432,7 @@ AgesaFchOemCallout (
AGESA_STATUS Status; Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; //return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index ba51951..42f475d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -260,7 +260,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
index b3819be..30b39d5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
@@ -474,7 +474,7 @@ LibAmdFinit()
/* TODO: finit */
__asm__ volatile ("finit");
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -511,7 +511,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -548,7 +548,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -578,7 +578,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -611,7 +611,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -648,7 +648,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -685,7 +685,7 @@ LibAmdMemWrite (
ASSERT (FALSE);
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -715,7 +715,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -748,7 +748,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -799,7 +799,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -854,7 +854,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -884,7 +884,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -917,7 +917,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -952,7 +952,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -985,7 +985,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1025,7 +1025,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1099,7 +1099,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1125,7 +1125,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1153,7 +1153,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1189,7 +1189,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1239,7 +1239,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1261,7 +1261,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1304,7 +1304,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c
index e996349..7639fc8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* entry point for enabling High Performance Computing.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c
index 633c9c4..4ba876d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c
@@ -85,7 +85,7 @@ F15TnReloadMicrocodePatchAfterMemInit (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -112,7 +112,7 @@ F15TnIsC6Supported (
return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C6 on a family 15h CPU.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
index dea99a2..e761c7f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -107,7 +107,7 @@ F15TnIsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
index fa6434f..90905ff 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
@@ -90,7 +90,7 @@ STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] =
0x6100, 0x6900
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
index fd38c7a..12ed9a7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
@@ -118,7 +118,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15TnEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
@@ -142,7 +142,7 @@ GetF15TnEarlyInitOnCoreTable (
*Table = F15TnEarlyInitOnCoreTable;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor for Family15h TN.
*
@@ -173,7 +173,7 @@ F15TnLoadMicrocodePatchAtEarly (
ApplyWorkaroundForFchErratum39 (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Apply the workaround for FCH H2/H3 erratum #39.
*
@@ -224,7 +224,7 @@ ApplyWorkaroundForFchErratum39 (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Prevent NB P-state transitions prior to AP launch on Family 15h TN.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
index e036713..90da563 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
@@ -89,7 +89,7 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 15h Trinity CPU.
* Implement BIOS Requirements for Initialization of C-states
@@ -145,7 +145,7 @@ F15TnInitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 15h Trinity core.
*
@@ -164,7 +164,7 @@ F15TnInitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -208,7 +208,7 @@ F15TnGetAcpiCstObj (
return CStateAcpiObjSize;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -337,7 +337,7 @@ F15TnCreateAcpiCstObj (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
index 3293658..a493e19 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
@@ -81,7 +81,7 @@ GetF15TnMicroCodePatchesStruct (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
index 94ddac4..addb639 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
@@ -229,7 +229,7 @@ CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable = {
(TABLE_ENTRY_FIELDS *) F15TnMsrWorkarounds,
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* MSR special programming requirements for MSR_C001_1005
*
@@ -259,7 +259,7 @@ SetTopologyExtensions (
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* MSR special programming requirements for MSR_C001_102D
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
index 8150e2b..453d992 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
@@ -758,7 +758,7 @@ CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Non-A0 TN processors.
*
@@ -789,7 +789,7 @@ SetEnCstateBoostBlockCC6Exit (
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Erratum #687 for TN processors.
*
@@ -834,7 +834,7 @@ Erratum687Workaround (
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Erratum #712 for TN processors.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
index 0b45637..f845232 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
@@ -86,7 +86,7 @@ GetF15TnSysPmTable (
*/
/* Family 15h Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] =
{
IDS_INITIAL_F15_TN_PM_STEP
@@ -138,7 +138,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
index 52edf52..b9281b5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
@@ -94,7 +94,7 @@ STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] =
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h core 0 entry point for performing power plane initialization.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
index 47f3030..01e0e02 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
@@ -283,7 +283,7 @@ CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable = {
(TABLE_ENTRY_FIELDS *) &F15TnSharedMsrWorkarounds,
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update the FP_CFG MSR in current processor for Family15h TN.
*
@@ -343,7 +343,7 @@ CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for CPUs with a minimum P-state = 800MHz.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
index c54e1af..facce37 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
@@ -144,7 +144,7 @@ F15TnSetDownCoreRegister (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current.
*
@@ -194,7 +194,7 @@ F15TnGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on Trinity
*
@@ -271,7 +271,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -307,7 +307,7 @@ F15TnGetCurrentNbFrequency (
return ReturnCode;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -404,7 +404,7 @@ F15TnGetMinMaxNbFrequency (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -480,7 +480,7 @@ F15TnGetNbPstateInfo (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB pstate current.
*
@@ -531,7 +531,7 @@ F15TnGetNbIddMax (
return IsNbPsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
@@ -558,7 +558,7 @@ F15TnGetNumberOfPhysicalCores (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -588,7 +588,7 @@ F15TnGetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -614,7 +614,7 @@ F15TnGetApCoreNumber (
return ((Cpuid.EBX_Reg >> 24) & 0xFF);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -668,7 +668,7 @@ F15TnIsNbPstateEnabled (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state.
* - clear F5x1[6C:64]
@@ -796,7 +796,7 @@ F15TnNbPstateDis (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state on core.
* - clear MSRC001_00[6B:64][NbPstate].
@@ -825,7 +825,7 @@ F15TnNbPstateDisCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB Frequency Numerator in MHz
*
@@ -847,7 +847,7 @@ F15TnGetNbFreqNumeratorInMHz (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB Frequency Divisor
*
@@ -869,7 +869,7 @@ F15TnGetNbFreqDivisor (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate NB Frequency in MHz
*
@@ -905,7 +905,7 @@ F15TnCalculateNbFrequencyInMHz (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Convert VID to microvolts(uV)
*
@@ -928,7 +928,7 @@ F15TnCovertVidInuV (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Core/NB Idd Divisor
*
@@ -966,7 +966,7 @@ F15TnCmnGetIddDivisor (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate Core/NB current in mA
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
index 92563bf..58ccf0f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
@@ -100,7 +100,7 @@ SetF15TnCacheFlushOnHaltRegister (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
index 5140d9f..1ce89c3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
@@ -92,7 +92,7 @@ F15TnPmCoreAfterResetPhase2OnCore (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Trinity core 0 entry point for performing the necessary steps for core
* P-states after a warm reset has occurred.
@@ -159,7 +159,7 @@ F15TnPmCoreAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
* cores of a family 15h socket.
@@ -200,7 +200,7 @@ F15TnPmCoreAfterResetPhase1OnCore (
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
* cores of a family 15h socket.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
index 0cad269..39a4932 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
@@ -153,7 +153,7 @@ DmiF15TnGetExtClock (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15TnGetInfo
@@ -232,7 +232,7 @@ DmiF15TnGetInfo (
CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15TnGetT4ProcFamily
@@ -295,7 +295,7 @@ DmiF15TnGetT4ProcFamily (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15TnGetVoltage
@@ -337,7 +337,7 @@ DmiF15TnGetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15TnGetMemInfo
@@ -357,7 +357,7 @@ DmiF15TnGetMemInfo (
CpuGetMemInfoPtr->EccCapable = FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15TnGetExtClock
@@ -377,7 +377,7 @@ DmiF15TnGetExtClock (
return (EXTERNAL_CLOCK_100MHZ);
}
-/* -----------------------------------------------------------------------------*/
+
CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15TnDmiTable =
{
// This table is for Processor family 15h Trinity
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
index 398c8e5..7a7eba9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
@@ -90,7 +90,7 @@ F15TnHtcInit (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Hardware Thermal Control
*
@@ -125,7 +125,7 @@ F15TnInitializeHtc (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
index 52c6149..6f01810 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
@@ -109,7 +109,7 @@ WaitForNbTransitionToComplete (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Trinity core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -189,7 +189,7 @@ F15TnPmNbAfterReset (
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment
* after a cold reset has occurred.
@@ -288,7 +288,7 @@ F15TnNbPstateVidAdjustAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
@@ -362,7 +362,7 @@ F15TnPmNbAfterResetOnCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmNbAfterResetOnCore to transition to the low NB P-state.
*
@@ -396,7 +396,7 @@ TransitionToNbLow (
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmNbAfterResetOnCore to transition to the high NB P-state.
*
@@ -428,7 +428,7 @@ TransitionToNbHigh (
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F15TnPmAfterResetCore to wait for NB FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
index 4f9d358..94d5414 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
@@ -95,7 +95,7 @@ F15TnPmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h core 0 entry point for performing the family 15h Processor-
* Systemboard Power Delivery Check.
@@ -329,7 +329,7 @@ F15TnPmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -430,7 +430,7 @@ F15TnPmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
index cff39b5..7fef6ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
@@ -90,7 +90,7 @@ F15TnPmVrmLowPowerModeEnable (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Power Status Indicator
*
@@ -128,7 +128,7 @@ F15TnInitializePsi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
index 22f6ed3..b18d320 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
@@ -151,7 +151,7 @@ F15TnGetPstateRegisterInfo (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -207,7 +207,7 @@ F15TnSetTscFreqSel (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -318,7 +318,7 @@ F15TnGetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -379,7 +379,7 @@ F15TnGetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -444,7 +444,7 @@ F15TnGetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -490,7 +490,7 @@ F15TnGetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
@@ -650,7 +650,7 @@ F15TnGetPllValueInTime (
IDS_HDT_CONSOLE (CPU_TRACE, " PllLockTimePtr=%d\n", *PllLockTimePtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will return the CpuFid and CpuDid in MHz, using the formula
* described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
index b94f066..02af13f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -116,7 +116,7 @@ F15SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -148,7 +148,7 @@ F15GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c
index 5bce8ca..0c127da 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c
@@ -78,7 +78,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Application Power Management
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
index 56b65da..e620d2d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -113,7 +113,7 @@ CONST CPU_F15_EXCEPTION_BRAND ROMDATA CpuF15ExceptionBrandIdString[] =
{str_Exception_0}
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the Processor Name String register based on F5x194/198
*
@@ -189,7 +189,7 @@ F15SetBrandIdRegistersAtEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Check if it's an exception
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
index 712b5a4..12926ec 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -116,7 +116,7 @@ CONST CACHE_INFO ROMDATA CpuF15CacheInfoCP =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
index 02896f8..9c10811 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
@@ -77,7 +77,7 @@ extern CONST UINT8 ROMDATA L2L3Associativity[];
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* generate CRAT cache entry for F15 processor
@@ -216,7 +216,7 @@ F15GenerateCratCacheEntry (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* generate CRAT TLB entry for F15 processor
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c
index 1eb82f2..0a69767 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c
@@ -78,7 +78,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF15GetMaxSpeed
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
index 1fd3b2f..175842e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
@@ -79,7 +79,7 @@ STATIC CONST UINT16 ROMDATA MmioBaseLimitHiRegOffset[MMIO_REG_PAIR_NUM] = {0x180
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for adding MMIO map
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
index 9a2ec6a..6579033 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
@@ -93,7 +93,7 @@ F15PmPwrChkCopyPstate (
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 15h core 0 entry point for performing the family 15h Processor-
* Systemboard Power Delivery Check.
@@ -309,7 +309,7 @@ F15PmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -410,7 +410,7 @@ F15PmPwrCheckCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c
index 630ad5a..b403679 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c
@@ -160,7 +160,7 @@ CONST STATIC HT_PHY_DLL_COMP_LOOKUP_TABLE ROMDATA HtPhyDllCompLookupTable[] = {
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -188,7 +188,7 @@ F15DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -224,7 +224,7 @@ F15TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -267,7 +267,7 @@ F15GetTscRate (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -435,7 +435,7 @@ F15LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the features of the next HT link.
*
@@ -560,7 +560,7 @@ F15GetNextHtLinkFeatures (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks to see if the HT phy register table entry should be applied
*
@@ -786,7 +786,7 @@ F15NextLinkHasHtPhyFeats (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy read-modify-write based on an HT Phy register table entry.
*
@@ -853,7 +853,7 @@ F15SetHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Applies an HT Phy write to a specified Phy register.
*
@@ -913,7 +913,7 @@ F15WriteOnlyHtPhyRegister (
} while (!(Temp & HTPHY_IS_COMPLETE_MASK));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the value of an HT PHY register.
*
@@ -973,7 +973,7 @@ F15GetHtPhyRegister (
return Temp;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A Family Specific Workaround method, to override HT DLL Compensation.
*
@@ -1100,7 +1100,7 @@ F15HtPhyOverrideDllCompensation (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -1126,7 +1126,7 @@ F15CommonGetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
index 5239723..6516474 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
@@ -98,7 +98,7 @@ AMD_WHEA_INIT_DATA F15WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c
index 015dcad..0ff8d92 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c
@@ -82,7 +82,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The contents of the mailbox registers should always be preserved.
*
@@ -102,7 +102,7 @@ IsPreserveAroundMailboxEnabled (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c
index 0b72761..e30d5b0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c
@@ -81,7 +81,7 @@ EnableApmOnSocket (
*/
extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Application Power Management (APM) be enabled
*
@@ -119,7 +119,7 @@ IsApmFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Application Power Management (APM)
*
@@ -168,7 +168,7 @@ InitializeApmFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable APM
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h
index 1964cef..d667d4d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Application Power Management (APM) is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_APM_IS_SUPPORTED (
/// Reference to a Method.
typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable APM.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c
index 96690a2..a8999f5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c
@@ -89,7 +89,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -127,7 +127,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -202,7 +202,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
@@ -231,7 +231,7 @@ EnableC6OnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h
index 01e65d5..24ac2fc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
@@ -104,7 +104,7 @@ typedef AGESA_STATUS F_C6_INIT (
/// Reference to a Method.
typedef F_C6_INIT *PF_C6_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to reload microcode patch after memory is initialized.
*
@@ -133,7 +133,7 @@ struct _C6_FAMILY_SERVICES {
PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index f2c2dec..3267bd3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -107,7 +107,7 @@ InitializeCacheFlushOnHaltFeature (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -127,7 +127,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
@@ -164,7 +164,7 @@ InitializeCacheFlushOnHaltFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
index fcd7bf4..e9eb5fb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
@@ -142,7 +142,7 @@ IsPowerOfTwo (
IN UINT32 TestNumber
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -428,7 +428,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -521,7 +521,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -546,7 +546,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
@@ -594,7 +594,7 @@ CalculateOccupiedExeCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function compares two memory regions for overlap and returns the combined
* Base,Size to describe the new combined region.
@@ -722,7 +722,7 @@ CompareRegions (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This local function tests the parameter for being an even power of two
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
index 65af6f7..7e7c0a3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
@@ -123,7 +123,7 @@ GetAcpiCditMain (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete CDIT table into a memory buffer.
@@ -147,7 +147,7 @@ CreateAcpiCdit (
return ((*(OptionCditConfiguration.CditFeature)) (StdHeader, PlatformConfig, CditPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the CDIT option is NOT requested.
@@ -172,7 +172,7 @@ GetAcpiCditStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete CDIT table into a memory buffer.
@@ -308,7 +308,7 @@ GetAcpiCditMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
index 72100de..8d27f0a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -98,7 +98,7 @@ CoreLevelingAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -126,7 +126,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c
index 29a3cfe..bac817b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should CPB be enabled
*
@@ -115,7 +115,7 @@ IsCpbFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable core performance boost
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h
index ad24e97..3114e57 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if CPB is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_CPB_IS_SUPPORTED (
/// Reference to a Method.
typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable CPB.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
index 71f685b..c7bffbe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
@@ -141,7 +141,7 @@ STATIC CRAT_HEADER ROMDATA CratHeaderStruct =
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Component Resource Affinity Table
@@ -164,7 +164,7 @@ CreateAcpiCrat (
return ((*(OptionCratConfiguration.CratFeature)) (StdHeader, CratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the CRAT option is NOT requested.
@@ -187,7 +187,7 @@ GetAcpiCratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Component Resource Affinity Table
@@ -251,7 +251,7 @@ GetAcpiCratMain (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add HSA Processing Unit entry.
*
@@ -307,7 +307,7 @@ MakeHSAProcUnitEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add memory entry.
*
@@ -383,7 +383,7 @@ MakeMemoryEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add cache entry.
*
@@ -406,7 +406,7 @@ MakeCacheEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add TLB entry.
*
@@ -429,7 +429,7 @@ MakeTLBEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add CRAT entry.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
index 5c80317..ab43970 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
@@ -117,7 +117,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -144,7 +144,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -170,7 +170,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -406,7 +406,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -584,7 +584,7 @@ GetType4Type7Info (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* DmiGetT4ProcFamilyFromBrandId
*
@@ -623,7 +623,7 @@ DmiGetT4ProcFamilyFromBrandId (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetNameString
@@ -658,7 +658,7 @@ GetNameString (
String[StringIndex] = '\0';
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IsSourceStrContainTargetStr
@@ -715,7 +715,7 @@ IsSourceStrContainTargetStr (
return IsContained;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -750,7 +750,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -771,7 +771,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -794,7 +794,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
index 27ba72d..8653a4a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -111,7 +111,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -187,7 +187,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -212,7 +212,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -237,7 +237,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h
index 2c94a42..bbb9623 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h
@@ -182,7 +182,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -201,7 +201,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c
index f8f3b93..0be9d61 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c
@@ -84,7 +84,7 @@ EnableHtcOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE HtcFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Hardware Thermal Control (HTC) be enabled
*
@@ -121,7 +121,7 @@ IsHtcFeatureEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware Thermal Control (HTC)
*
@@ -160,7 +160,7 @@ InitializeHtcFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable HTC
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h
index a17ee39..e99befe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (HTC_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Hardware Thermal Control (HTC) is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_HTC_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HTC_IS_SUPPORTED *PF_HTC_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable HTC.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c
index 19de2cc..5da2adf 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should hardware C1e be enabled
*
@@ -130,7 +130,7 @@ IsHwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware C1e
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h
index d662052..8d9b03b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if hardware C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c
index 1cf61b2..96bd68d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c
@@ -85,7 +85,7 @@ EnableIoCstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should IO Cstate be enabled
* If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
@@ -132,7 +132,7 @@ IsIoCstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate feature
*
@@ -168,7 +168,7 @@ InitializeIoCstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable IO Cstate on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h
index 42c861e..e57da06 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h
@@ -166,7 +166,7 @@ typedef struct _ACPI_CST_GET_INPUT {
} ACPI_CST_GET_INPUT ;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if IO Cstate is supported.
*
@@ -184,7 +184,7 @@ typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable IO Cstate.
*
@@ -203,7 +203,7 @@ typedef AGESA_STATUS F_IO_CSTATE_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to return the size of ACPI C-State Objects
*
@@ -220,7 +220,7 @@ typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to create ACPI C-State Objects
*
@@ -237,7 +237,7 @@ typedef VOID F_IO_CSTATE_CREATE_CST (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c
index 963deb3..f6ab9d9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*/
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should L3 features be enabled
*
@@ -129,7 +129,7 @@ IsL3FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable L3 dependent features.
*
@@ -277,7 +277,7 @@ InitializeL3Feature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Disable all the caches on current core.
@@ -310,7 +310,7 @@ DisableAllCaches (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Enable all the caches on current core.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h
index e85cc65..de8fe3f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h
@@ -63,7 +63,7 @@ AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES);
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if L3 Features are supported.
*
@@ -84,7 +84,7 @@ typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before L3 features are initialized.
*
@@ -102,7 +102,7 @@ typedef VOID F_L3_FEATURE_BEFORE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -120,7 +120,7 @@ typedef VOID F_L3_FEATURE_DISABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -138,7 +138,7 @@ typedef VOID F_L3_FEATURE_ENABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize L3 Features
*
@@ -156,7 +156,7 @@ typedef VOID F_L3_FEATURE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook after L3 Features are initialized.
*
@@ -174,7 +174,7 @@ typedef VOID F_L3_FEATURE_AFTER_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -194,7 +194,7 @@ typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -214,7 +214,7 @@ typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -235,7 +235,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize HT Assist
*
@@ -253,7 +253,7 @@ typedef VOID F_HT_ASSIST_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to provide non_optimal HT Assist support
*
@@ -274,7 +274,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if ATM Mode is supported.
*
@@ -295,7 +295,7 @@ typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize ATM mode
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c
index 96b9adb..1978d60 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c
@@ -93,7 +93,7 @@ ProgramHtcPstateLimit (
*/
extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Low Power P-state be enabled
* If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
@@ -139,7 +139,7 @@ IsLowPwrPstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable low power P-state
*
@@ -211,7 +211,7 @@ InitializeLowPwrPstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* All APs task to enable low power P-state
*
@@ -234,7 +234,7 @@ EnableLowPwrPstateOnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable low power P-state
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h
index 4433db8..cb7bf8f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Low Power P-state is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable Low Power P-state
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c
index 5a2e0fe..5a196b8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -86,7 +86,7 @@ EnableMsgC1eOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should message-based C1e be enabled
*
@@ -134,7 +134,7 @@ IsMsgBasedC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Message-based C1e
*
@@ -172,7 +172,7 @@ InitializeMsgBasedC1eFeature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable message-based C1e on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h
index c7e186f..ca7f77e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c
index 08cc370..245a619 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c
@@ -84,7 +84,7 @@ EnablePsiOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE PsiFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Power Status Indicator (PSI) be enabled
*
@@ -133,7 +133,7 @@ IsPsiFeatureEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Power Status Indicator (PSI)
*
@@ -172,7 +172,7 @@ InitializePsiFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable PSI
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h
index 91c405b..1e2e479 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (PSI_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Power Status Indicator (PSI) is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_PSI_IS_SUPPORTED (
/// Reference to a Method.
typedef F_PSI_IS_SUPPORTED *PF_PSI_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable PSI.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c
index 0b922f5..b4ebbb3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c
@@ -84,7 +84,7 @@ EnablePstateHpcModeOnAps (
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateHpcModeFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should P-state HPC mode be enabled
* If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE
@@ -126,7 +126,7 @@ IsPstateHpcModeFeatureSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable high performance computing (HPC mode)
*
@@ -182,7 +182,7 @@ InitializePstateHpcModeFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable Pstate HPC mode
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h
index 37e22ef..e07fbb4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h
@@ -57,7 +57,7 @@ AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable P-state HPC mode
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c
index 5eb55d8..39d79c5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -960,7 +960,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
index ce4487f..cbef07e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
@@ -99,7 +99,7 @@ typedef struct {
IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
} S_CPU_AMD_PSTATE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -121,7 +121,7 @@ typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c
index ad03863..aac92fa 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c
@@ -133,7 +133,7 @@ ReleaseSlitBuffer (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -157,7 +157,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -182,7 +182,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -318,7 +318,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -346,7 +346,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -367,7 +367,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
index 5d0cc93..a5068fd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
@@ -141,7 +141,7 @@ STATIC
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -164,7 +164,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -187,7 +187,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -298,7 +298,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -509,7 +509,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -545,7 +545,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c
index decb1b5..c6e987d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c
@@ -79,7 +79,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should software C1e be enabled
*
@@ -130,7 +130,7 @@ IsSwC1eFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Software C1e
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h
index 04ea50a..b1687ea 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if software C1e is supported.
*
@@ -77,7 +77,7 @@ typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
/// Reference to a Method
typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable software C1e.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
index fa62864..244608f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
@@ -97,7 +97,7 @@ GetAcpiWheaMain (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -119,7 +119,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -145,7 +145,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -243,7 +243,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
index f2c65e0..9c305e4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
@@ -149,7 +149,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -182,7 +182,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -279,7 +279,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -371,7 +371,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -466,7 +466,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -509,7 +509,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -555,7 +555,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -639,7 +639,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -700,7 +700,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -760,7 +760,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -866,7 +866,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -974,7 +974,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -1027,7 +1027,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1083,7 +1083,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1104,7 +1104,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1128,7 +1128,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1153,7 +1153,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1177,7 +1177,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1201,7 +1201,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c
index ba2ab30..c1942ec 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c
@@ -89,7 +89,7 @@ SetRegistersFromTablesAtEarly (
extern BUILD_OPT_CFG UserOptions;
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -150,7 +150,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -181,7 +181,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -254,7 +254,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -285,7 +285,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -336,7 +336,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Family Specific Workaround Register Entry.
*
@@ -365,7 +365,7 @@ SetRegisterForFamSpecificWorkaroundEntry (
Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -404,7 +404,7 @@ SetRegisterForPerformanceProfileEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -445,7 +445,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -486,7 +486,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts PCI Register Entry.
*
@@ -527,7 +527,7 @@ SetRegisterForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts MSR Register Entry.
*
@@ -560,7 +560,7 @@ SetMsrForComputeUnitCountsEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -654,7 +654,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -702,7 +702,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -746,7 +746,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -781,7 +781,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -864,7 +864,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
index c21cb9c..d5012b1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
@@ -120,11 +120,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -162,11 +162,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -622,11 +622,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -896,11 +896,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -950,11 +950,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -981,11 +981,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -1047,11 +1047,11 @@ typedef struct {
FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
index e42150f..15cac04 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
@@ -85,7 +85,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers using BKDG values.
*
@@ -140,7 +140,7 @@ SetRegisterForHtPhyEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program a range of HT Phy PCI registers using BKDG values.
*
@@ -205,7 +205,7 @@ SetRegisterForHtPhyRangeEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -226,7 +226,7 @@ IsDeemphasisLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Package Link number, for the current node and real link number.
*
@@ -275,7 +275,7 @@ LookupPackageLink (
return PackageLink;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the platform's specified deemphasis levels for the current link.
*
@@ -331,7 +331,7 @@ GetLinkDeemphasis (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program Deemphasis registers using BKDG values, for the platform specified levels.
*
@@ -422,7 +422,7 @@ SetRegisterForDeemphasisEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program HT Phy PCI registers which have complex frequency dependencies.
*
@@ -531,7 +531,7 @@ SetRegisterForHtPhyFreqEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Phy Performance Profile Register Entry.
*
@@ -567,7 +567,7 @@ SetRegisterForHtPhyProfileEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host PCI Register Entry.
*
@@ -626,7 +626,7 @@ SetRegisterForHtHostEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Host Performance PCI Register Entry.
*
@@ -668,7 +668,7 @@ SetRegisterForHtHostPerfEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the HT Link Token Count registers.
*
@@ -747,7 +747,7 @@ SetRegisterForHtLinkTokenEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Token Counts PCI Register Entry.
*
@@ -791,7 +791,7 @@ SetRegisterForTokenPciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link Feature PCI Register Entry.
*
@@ -864,7 +864,7 @@ SetRegisterForHtFeaturePciEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the HT Link PCI Register Entry.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c
index 2fd796d..1281ee3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c
@@ -197,7 +197,7 @@ ExecuteFinalHltInstruction (
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -281,7 +281,7 @@ LocalApicInitialization (
LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -305,7 +305,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -453,7 +453,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -482,7 +482,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -507,7 +507,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -531,7 +531,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -552,7 +552,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -658,7 +658,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -710,7 +710,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -777,7 +777,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -823,7 +823,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -898,7 +898,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -979,7 +979,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1126,7 +1126,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1164,7 +1164,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1212,7 +1212,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1241,7 +1241,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1272,7 +1272,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1294,7 +1294,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1327,7 +1327,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1352,7 +1352,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1394,7 +1394,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c
index f759c1f..9e53fc9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c
@@ -72,7 +72,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -145,7 +145,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c
index 9a20bb4..e994350 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c
@@ -89,7 +89,7 @@ SetBrandIdRegistersAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
@@ -284,7 +284,7 @@ SetBrandIdRegisters (
HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Program BrandID registers (CPUIDNameStringPtr[0-5])
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c
index 8eeab49..f9e833b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c
@@ -93,7 +93,7 @@ McaInitializationAtEarly (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
@@ -116,7 +116,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -276,7 +276,7 @@ AmdCpuEarly (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -321,7 +321,7 @@ McaInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -343,7 +343,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
@@ -379,7 +379,7 @@ ApUtilRunCodeOnAllLocalCoresAtEarly (
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c
index e4394a2..cf01ae3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c
@@ -94,7 +94,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -131,7 +131,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -168,7 +168,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -246,7 +246,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -300,7 +300,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -362,7 +362,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c
index 6ae07d3..3ed80ed 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c
@@ -127,7 +127,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -166,7 +166,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -189,7 +189,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -261,7 +261,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -288,7 +288,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -314,7 +314,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -337,7 +337,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -362,7 +362,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -389,7 +389,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -413,7 +413,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -456,7 +456,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
index 71cc991..fe14552 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
@@ -804,7 +804,7 @@ typedef enum {
} FAMILY_CACHE_INIT_POLICY;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c
index b0751f7..7e6b76b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c
@@ -184,7 +184,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -228,7 +228,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -272,7 +272,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -314,7 +314,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -333,7 +333,7 @@ GetPlatformNumberOfSockets ( VOID )
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -351,7 +351,7 @@ GetPlatformNumberOfModules ( VOID )
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -395,7 +395,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -438,7 +438,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -483,7 +483,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -526,7 +526,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -548,7 +548,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -570,7 +570,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -649,7 +649,7 @@ GetNumberOfCompUnitsInCurrentModule (
return ComputeUnitCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -688,7 +688,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -735,7 +735,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -774,7 +774,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -797,7 +797,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -831,7 +831,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -871,7 +871,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -914,7 +914,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -948,7 +948,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -977,7 +977,7 @@ GetSystemDegree (
return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -1007,7 +1007,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1036,7 +1036,7 @@ IsBsp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the compute unit mapping algorithm.
*
@@ -1102,7 +1102,7 @@ GetComputeUnitMapping (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is current core the primary core of its compute unit?
*
@@ -1150,7 +1150,7 @@ IsCorePairPrimary (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Are the two specified cores shared in a compute unit?
*
@@ -1199,7 +1199,7 @@ AreCoresPaired (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c
index 3564db4..c68a94e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c
@@ -95,7 +95,7 @@ CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
{NULL, 0}
};
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c
index a82625d..43a24d8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c
@@ -78,7 +78,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -113,7 +113,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CpuLateInitApTask
@@ -209,7 +209,7 @@ CpuLateInitApTask (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -252,7 +252,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -283,7 +283,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -338,7 +338,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
index 9b54068..d8f8351 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
@@ -92,7 +92,7 @@ LoadMicrocodePatchAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -161,7 +161,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -205,7 +205,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -264,7 +264,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -373,7 +373,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -401,7 +401,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
index 453a60e..e1b6754 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
@@ -104,7 +104,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -180,7 +180,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -207,7 +207,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -234,7 +234,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -352,7 +352,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -392,7 +392,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
@@ -413,7 +413,7 @@ FinalizeAtPost (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection.
*
@@ -439,7 +439,7 @@ SetTscFreqSel (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set TSC Frequency Selection to all cores.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c
index 8988ea3..bcdb5df 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c
@@ -99,7 +99,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -156,7 +156,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -219,7 +219,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -246,7 +246,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c
index 84f7d37..11775d8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -85,7 +85,7 @@ GetNextEvent (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -144,7 +144,7 @@ RunCodeOnAllSystemCore0sMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -184,7 +184,7 @@ GetNumberOfSystemPmStepsPtrMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the frequency that the northbridges must run.
*
@@ -283,7 +283,7 @@ GetSystemNbCofMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -332,7 +332,7 @@ GetSystemNbCofVidUpdateMulti (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -473,7 +473,7 @@ GetMinNbCofMulti (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get PCI Config Space Address for the current running core.
*
@@ -516,7 +516,7 @@ GetCurrPciAddrMulti (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
@@ -560,7 +560,7 @@ ModifyCurrSocketPciMulti (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to return the next event log entry to the BSC.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c
index b89f23a..560ef34 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -104,7 +104,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -129,7 +129,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -178,7 +178,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -207,7 +207,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -276,7 +276,7 @@ GetMinNbCofSingle (
ASSERT ((MinSysNbFreq != 0) && (MinP0NbFreq != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get PCI Config Space Address for the current running core.
*
@@ -297,7 +297,7 @@ GetCurrPciAddrSingle (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
index c252c75..3006d49 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -98,7 +98,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -143,7 +143,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
@@ -193,7 +193,7 @@ IsWarmReset (
return WarmReset;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index 707b19f..80588f8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -103,7 +103,7 @@ InsertFreeSpaceNode (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -232,7 +232,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -425,7 +425,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -557,7 +557,7 @@ HeapDeallocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -665,7 +665,7 @@ HeapLocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the heap base address
*
@@ -727,7 +727,7 @@ HeapGetBaseAddress (
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DeleteFreeSpaceNode
@@ -786,7 +786,7 @@ DeleteFreeSpaceNode (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InsertFreeSpaceNode
@@ -839,7 +839,7 @@ InsertFreeSpaceNode (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
index bb174e6..24f2db1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
@@ -81,7 +81,7 @@ extern CPU_FAMILY_SUPPORT_TABLE MmioMapFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* MMIO map manager
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
index cf3881f..99912dd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
@@ -94,7 +94,7 @@ typedef struct _AMD_ADD_MMIO_PARAMS {
AMD_MMIO_ATTRIBUTE Attributes;///< This indicates the attributes of the requested range.
} AMD_ADD_MMIO_PARAMS;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to MMIO map manager.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c
index 1ec94d3..5d74cfa 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c
@@ -97,7 +97,7 @@ AllocateExecutionCacheInitializer (
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -117,7 +117,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -145,7 +145,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -180,7 +180,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
index de6f06a..78849dc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
@@ -112,7 +112,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
index a70d5b5..6cf3ece 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
@@ -89,7 +89,7 @@ AmdLatePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -185,7 +185,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
index d67d0a2..dba4781 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
@@ -109,7 +109,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
index e7bed28..1c25ec7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
@@ -90,7 +90,7 @@ AmdPostPlatformConfigInit (
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -199,7 +199,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c
index 009cca4..830980e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
@@ -124,7 +124,7 @@ AmdInitRecovery (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initialize defaults and options for Amd Init Reset.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
index 96e9ffb..1008a5d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
@@ -87,7 +87,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -111,7 +111,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -221,7 +221,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c
index 3079a51..11a652a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -173,7 +173,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -204,7 +204,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
index 4bd7e5c..2d61ca9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G3_DXE)
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -123,7 +123,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
index 58cd56f..5603a05 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
@@ -84,7 +84,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -159,7 +159,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -191,7 +191,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3LateRestore stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c
index 5f1171c..ca9a601 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c
@@ -102,7 +102,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -306,7 +306,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -339,7 +339,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -391,7 +391,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
index ff72538..450b001 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
@@ -73,7 +73,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
index 7a74c0c..af47cb3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
@@ -76,7 +76,7 @@ FchTaskDummy (
IN VOID *DataPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return TRUE.
*
@@ -89,7 +89,7 @@ CommonReturnTrue ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -101,7 +101,7 @@ CommonReturnFalse ( VOID )
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -114,7 +114,7 @@ CommonReturnZero8 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -127,7 +127,7 @@ CommonReturnZero32 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -140,7 +140,7 @@ CommonReturnZero64 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -152,7 +152,7 @@ CommonReturnNULL ( VOID )
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -165,7 +165,7 @@ CommonReturnAgesaSuccess ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -175,7 +175,7 @@ CommonVoid ( VOID )
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
@@ -187,7 +187,7 @@ CommonAssert ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c
index aa3d63a..9322f57 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c
@@ -77,7 +77,7 @@ extern CONST UINTN InitializerCount;
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -222,7 +222,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
index a24cdc2..ce61958 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
@@ -82,7 +82,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -99,7 +99,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -116,7 +116,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -142,7 +142,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
index 07f684f..e9b09fd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
@@ -78,7 +78,7 @@ S3SaveStateExtendTableLenth (
IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -94,7 +94,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -110,7 +110,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -138,7 +138,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -192,7 +192,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -220,7 +220,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -284,7 +284,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -358,7 +358,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -434,7 +434,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 info opcode
*
@@ -490,7 +490,7 @@ S3SaveStateSaveInfoOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 dispatch opcode
*
@@ -554,7 +554,7 @@ S3SaveStateSaveDispatchOp (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
@@ -599,7 +599,7 @@ S3SaveDebugOpcodeString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
index bd2e286..97ab099 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
@@ -44,7 +44,7 @@
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchSmmAcpiOn - Config Fch during ACPI_ON
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c
index bbfb235..e629e44 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c
@@ -329,7 +329,7 @@ RwAlink (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -360,7 +360,7 @@ ReadPmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO
*
@@ -391,7 +391,7 @@ WritePmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio - Read/Write PMIO
*
@@ -421,7 +421,7 @@ RwPmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO2
*
@@ -453,7 +453,7 @@ ReadPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO 2
*
@@ -485,7 +485,7 @@ WritePmio2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio2 - Read/Write PMIO2
*
@@ -515,7 +515,7 @@ RwPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read BIOSRAM
*
@@ -546,7 +546,7 @@ ReadBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write BIOSRAM
*
@@ -577,7 +577,7 @@ WriteBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Record SMI Status
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c
index 2960bde..e8496b2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c
@@ -43,7 +43,7 @@
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
*
@@ -89,7 +89,7 @@ ProgramPciByteTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
*
@@ -125,7 +125,7 @@ ProgramFchAcpiMmioTbl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
*
@@ -163,7 +163,7 @@ ProgramFchSciMapTbl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
*
@@ -195,7 +195,7 @@ ProgramFchGpioTbl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
*
@@ -293,7 +293,7 @@ GetEfuseStatus (
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SbSleepTrapControl - SB Sleep Trap Control
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c
index 0a4433b..b2d39ad 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c
@@ -61,7 +61,7 @@ FchInitEnvEc (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* EnterEcConfig - Force EC into Config mode
*
@@ -83,7 +83,7 @@ EnterEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ExitEcConfig - Force EC exit Config mode
*
@@ -105,7 +105,7 @@ ExitEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ReadEc8 - Read EC register data
*
@@ -131,7 +131,7 @@ ReadEc8 (
LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwEc8 - Read/Write EC register
*
@@ -158,7 +158,7 @@ RwEc8 (
WriteEc8 (Address, &Result, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* WriteEc8 - Write date into EC register
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
index 98004f1..4c8a462 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
@@ -64,7 +64,7 @@ AGESA_STATUS
FchEnvConstructor (
IN AMD_ENV_PARAMS *EnvParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitEnv - Config Fch before PCI emulation
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
index 07606f4..206dcd8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
@@ -59,7 +59,7 @@ FchLateConstructor (
IN AMD_LATE_PARAMS *LateParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitLate - Prepare Fch to boot to OS.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
index 5c9341a..bb0356e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
@@ -47,7 +47,7 @@
extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[];
extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[];
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
*
@@ -69,7 +69,7 @@ FchInitS3EarlyRestore (
FchDataPtr->Misc.S3Resume = 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
index e06f8a0..abcbe4d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
@@ -72,7 +72,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* DIspathc feature tanle
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
index 0e032f0..1158959 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
@@ -78,7 +78,7 @@ AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early
*
@@ -98,7 +98,7 @@ GnbInitAtEarly (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early before CPU
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
index 67f13af..3ad8d06 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
@@ -76,7 +76,7 @@ GnbInitDataStructAtEnvDef (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -113,7 +113,7 @@ GnbInitDataStructAtEnvDef (
GnbEnvConfigPtr->DisplayMiscControl.Value = UserOptions.CfgDisplayMiscControl.Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
index 6343f81..87cfd4a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
@@ -70,7 +70,7 @@ GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
index 3e49871..60e96c6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
@@ -70,7 +70,7 @@ GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
index 5648303..60dce1a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
@@ -85,7 +85,7 @@ GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -104,7 +104,7 @@ GnbInitDataStructAtPostDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -125,7 +125,7 @@ GnbInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
index 5ea034b..0b9d4e0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
@@ -68,7 +68,7 @@ GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
index 2b78d6a..2273606 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
@@ -70,7 +70,7 @@ GnbInitAtS3Save (
IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at S3 save
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
index 659300a..f3fa0a0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
@@ -61,7 +61,7 @@ GnbLibStallS3Script (
IN VOID* Context
);
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall and save to script table
*
@@ -82,7 +82,7 @@ GnbLibStallS3Save (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall
*
@@ -109,7 +109,7 @@ GnbLibStall (
} while (TimeStampDelta < Microsecond);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Stall S3 script
*
@@ -128,7 +128,7 @@ GnbLibStallS3Script (
{
GnbLibStall (* ((UINT32*) Context), StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Time stamp in us
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 6f900bd..daa76ac 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -75,7 +75,7 @@ extern GNB_SERVICE *ServiceTable;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers
*
@@ -101,7 +101,7 @@ GnbLibPciIndirectRead (
GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers field
*
@@ -130,7 +130,7 @@ GnbLibPciIndirectReadField (
*Value = (*Value >> FieldOffset) & Mask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers
*
@@ -158,7 +158,7 @@ GnbLibPciIndirectWrite (
GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers field
*
@@ -192,7 +192,7 @@ GnbLibPciIndirectWriteField (
GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write GNB indirect registers field
*
@@ -228,7 +228,7 @@ GnbLibPciIndirectRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI registers
*
@@ -255,7 +255,7 @@ GnbLibPciRMW (
GnbLibPciWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write I/O registers
*
@@ -282,7 +282,7 @@ GnbLibIoRMW (
GnbLibIoWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Indirect IO block read
*
@@ -316,7 +316,7 @@ GnbLibIndirectIoBlockRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOAPIC ID
*
@@ -338,7 +338,7 @@ GnbLiGetIoapicId (
return (UINT8) (Value >> 24);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write MMIO registers
*
@@ -367,7 +367,7 @@ GnbLibMemRMW (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Claculate power of number
*
@@ -394,7 +394,7 @@ GnbLibPowerOf (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search buffer for pattern
*
@@ -432,7 +432,7 @@ GnbLibFind (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
@@ -484,7 +484,7 @@ GnbLibDebugDumpBuffer (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index c5b9f70..600af93 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -68,7 +68,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU (DCT) indirect registers
*
@@ -96,7 +96,7 @@ GnbLibCpuPciIndirectRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write CPU (DCT) indirect registers
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index d091083..7713369 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -65,7 +65,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -99,7 +99,7 @@ GnbAllocateHeapBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap and clear it
*
@@ -127,7 +127,7 @@ GnbAllocateHeapBufferAndClear (
return Buffer;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index e1793e1..32cef3b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -67,10 +67,10 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*---------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
+
/**
* Write I/O Port
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 29c931e..147156f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write Memory/MMIO registers
*
@@ -94,7 +94,7 @@ GnbLibMemWrite (
LibAmdMemWrite (Width, Address, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Memory/MMIO registers
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
index 390c371..0cdcb68 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -53,7 +53,7 @@
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device present
*
@@ -81,7 +81,7 @@ GnbLibPciIsDevicePresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is bridge
*
@@ -108,7 +108,7 @@ GnbLibPciIsBridgeDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is multifunction
*
@@ -135,7 +135,7 @@ GnbLibPciIsMultiFunctionDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is PCIe device
*
@@ -162,7 +162,7 @@ GnbLibPciIsPcieDevice (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCI capability pointer
*
@@ -200,7 +200,7 @@ GnbLibFindPciCapability (
}
return CapabilityPtr;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCIe extended capability pointer
*
@@ -238,7 +238,7 @@ GnbLibFindPcieExtendedCapability (
return 0;
}
#endif
-/*----------------------------------------------------------------------------------------*/
+
/*
* Scan range of device on PCI bus.
*
@@ -249,7 +249,7 @@ GnbLibFindPcieExtendedCapability (
* @param[in] ScanData Supporting data
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
@@ -306,7 +306,7 @@ GnbLibPciScan (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan all subordinate buses
*
@@ -332,7 +332,7 @@ GnbLibPciScanSecondaryBus (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe device type
*
@@ -343,7 +343,7 @@ GnbLibPciScanSecondaryBus (
*
* @retval PCIE_DEVICE_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_DEVICE_TYPE
GnbLibGetPcieDeviceType (
@@ -362,7 +362,7 @@ GnbLibGetPcieDeviceType (
return PcieNotPcieDevice;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save config space area
*
@@ -375,7 +375,7 @@ GnbLibGetPcieDeviceType (
* @param[in] StdHeader Standard header.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibS3SaveConfigSpace (
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
index 9410cfa..6acad5e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI registers
*
@@ -95,7 +95,7 @@ GnbLibPciWrite (
LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI registers
*
@@ -122,7 +122,7 @@ GnbLibPciRead (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll PCI reg
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index 2d2ac59..4f187e7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -69,7 +69,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -104,7 +104,7 @@ PcieFmConfigureEnginesLaneAllocation (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -141,7 +141,7 @@ PcieFmGetCoreConfigurationValue (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -176,7 +176,7 @@ PcieFmCheckPortPciDeviceMapping (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -208,7 +208,7 @@ PcieFmDebugGetCoreConfigurationString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -238,7 +238,7 @@ PcieFmDebugGetWrapperNameString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -269,7 +269,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
@@ -304,7 +304,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -335,7 +335,7 @@ PcieFmMapPortPciAddress (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -366,7 +366,7 @@ PcieFmGetComplexDataLength (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -393,7 +393,7 @@ PcieFmBuildComplexConfiguration (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -424,7 +424,7 @@ PcieFmGetLinkSpeedCap (
return PcieGen1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get native PHY lane bitmap
*
@@ -454,7 +454,7 @@ PcieFmGetNativePhyLaneBitmap (
return 0x0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -483,7 +483,7 @@ PcieFmSetLinkSpeedCap (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SB port info
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
index ae90f13..80e820e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
@@ -69,7 +69,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if IOMMU unit present and enabled
*
@@ -96,7 +96,7 @@ GnbFmCheckIommuPresent (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVRS entry
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
index 087eed9..8c072cd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -78,7 +78,7 @@ GfxConfigEnvInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
index 1fbdae6..d1ae7b5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -74,7 +74,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable GMM Access
*
@@ -127,7 +127,7 @@ GfxEnableGmmAccess (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get UMA info
*
@@ -157,7 +157,7 @@ GfxGetUmaInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate UMA configuration data
*
@@ -185,7 +185,7 @@ GfxLocateConfigData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
index 6cae630..78f6551 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
@@ -76,7 +76,7 @@ GfxConfigMidInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 90269e0..0291a4b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -78,7 +78,7 @@ GfxConfigPostInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate UMA configuration data
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
index b99210d..2d4dc34 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -85,7 +85,7 @@ GfxScanPcieDevice (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get information about all discrete GFX card in system
*
@@ -116,7 +116,7 @@ GfxGetDiscreteCardInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index 73be5d0..d6fb55a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -234,7 +234,7 @@ UINT8 ConnectorNumerArray[] = {
// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS)
6, 1, 6, 6, 6, 1, 1, 2
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -308,7 +308,7 @@ EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
0x260,
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -342,7 +342,7 @@ GfxIntegratedExtDisplayDeviceInfo (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors
*
@@ -390,7 +390,7 @@ GfxIntegratedEnumerateAllConnectors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -428,7 +428,7 @@ GfxIntegratedDdiInterfaceCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -508,7 +508,7 @@ GfxIntegratedEnumConnectorsForDevice (
return ConnectorEnumInfo.Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -566,7 +566,7 @@ GfxIntegratedCopyDisplayInfo (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump display path settings
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 1670c7f..36e2d88 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -113,7 +113,7 @@ GfxIntegratedDebugDumpPpTable (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing tdp
*
@@ -152,7 +152,7 @@ GfxPowerPlayLocateTdp (
return PpFuses->SclkDpmTdpLimit[DpmIndex];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new software state
*
@@ -176,7 +176,7 @@ GfxPowerPlayCreateSwState (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new DPM state
*
@@ -209,7 +209,7 @@ GfxPowerPlayCreateDpmState (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate existing or Create new DPM state
*
@@ -238,7 +238,7 @@ GfxPowerPlayAddDpmState (
return GfxPowerPlayCreateDpmState (PpWorkspace, Sclk, Vid, Tdp);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add reference to DPM state for SW state
*
@@ -256,7 +256,7 @@ GfxPowerPlayAddDpmStateToSwState (
SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy SW state info to PPTable
*
@@ -293,7 +293,7 @@ GfxPowerPlayAttachStateInfoBlock (
PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray);
return StateArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy clock info to PPTable
*
@@ -326,7 +326,7 @@ GfxPowerPlayAttachClockInfoBlock (
return ClockInfoArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy non clock info to PPTable
*
@@ -361,7 +361,7 @@ GfxPowerPlayAttachNonClockInfoBlock (
return NonClockInfoArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if fused state valid
*
@@ -389,7 +389,7 @@ GfxPowerPlayIsFusedStateValid (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SW state calssification from fuses
*
@@ -441,7 +441,7 @@ GfxPowerPlayGetClassificationFromFuses (
return Classification;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SW state calssification2 from fuses
*
@@ -475,7 +475,7 @@ GfxPowerPlayGetClassification2FromFuses (
return Classification2;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build SCLK state info
*
@@ -544,7 +544,7 @@ GfxPowerPlayBuildSclkStateTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add ECLK state
*
@@ -577,7 +577,7 @@ GfxPowerPlayAddEclkState (
return PpWorkspace->NumOfVceClockEnties++;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add ECLK state
*
@@ -607,7 +607,7 @@ GfxPowerPlayAddEclkVoltageRecord (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach extended header
*
@@ -627,7 +627,7 @@ GfxPowerPlayAttachVceTableRevBlock (
return VceTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach extended header
*
@@ -647,7 +647,7 @@ GfxPowerPlayAttachExtendedHeaderBlock (
return ExtendedHeader;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE clock info block
*
@@ -677,7 +677,7 @@ GfxPowerPlayAttachVceClockInfoBlock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE voltage limit block
*
@@ -706,7 +706,7 @@ GfxPowerPlayAttachVceVoltageLimitBlock (
return VceClockVoltageLimitTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE state block
*
@@ -735,7 +735,7 @@ GfxPowerPlayAttachVceStateTaleBlock (
return VceStateTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build VCE state info
*
@@ -783,7 +783,7 @@ GfxPowerPlayBuildVceStateTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build PP table
*
@@ -855,7 +855,7 @@ GfxPowerPlayBuildTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump PP table
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
index 75932c6..7979aee 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
@@ -76,7 +76,7 @@ extern BUILD_OPT_CFG UserOptions;
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if GFX controller fused off
*
@@ -93,7 +93,7 @@ GfxLibIsControllerPresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Gfx SSID Registers
*
@@ -140,7 +140,7 @@ GfxInitSsid (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
@@ -171,7 +171,7 @@ GfxLibCopyMemToFb (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set iGpu VGA mode
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
index af2f493..72aa25f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
@@ -87,7 +87,7 @@ GfxEnvInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shut Down Disabled SIMDs
*
@@ -161,7 +161,7 @@ GfxShutDownDisabledSimdsTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Shut Down Disabled SIMDs
*
@@ -291,7 +291,7 @@ GfxShutDownDisabledRbsTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GFX straps.
*
@@ -377,7 +377,7 @@ GfxEnvInitTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Env Post.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
index ac24239..19bad7e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -203,7 +203,7 @@ DCT_REGISTER_ENTRY DctRegisterTable [] = {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Fb location
*
@@ -238,7 +238,7 @@ GfxGmcInitializeFbLocationTN (
GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Sequencer model info
*
@@ -269,7 +269,7 @@ GfxGmcDctMemoryChannelInfoTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize sequencer model
*
@@ -428,7 +428,7 @@ GfxGmcInitializeSequencerTN (
GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*
*
@@ -455,7 +455,7 @@ GfxGmcSecureGarlicAccessTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize C6 aperture location
*
@@ -499,7 +499,7 @@ GfxGmcInitializeC6LocationTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GMC
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
index 4364287..7b7e69b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
@@ -112,7 +112,7 @@ CONST UINT8 DdiLaneConfigArrayTN [][4] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init TN Support for eDP to Lvds translators
*
@@ -151,7 +151,7 @@ GfxIntegrateducEDPToLVDSRxIdCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init TN Nb p-State MemclkFreq
*
@@ -215,7 +215,7 @@ GfxFillNbPstateMemclkFreqTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init TN HTC Data
*
@@ -248,7 +248,7 @@ GfxFillHtcDataTN (
IntegratedInfoTable->ucHtcHystLmt = 0;
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get TN CSR phy self refresh power down mode.
*
@@ -277,7 +277,7 @@ GfxLibGetMemPhyPllPdModeTN (
return D18F2xA8.Field.MemPhyPllPdMode;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get TN disable DLL shutdown in self-refresh mode.
*
@@ -306,7 +306,7 @@ GfxLibGetDisDllShutdownSRTN (
return D18F2x90.Field.DisDllShutdownSR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init TN NbPstateVid
*
@@ -365,7 +365,7 @@ GfxFillNbPStateVidTN (
IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -426,7 +426,7 @@ GfxFmMapEngineToDisplayPath (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
@@ -454,7 +454,7 @@ GfxIntInfoTabablePostToFb (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Dispclk <-> VID table
*
@@ -491,7 +491,7 @@ GfxIntInfoTableInitDispclkTable (
IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Sclk <-> VID table
*
@@ -549,7 +549,7 @@ GfxIntInfoTableInitSclkTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Read GFX PGFSM register
*
@@ -589,7 +589,7 @@ GfxPgfsmRegisterReadTN (
*Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Calculate ulGMCRestoreResetTime
*
@@ -705,7 +705,7 @@ GfxCalculateRestoreResetTimeTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
*
@@ -860,7 +860,7 @@ GfxIntInfoTableInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
* GMC FB access requred
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
index 0b9fdef..19f0582 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
@@ -93,7 +93,7 @@ BOOLEAN
GfxFmIsVbiosPosted (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable GFX controller
*
@@ -116,7 +116,7 @@ GfxFmDisableController (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get system PLL COF
*
@@ -135,7 +135,7 @@ GfxLibGetSytemPllCofTN (
return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate COF for DFS out of Main PLL
*
@@ -171,7 +171,7 @@ GfxFmCalculateClock (
return (((SystemPllCof * 100) + (Divider - 1)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set idle voltage mode for GFX
*
@@ -190,7 +190,7 @@ GfxFmIsVbiosPosted (
return ((Value & BIT16) == 0) ? TRUE : FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Extract DRAM frequency
*
@@ -213,7 +213,7 @@ GfxLibExtractDramFrequency (
return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max SCLK
*
@@ -239,7 +239,7 @@ GfxLibGetMaxSclk (
return MaxSclkClk;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of SCLK Dram burst
*
@@ -269,7 +269,7 @@ GfxLibGetNumberOfSclkPerDramBurst (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate TN NCLK clock
*
@@ -299,7 +299,7 @@ GfxLibGetNclkTN (
return ((10000 * (NbFid + 4)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set VID through CG client
*
@@ -334,7 +334,7 @@ GfxRequestVoltageTN (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set SCLK
*
@@ -355,7 +355,7 @@ GfxRequestSclkTNS3Save (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set SCLK
*
@@ -388,7 +388,7 @@ GfxRequestSclkTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Sclk in S3 script
*
@@ -409,7 +409,7 @@ GfxRequestSclkTNS3Script (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate did from main VCO
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
index c993c89..8003fac 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
@@ -94,7 +94,7 @@ VOID
exec803 /* GfxAzWorkaroundTN */ (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set boot up voltage
*
@@ -113,7 +113,7 @@ GfxSetBootUpVoltageTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set boot up voltage
*
@@ -141,7 +141,7 @@ exec803 /* GfxAzWorkaroundTN */ (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Mid Post.
*
@@ -197,7 +197,7 @@ GfxMidInterfaceTN (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine number of audio ports for each connector
*
@@ -232,7 +232,7 @@ GfxIntegratedAudioEnumCallback (
IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors with audio capability and configure number of ports
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
index 7fc2609..cacfd19 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
@@ -76,7 +76,7 @@ GfxPostInterfaceTN (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Post.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
index 34b313a..4910bc5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
@@ -74,7 +74,7 @@
INT32 _fltused = 0;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate power of
*
@@ -98,7 +98,7 @@ GnbBapmPowerOf (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Decode R from fuse
*
@@ -117,7 +117,7 @@ GnbBapmDecodeR (
return ((FuseR & 0x200) != 0) ? (-1) * Value : Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Decode Tau from fuse
*
@@ -136,7 +136,7 @@ GnbBapmDecodeTau (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calaculate X
*
@@ -160,7 +160,7 @@ GnbBapmCalculateX (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calaculate Y
*
@@ -181,7 +181,7 @@ GnbBapmCalculateY (
return (Result * GnbBapmPowerOf (2, 32)) + 0.5;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set X & Y value
*
@@ -218,7 +218,7 @@ GnbBapmSetYAndX (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Extract INt32 from DOUBLE
*
@@ -247,7 +247,7 @@ GnbFpLibDoubleToInt32 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calcuate BAPM coefficient
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
index ef035dd..b2efb8b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
@@ -93,7 +93,7 @@ AGESA_STATUS
GnbEarlierInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
@@ -121,7 +121,7 @@ GnbAdjustSmuVidBeforeSmuTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
@@ -184,7 +184,7 @@ GnbAdjustSmuVidAfterSmuTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb SMU LHTC support
*
@@ -230,7 +230,7 @@ GnbBapmLhtcInitTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Measured temperature with BAPM
*
@@ -272,7 +272,7 @@ GnbBapmMeasuredTempTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb SMU LHTC Enable
*
@@ -296,7 +296,7 @@ GnbLhtcEnableTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb TN Update BAPMTI_TjOffset
*
@@ -361,7 +361,7 @@ GnbTjOffsetUpdateTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* GPU CAC enablement and weights programming
*
@@ -428,7 +428,7 @@ GnbCacEnablement (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Decode power of CPU out of Watt
*
@@ -458,7 +458,7 @@ CpuPowerDecode (
return Power;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Encode the offset of power of CPU
*
@@ -504,7 +504,7 @@ CpuPowerOffsetEncode (
return (UINT8) PowerOffsetEncode;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Decode power of GPU out of Watt
*
@@ -528,7 +528,7 @@ GpuPowerDecode (
return Power;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Decode Max Tj
*
@@ -549,7 +549,7 @@ TjMaxDecode (
return (TjMax * 100);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* for BAPMTI_TjOffset decoding
*
@@ -600,7 +600,7 @@ TjOffsetDecode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to
* account for underspec thermal solutions.
@@ -712,7 +712,7 @@ GnbSoftwareTjOffsetTN (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init TDC
*
@@ -742,7 +742,7 @@ GnbInitTdc (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
@@ -805,7 +805,7 @@ GnbEarlyInterfaceTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
index 380403f..61d0132 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
@@ -83,7 +83,7 @@ GnbEnvInterfaceTN (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
index cbcc329..abbe7b7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -784,7 +784,7 @@ FUSE_TABLE_TN FuseTableTN = {
FuseRegisterTableTN
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Fuse Table TN
*
@@ -825,7 +825,7 @@ NbFuseLoadFuseTableTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb load fuse table
*
@@ -870,7 +870,7 @@ GnbLoadFuseTableTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump fuse table
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
index f6e54cd..023e9ea 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
@@ -109,7 +109,7 @@ GnbCheckIommuPresentTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if IOMMU unit present and enabled
*
@@ -132,7 +132,7 @@ GnbCheckIommuPresentTN (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVRS entry
*
@@ -177,7 +177,7 @@ GnbCreateIvrsEntryTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVRS entry
*
@@ -213,7 +213,7 @@ GnbCreateIvhdHeaderTN (
(4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHD entry
*
@@ -237,7 +237,7 @@ GnbCreateIvhdTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
index 298f7ce..8906b9d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
@@ -90,7 +90,7 @@ GnbMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Registers needs to be set if no GFX PCIe ports beeing us
*
@@ -141,7 +141,7 @@ GnbIommuMidInitCheckGfxPciePorts (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to for each PCIe port
*
@@ -219,7 +219,7 @@ GnbIommuMidInitOnPortCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Orb/Ioc Cgtt Override setting
*
@@ -287,7 +287,7 @@ GnbCgttOverrideTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* IOMMU Mid Init
*
@@ -321,7 +321,7 @@ GnbIommuMidInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* IOMMU Mid Init
*
@@ -466,7 +466,7 @@ GnbLclkDpmInitTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Post Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
index d34bdb7..c0396f6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
@@ -72,7 +72,7 @@ GnbPostInterfaceTN (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
index b228b2d..835ed78 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
@@ -101,7 +101,7 @@ GnbRegisterWriteServiceTN (
IN UINT32 Flags,
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/*
* Config Dct and Mp.
*
@@ -158,7 +158,7 @@ GnbDctMpConfigTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to Read Dct Additional Data.
*
@@ -221,7 +221,7 @@ GnbDctAdditionalDataReadTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to Write Dct Additional Data.
*
@@ -286,7 +286,7 @@ GnbDctAdditionalDataWriteTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to read all register spaces.
*
@@ -311,7 +311,7 @@ GnbRegisterReadServiceTN (
{
return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to read all register spaces.
*
@@ -771,7 +771,7 @@ GnbRegisterReadTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to write all register spaces.
*
@@ -797,7 +797,7 @@ GnbRegisterWriteServiceTN (
return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to write all register spaces.
*
@@ -1248,7 +1248,7 @@ GnbRegisterWriteTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to dump all write register spaces.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
index 4920ee8..b5c9c7f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
@@ -71,7 +71,7 @@ PcieAlibGetBaseTableTNFM2 (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get base SSDT table
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
index 34e2451..b910d2e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
@@ -71,7 +71,7 @@ PcieAlibGetBaseTableTNFS1 (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get base SSDT table
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
index 2ee1d2c..aaa22fb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
@@ -181,7 +181,7 @@ PcieGetSbConfigInfoTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -236,7 +236,7 @@ CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = {
{0, 7, 8, 15}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -279,7 +279,7 @@ CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = {
{0, 7, 8, 11, 12, 15},
{4, 7, 8, 11, 12, 15}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -316,7 +316,7 @@ PcieConfigureGfxDdiEnginesLaneAllocationTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -366,7 +366,7 @@ CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure GFX engine list to support lane allocation according to configuration ID.
*
@@ -410,7 +410,7 @@ CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
{0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure DDI engine list to support lane allocation according to configuration ID.
*
@@ -452,7 +452,7 @@ CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = {
{0, 3}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure DDI engine list to support lane allocation according to configuration ID.
*
@@ -489,7 +489,7 @@ PcieConfigureDdi2EnginesLaneAllocationTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get configuration Value for GFX wrapper
*
@@ -520,7 +520,7 @@ PcieGetGfxConfigurationValueTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get configuration Value for GPP wrapper
*
@@ -557,7 +557,7 @@ PcieGetGppConfigurationValueTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -591,7 +591,7 @@ PcieGetCoreConfigurationValueTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -619,7 +619,7 @@ PcieCheckPortPciDeviceMappingTN (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -655,7 +655,7 @@ PcieDebugGetCoreConfigurationStringTN (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -685,7 +685,7 @@ PcieDebugGetWrapperNameStringTN (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -741,7 +741,7 @@ PcieDebugGetHostRegAddressSpaceStringTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
@@ -794,7 +794,7 @@ PcieCheckPortPcieLaneCanBeMuxedTN (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -878,7 +878,7 @@ PcieMapPortPciAddressTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -903,7 +903,7 @@ PcieGetComplexDataLengthTN (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -925,7 +925,7 @@ PcieBuildComplexConfigurationTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* get native PHY lane bitmap
*
@@ -949,7 +949,7 @@ STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = {
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build default SB configuration descriptor
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
index c696d1c..ee76130 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
@@ -90,7 +90,7 @@ PcieEarlyInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane parameter Init
*
@@ -139,7 +139,7 @@ PciePhyLaneInitInitCallbackTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Satic init for various registers.
*
@@ -168,7 +168,7 @@ PcieEarlyStaticInitTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init core registers.
*
@@ -210,7 +210,7 @@ PcieEarlyCoreInitTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Dll Cap based on fuses
*
@@ -340,7 +340,7 @@ PcieSetDllCapTN (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* TN FP2 PCIE allocation x8 check
*
@@ -392,7 +392,7 @@ PcieFP2x8CheckCallbackTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* TN FP2 PCIE critera check
*
@@ -426,7 +426,7 @@ PcieFP2CriteriaTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RX offset cancellation enablement
*
@@ -477,7 +477,7 @@ PcieOffsetCancelCalibration (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
*
@@ -500,7 +500,7 @@ PcieInitSrbmCallbackTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY Pll Personality Init Callback
*
@@ -545,7 +545,7 @@ PciePhyLetPllPersonalityInitCallbackTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -608,7 +608,7 @@ PcieEarlyInitCallbackTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -646,7 +646,7 @@ PcieEarlyInitTN (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -701,7 +701,7 @@ PcieEarlyPortInitCallbackTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -734,7 +734,7 @@ PcieEarlyPortInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
index 51bec06..2aa1cfc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
@@ -72,7 +72,7 @@ PcieEnvInterfaceTN (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Env Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
index 3445dd2..4a912bd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
@@ -85,7 +85,7 @@ PcieGetLinkSpeedCapTN (
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visibility in PCI config space
*
@@ -114,7 +114,7 @@ PciePortsVisibilityControlTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down inactive lanes
*
@@ -149,7 +149,7 @@ PciePowerDownPllInL1TN (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request boot up voltage
*
@@ -231,7 +231,7 @@ PcieSetVoltageTN (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL power up latency
*
@@ -250,7 +250,7 @@ PciePifGetPllPowerUpLatencyTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -297,7 +297,7 @@ PcieGetLinkSpeedCapTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL personality
*
@@ -334,7 +334,7 @@ PcieSetPhyPersonalityTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* DCC recalibration
*
@@ -356,7 +356,7 @@ PcieForceDccRecalibrationCallbackTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for Osc switch
*
@@ -385,7 +385,7 @@ PcieOscPifInitPrePowerdownCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Osc switch
*
@@ -455,7 +455,7 @@ PcieOscInitPllModeCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Osc init
*
@@ -488,7 +488,7 @@ PcieOscPifInitPostPowerdownCallback (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare PHY for Gen2
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
index b72fd14..d3c025f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
@@ -84,7 +84,7 @@ PcieMidInterfaceTN (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -118,7 +118,7 @@ PcieMidPortInitCallbackTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -158,7 +158,7 @@ PcieMidPortInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Late Init.
*
@@ -182,7 +182,7 @@ PcieMidInitCallbackTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Late Init
*
@@ -214,7 +214,7 @@ PcieMidInitTN (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
index a92bd21..1df156f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
@@ -94,7 +94,7 @@ PcieLateRestoreInitTNS3Script (
IN UINT16 ContextLength,
IN VOID* Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -132,7 +132,7 @@ PciePostPortInitCallbackTN (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -206,7 +206,7 @@ PciePostS3PortInitCallbackTN (
PcieTrainingSetPortState (Engine, State, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -233,7 +233,7 @@ PciePostEarlyPortInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -262,7 +262,7 @@ PciePostPortInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -291,7 +291,7 @@ PciePostS3PortInitTN (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -320,7 +320,7 @@ PciePostInitTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -358,7 +358,7 @@ PciePostEarlyInterfaceTN (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -401,7 +401,7 @@ PciePostInterfaceTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -447,7 +447,7 @@ PciePostS3InterfaceTN (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe S3 restore
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
index c36d1fc..8ab1577 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
@@ -78,7 +78,7 @@ PciePowerGateTN (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Report used lanes
*
@@ -142,7 +142,7 @@ PciePowerGateReportActiveLanesCallbackTN (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes
*
@@ -218,7 +218,7 @@ PciePowerGatePowerDownUnusedLanesCallbackTN (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes
*
@@ -296,7 +296,7 @@ PciePowerGatePowerDownLanesCallbackTN (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Power gate init
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index 9a243c2..50720ae 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -107,7 +107,7 @@ IOMMU_IVRS_HEADER IvrsHeader = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build IVRS table
*
@@ -172,7 +172,7 @@ GnbIommuIvrsTable (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build IVMD list
*
@@ -231,7 +231,7 @@ GnbBuildIvmdList (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump IVRS table
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
index 2721144..31ef428 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for device range
*
@@ -108,7 +108,7 @@ GnbIvhdAddDeviceRangeEntry (
Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for aliased range
*
@@ -147,7 +147,7 @@ GnbIvhdAddDeviceAliasRangeEntry (
Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHDR entry for special device
*
@@ -182,7 +182,7 @@ GnbIvhdAddSpecialDeviceEntry (
Ivhd->Length = sizeof (IVHD_SPECIAL_ENTRY) + Offset;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVMD entry
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
index b0e0066..b0b2bec 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
@@ -73,7 +73,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Host bridge PCI Address
*
@@ -108,7 +108,7 @@ GnbFmGetPciAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bus range decoded by GNB
*
@@ -146,7 +146,7 @@ GnbFmGetBusDecodeRange (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link to which GNB connected to
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index 45469b2..0947e51 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -73,7 +73,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB set top of memory
*
@@ -139,7 +139,7 @@ GnbSetTom (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Avoid LPC DMA transaction deadlock
*
@@ -176,7 +176,7 @@ GnbLpcDmaDeadlockPrevention (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Dynamic Wake
* ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
@@ -223,7 +223,7 @@ GnbOrbDynamicWake (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock NB registers
*
@@ -251,7 +251,7 @@ GnbLock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -283,7 +283,7 @@ GnbClumpUnitID (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of highest SCLK VID
*
@@ -319,7 +319,7 @@ GnbLocateHighestVidIndex (
return MaxVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of lowest SCLK VID
*
@@ -353,7 +353,7 @@ GnbLocateLowestVidIndex (
return MinVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the highest SCLK VID (high voltage)
*
@@ -377,7 +377,7 @@ GnbLocateHighestVidCode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the lowest SCLK VID (low voltage)
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index db867a1..271abfd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -86,7 +86,7 @@ GnbSmuServiceRequestV4S3Script (
IN VOID *Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check a PCIE device to see if it supports phantom functions
*
@@ -111,7 +111,7 @@ GnbCheckPhantomFuncSupport (
return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -167,7 +167,7 @@ GnbTopologyInfoScanCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOMMU topology info
*
@@ -199,7 +199,7 @@ GnbGetTopologyInfoV4 (
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU service request
*
@@ -244,7 +244,7 @@ GnbSmuServiceRequestV4 (
} while (D0F0xBC_xE0003004.Field.IntDone == 0x0);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU service request for S3 script
*
@@ -266,7 +266,7 @@ GnbSmuServiceRequestV4S3Script (
GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware download
*
@@ -418,7 +418,7 @@ GnbSmuFirmwareLoadV4 (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOMMU PCI address
*
@@ -440,7 +440,7 @@ GnbGetIommuPciAddressV4 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -494,7 +494,7 @@ GnbClumpUnitIdV4 (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Config GNB to prevent LPC deadlock scenario
*
@@ -539,7 +539,7 @@ GnbLpcDmaDeadlockPreventionV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable IOMMU base address. (MMIO space )
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
index 9c76490..1227ecc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -139,7 +139,7 @@ PcieAlibSetSclkVid (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create ACPI ALIB SSDT table
*
@@ -159,7 +159,7 @@ PcieAlibFeature (
return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
@@ -221,7 +221,7 @@ PcieAlibBuildAcpiTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update MMIO info
*
@@ -264,7 +264,7 @@ PcieAlibUpdatePcieMmioInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update MMIO info
*
@@ -338,7 +338,7 @@ PcieAlibUpdateVoltageInfo (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update PCIe info
*
@@ -416,7 +416,7 @@ PcieAlibUpdatePcieInfo (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -444,7 +444,7 @@ PcieAlibSetPortMaxSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init max port speed capability
*
@@ -475,7 +475,7 @@ PcieAlibSetPortOverrideSpeedCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init port info
*
@@ -511,7 +511,7 @@ PcieAlibSetPortInfoCallback (
PortInfoPackage->PortInfo[PortIndex].ClkPmSupport = Engine->Type.Port.PortData.MiscControls.ClkPmSupport;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init port info
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
index ed75277..c2bb81e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
@@ -101,7 +101,7 @@ PcieAspmGetPmCapability (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable PCIE Advance state power management
*
@@ -127,7 +127,7 @@ PcieLinkAspmEnable (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -192,7 +192,7 @@ PcieAspmCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on PCIe device function
*
@@ -203,7 +203,7 @@ PcieAspmCallback (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnFunction (
IN PCI_ADDR Function,
@@ -224,7 +224,7 @@ PcieAspmEnableOnFunction (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on all function of PCI device
*
@@ -235,7 +235,7 @@ PcieAspmEnableOnFunction (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC VOID
PcieAspmEnableOnDevice (
IN PCI_ADDR Device,
@@ -254,7 +254,7 @@ PcieAspmEnableOnDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on link
*
@@ -316,7 +316,7 @@ PcieAspmEnableOnLink (
-/**----------------------------------------------------------------------------------------*/
+
/**
* Port/Endpoint ASMP capability
*
@@ -327,7 +327,7 @@ PcieAspmEnableOnLink (
*
* @retval PCIE_ASPM_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_ASPM_TYPE
PcieAspmGetPmCapability (
IN PCI_ADDR Device,
@@ -349,7 +349,7 @@ PcieAspmGetPmCapability (
return (Value >> 10) & 3;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -382,7 +382,7 @@ PcieAspmPortInitCallback (
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Interface to enable Clock Power Managment
*
@@ -392,7 +392,7 @@ PcieAspmPortInitCallback (
*
* @retval AGESA_STATUS
*/
- /*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieAspmInterface (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
index 41f6573..43ab432 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
@@ -69,7 +69,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Clock Power Managment on function of the device
*
@@ -79,7 +79,7 @@
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC VOID
PcieClkPmEnableOnFunction (
IN PCI_ADDR Function,
@@ -100,7 +100,7 @@ PcieClkPmEnableOnFunction (
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* check capability of intire device including its functions
*
@@ -111,7 +111,7 @@ PcieClkPmEnableOnFunction (
*
* @retval TRUE - Device support Clock Power Managment
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC BOOLEAN
PcieClkPmCheckDeviceCapability (
IN PCI_ADDR Device,
@@ -148,7 +148,7 @@ PcieClkPmCheckDeviceCapability (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Clock power managment on device
*
@@ -158,7 +158,7 @@ PcieClkPmCheckDeviceCapability (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC VOID
PcieClkPmEnableOnDevice (
IN PCI_ADDR Device,
@@ -183,7 +183,7 @@ PcieClkPmEnableOnDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -233,7 +233,7 @@ PcieClkPmCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Confiugure Clock Power Managment
*
@@ -259,7 +259,7 @@ PcieClkPmPortInitConfigure (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -290,7 +290,7 @@ PcieClkPmPortInitCallback (
}
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Interface to enable Clock Power Managment
*
@@ -300,7 +300,7 @@ PcieClkPmPortInitCallback (
*
* @retval AGESA_STATUS
*/
- /*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieClkPmInterface (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
index a5dac09..deeda56 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -71,7 +71,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GNB handle
*
@@ -96,7 +96,7 @@ GnbGetHandle (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GNB socket ID
*
@@ -111,7 +111,7 @@ GnbGetSocketId (
return PcieConfigGetParentComplex (GnbHandle)->SocketId;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Get PCI_ADDR of GNB
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index 88ed9b9..14c6b3e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -110,7 +110,7 @@ PcieConfigurationMap (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration topology
*
@@ -184,7 +184,7 @@ PcieConfigurationInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration topology
*
@@ -255,7 +255,7 @@ PcieConfigurationMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -407,7 +407,7 @@ PcieConfigProcessUserConfig (
return ResultComplexConfig;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -434,7 +434,7 @@ PcieLocateConfigurationData (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attache descriptors
*
@@ -462,7 +462,7 @@ PcieConfigAttachDescriptors (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach configurations of two GNB to each other.
*
@@ -490,7 +490,7 @@ PcieConfigAttachComplexes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update configuration data
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index d41e2e8..7cdcbbe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* get Master Lane of PCIe port engine
*
@@ -100,7 +100,7 @@ PcieConfigGetPcieEngineMasterLane (
return MasterLane;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of core lanes
*
@@ -120,7 +120,7 @@ PcieConfigGetNumberOfCoreLane (
return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable engine
*
@@ -140,7 +140,7 @@ PcieConfigDisableEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable all engines on wrapper
*
@@ -166,7 +166,7 @@ PcieConfigDisableAllEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get engine PHY lanes bitmap
*
@@ -188,7 +188,7 @@ PcieConfigGetEnginePhyLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of phy lanes
*
@@ -212,7 +212,7 @@ PcieConfigGetNumberOfPhyLane (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get port configuration signature for given wrapper and core
*
@@ -241,7 +241,7 @@ PcieConfigGetConfigurationSignature (
return ConfigurationSignature;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check Port Status
*
@@ -260,7 +260,7 @@ PcieConfigCheckPortStatus (
return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set/Reset port status
*
@@ -283,7 +283,7 @@ PcieConfigUpdatePortStatus (
return Engine->InitStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all descriptor of specific type
*
@@ -322,7 +322,7 @@ PcieConfigRunProcForAllDescriptors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all wrappers in topology
*
@@ -360,7 +360,7 @@ PcieConfigRunProcForAllWrappers (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all engine in topology
*
@@ -394,7 +394,7 @@ PcieConfigRunProcForAllEngines (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get parent descriptor of specific type
*
@@ -418,7 +418,7 @@ PcieConfigGetParent (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get child descriptor of specific type
*
@@ -442,7 +442,7 @@ PcieConfigGetChild (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get peer descriptor of specific type
*
@@ -467,7 +467,7 @@ PcieConfigGetPeer (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check is engine is active or potentially active
*
@@ -494,7 +494,7 @@ PcieConfigIsActivePcieEngine (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate SB engine on wrapper
*
@@ -520,7 +520,7 @@ PcieConfigLocateSbEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump engine configuration
*
@@ -601,7 +601,7 @@ PcieConfigEngineDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump wrapper configuration
*
@@ -641,7 +641,7 @@ PcieConfigWrapperDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump configuration to debug out
*
@@ -711,7 +711,7 @@ PcieConfigDebugDump (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to user engine descriptor
*
@@ -757,7 +757,7 @@ PcieUserDescriptorConfigDump (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to debug out
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 9a6500f..1e61ae3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -71,7 +71,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of complexes in platform topology configuration
*
@@ -95,7 +95,7 @@ PcieInputParserGetNumberOfComplexes (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of PCIe engines in given complex
*
@@ -120,7 +120,7 @@ PcieInputParserGetLengthOfPcieEnginesList (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of DDI engines in given complex
*
@@ -146,7 +146,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of engines in given complex
*
@@ -168,7 +168,7 @@ PcieInputParserGetNumberOfEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -188,7 +188,7 @@ PcieInputParserGetComplexDescriptor (
return &ComplexList[Index];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -217,7 +217,7 @@ PcieInputParserGetComplexDescriptorOfSocket (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Engine descriptor from given complex by index
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index f80e788..6a3d169 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -123,7 +123,7 @@ PcieAllocateEngine (
IN UINT8 DescriptorIndex,
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -173,7 +173,7 @@ PcieMapTopologyOnComplex (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -252,7 +252,7 @@ PcieEnginesToWrapper (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
*
@@ -285,7 +285,7 @@ PcieCheckDescriptorMapsToWrapper (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Engine to be allocated.
*
@@ -303,7 +303,7 @@ PcieAllocateEngine (
Engine->Scratch = DescriptorIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -415,7 +415,7 @@ PcieMapTopologyOnWrapper (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize engine data
*
@@ -453,7 +453,7 @@ PcieMapInitializeEngineData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -484,7 +484,7 @@ PcieCheckPortPciDeviceMapping (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -546,7 +546,7 @@ PcieMapPortsPciAddresses (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* If link width from user descriptor less or equal to link width of engine
*
@@ -592,7 +592,7 @@ PcieCheckLanesMatch (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
index 886f7a1..3d0044c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -95,7 +95,7 @@ UINT16 AspmBrDeviceTable[] = {
0x1969, 0x1083, (UINT16) ~(AspmL0s)
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie ASPM Black List
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index 35aee11..b0330d9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -81,7 +81,7 @@ PcieAspmGetMaxExitLatencyCallback (
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine ASPM L-state maximum exit latency for PCIe segment
*
@@ -108,7 +108,7 @@ PcieAspmGetMaxExitLatency (
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
index 988d481..0df2c15 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
@@ -85,7 +85,7 @@ INT8 chtype_3 /* Deemph60Gen2NOm */ [] = { 42, 64, 0, 42,
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PHY lane ganging
*
@@ -155,7 +155,7 @@ PciePhyApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Point "virtual" PLL clock picker away from PCIe
*
@@ -197,7 +197,7 @@ PciePhyAvertClockPickers (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PHY channel characteristic
*
@@ -268,7 +268,7 @@ PciePhyChannelCharacteristic (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* DCC recalibration
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
index 816aa87..fa0e8ab 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -85,7 +85,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply PIF ganging for all lanes for given wrapper
*
@@ -178,7 +178,7 @@ PciePifApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -224,7 +224,7 @@ PciePifPllPowerDown (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL init for DDI
*
@@ -268,7 +268,7 @@ PciePifPllInitForDdi (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for on PIF to indicate action completion
*
@@ -301,7 +301,7 @@ PciePollPifForCompeletion (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable fifo reset
*
@@ -332,7 +332,7 @@ PciePifDisableFifoReset (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program LS2 exit time
*
@@ -364,7 +364,7 @@ PciePifSetLs2ExitTime (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -406,7 +406,7 @@ PciePifSetPllModeForL1 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
@@ -439,7 +439,7 @@ PciePifSetRxDetectPowerMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll ramp up time
*
@@ -512,7 +512,7 @@ PciePifSetPllRampTime (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
@@ -555,7 +555,7 @@ PciePifPllPowerControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 41e6afe..cc5a35b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe port indirect register.
*
@@ -97,7 +97,7 @@ PciePortRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register.
*
@@ -131,7 +131,7 @@ PciePortRegisterWrite (
GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -166,7 +166,7 @@ PciePortRegisterWriteField (
PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -195,7 +195,7 @@ PciePortRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe port register.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
index 57af1ba..45cf71a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -74,7 +74,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set completion timeout
*
@@ -111,7 +111,7 @@ PcieCompletionTimeout (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init hotplug port
*
@@ -189,7 +189,7 @@ PcieLinkInitHotplug (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set misc slot capability
*
@@ -222,7 +222,7 @@ PcieLinkSetSlotCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Safe mode to force link advertize Gen1 only capability in TS
*
@@ -252,7 +252,7 @@ PcieLinkSafeMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -277,7 +277,7 @@ PcieSetLinkWidthCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -365,7 +365,7 @@ PcieSetLinkSpeedCap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Force compliance
*
@@ -403,7 +403,7 @@ PcieForceCompliance (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slot power limit
*
@@ -434,7 +434,7 @@ PcieEnableSlotPowerLimit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on SB link
*
@@ -460,7 +460,7 @@ PcieEnableAspm (
UINT8 L1State = 0x1b;
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L1
*
@@ -481,7 +481,7 @@ PciePollLinkForL1Entry (
} while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L1
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index c1a5345..2f8c4c9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes and plls
*
@@ -117,7 +117,7 @@ PciePwrPowerDownUnusedLanes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lane bitmam to enable PLL power down in L1
*
@@ -186,7 +186,7 @@ PcieLanesToPowerDownPllInL1 (
return LaneBitmapForPllOffInL1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Auto-Power Down electrical Idle detector
*
@@ -237,7 +237,7 @@ PciePwrAutoPowerDownElectricalIdleDetector (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clock gating
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 8acf31c..e87fef9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -71,7 +71,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Gen1 voltage Index
*
@@ -103,7 +103,7 @@ PcieSiliconGetGen1VoltageIndex (
return Gen1VidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request Pcie voltage change
*
@@ -161,7 +161,7 @@ PcieSiliconRequestVoltage (
} while (ex488.Field.VoltageChangeReq != ex489.Field.VoltageChangeAck);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Unhide all ports
*
@@ -195,7 +195,7 @@ PcieSiliconUnHidePorts (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide unused ports
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
index ac6cab3..2fce628 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe timer timestamp
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index df3d000..8fdd5e5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -74,7 +74,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Cleanup reconfig
*
@@ -102,7 +102,7 @@ PcieTopologyCleanUpReconfig (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for reconfiguration
*
@@ -153,7 +153,7 @@ PcieTopologyPrepareForReconfig (
UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate mux array index
*
@@ -178,7 +178,7 @@ PcieTopologyLocateMuxIndex (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply lane mux
*
@@ -270,7 +270,7 @@ PcieTopologyApplyLaneMux (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Select master PLL
*
@@ -364,7 +364,7 @@ PcieTopologySelectMasterPll (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -435,7 +435,7 @@ PcieTopologyExecuteReconfig (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
@@ -474,7 +474,7 @@ PcieTopologySetLinkReversal (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reduce link width
*
@@ -508,7 +508,7 @@ PcieTopologyReduceLinkWidth (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lanes enable/disable control
*
@@ -547,7 +547,7 @@ PcieTopologyLaneControl (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SRBM reset
*
@@ -591,7 +591,7 @@ PcieTopologyInitSrbmReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set core configuration according to PCIe port topology
*
@@ -659,7 +659,7 @@ PcieTopologySetCoreConfig (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Relinquish control to DDI for specific lanes
*
@@ -707,7 +707,7 @@ PcieSetDdiOwnPhy (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for PCIe lanes
*
@@ -749,7 +749,7 @@ PcieWrapSetTxS1CtrlForLaneMux (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for lane muxes
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 7ea7725..337d56e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -89,7 +89,7 @@ typedef struct {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link state history from HW state machine
*
@@ -128,7 +128,7 @@ PcieUtilGetLinkHwStateHistory (
LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search array for specific pattern
*
@@ -168,7 +168,7 @@ PcieUtilSearchArray (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link reversed
*
@@ -201,7 +201,7 @@ PcieUtilIsLinkReversed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link width detected during training
*
@@ -249,7 +249,7 @@ PcieUtilGetLinkWidth (
return LinkWidth;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -316,7 +316,7 @@ PcieUtilGetPcieEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -357,7 +357,7 @@ PcieUtilGetDdiEngineLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of engine lane of requested type
*
@@ -439,7 +439,7 @@ PcieUtilGetEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of phy lane confugred for master pll
*
@@ -459,7 +459,7 @@ PcieUtilGetMasterPllLaneBitMap (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of Wrapper lane of requested type
*
@@ -503,7 +503,7 @@ PcieUtilGetWrapperLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program port register table
*
@@ -547,7 +547,7 @@ PciePortProgramRegisterTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock registers
*
@@ -581,7 +581,7 @@ PcieLockRegisters (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -625,7 +625,7 @@ PcieUtilGlobalGenCapabilityCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine global GEN capability
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
index 265c71b..2673517 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -53,7 +53,7 @@
#include "GnbPcieInitLibV1.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -77,7 +77,7 @@ PcieRegisterRead (
return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -102,7 +102,7 @@ PcieSiliconRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -135,7 +135,7 @@ PcieRegisterWrite (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -167,7 +167,7 @@ PcieSiliconRegisterWrite (
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register field.
*
@@ -196,7 +196,7 @@ PcieRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register field.
*
@@ -232,7 +232,7 @@ PcieRegisterWriteField (
PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
@@ -266,7 +266,7 @@ PcieRegisterRMW (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
index bb5b225..d231519 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
@@ -99,7 +99,7 @@ PciePayloadBlackListFeature (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine maximum payload size for PCIe segment
*
@@ -132,7 +132,7 @@ PcieSetMaxPayload (
IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadExit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment
*
@@ -194,7 +194,7 @@ PcieGetMaxPayloadCallback (
return SCAN_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure the Max Payload setting to all devices in the PCIe Segment
*
@@ -254,7 +254,7 @@ UINT16 PayloadBlacklistDeviceTable[] = {
0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Max_Payload_Size Black List
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
index 6f69a79..91cfb5f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
@@ -73,7 +73,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -159,7 +159,7 @@ PcieSetLinkSpeedCapV4 (
GnbLibGetHeader (Pcie)
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable passing TLP prefix to IOMMU if IOMMU enabled
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
index d1c265f..d7ae2b1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
@@ -75,7 +75,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clock gating
*
@@ -241,7 +241,7 @@ PciePwrClockGatingV4 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down DDI plls
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
index 1487eda..0e274f5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
@@ -77,7 +77,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Relinquish control to DDI for specific lanes
*
@@ -113,7 +113,7 @@ PcieSetDdiOwnPhyV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -181,7 +181,7 @@ PcieTopologyExecuteReconfigV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set SSID
*
@@ -208,7 +208,7 @@ PcieSetSsidV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
index c890ef7..4472958 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -114,7 +114,7 @@ PcieTrainingDebugDumpPortState (
);
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set link State
*
@@ -145,7 +145,7 @@ PcieTrainingSetPortState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set state for all engines connected to same reset ID
*
@@ -178,7 +178,7 @@ PcieSetResetStateOnEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Assert GPIO port reset.
*
@@ -209,7 +209,7 @@ PcieTrainingAssertReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for reset duration
*
@@ -232,7 +232,7 @@ PcieTrainingCheckResetDuration (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Deassert GPIO port reset.
*
@@ -263,7 +263,7 @@ PcieTrainingDeassertReset (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for after reset deassertion timeout
*
@@ -287,7 +287,7 @@ PcieTrainingCheckResetTimeout (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Release training
*
@@ -321,7 +321,7 @@ PcieTrainingRelease (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect presence of any EP on the link
*
@@ -355,7 +355,7 @@ UINT8 FailPattern1 [] = {0x2a, 0x6};
UINT8 FailPattern2 [] = {0x2a, 0x9};
UINT8 FailPattern3 [] = {0x2a, 0xb};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect Link State
*
@@ -397,7 +397,7 @@ PcieTrainingDetectLinkState (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Broken Lane
*
@@ -435,7 +435,7 @@ PcieTrainingBrokenLine (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen2
*
@@ -471,7 +471,7 @@ PcieTrainingGen2Fail (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Link in L0
*
@@ -489,7 +489,7 @@ PcieCheckLinkL0 (
{
PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen X
*
@@ -525,7 +525,7 @@ PcieTrainingCheckVcoNegotiation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if for GFX workaround condition
*
@@ -568,7 +568,7 @@ PcieTrainingGfxWorkaround (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrain link
*
@@ -596,7 +596,7 @@ PcieTrainingRetrainLink (
PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training fail on this port
*
@@ -616,7 +616,7 @@ PcieTrainingFail (
PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links training success
*
@@ -637,7 +637,7 @@ PcieTrainingSuccess (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links in compliance
*
@@ -657,7 +657,7 @@ PcieTrainingCompliance (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCie EP not present
*
@@ -688,7 +688,7 @@ PcieTrainingNotPresent (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Final state. Port training completed.
*
@@ -707,7 +707,7 @@ PcieTrainingCompleted (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -796,7 +796,7 @@ PcieTrainingPortCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main link training procedure
*
@@ -830,7 +830,7 @@ PcieTraining (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump port state on state transition
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index 2db20a2..d517255 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -112,7 +112,7 @@ PcieIsDeskewCardDetected (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* ATI RV370/RV380 card workaround
*
@@ -163,7 +163,7 @@ PcieGfxCardWorkaround (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RV370/RV380 Deskew workaround
*
@@ -206,7 +206,7 @@ PcieDeskewWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NV43 card workaround (lost SSID)
*
@@ -241,7 +241,7 @@ PcieNvWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate temporary resources for Pcie P2P bridge
*
@@ -274,7 +274,7 @@ PcieConfigureBridgeResources (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Free temporary resources for Pcie P2P bridge
*
@@ -300,7 +300,7 @@ PcieFreeBridgeResources (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Save CPU MMIO register
*
@@ -326,7 +326,7 @@ PcieProgramCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Restore CPU MMIO register
*
@@ -347,7 +347,7 @@ PcieRestoreCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if card required test for deskew workaround
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
index ffbbc08..39a10a9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
@@ -74,7 +74,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Host bridge PCI Address
*
@@ -97,7 +97,7 @@ GnbFmGetPciAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bus range decoded by GNB
*
@@ -124,7 +124,7 @@ GnbFmGetBusDecodeRange (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link to which GNB connected to
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
index dfa7314..7bcd479 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
@@ -74,7 +74,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVHD entry
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
index 3260f8b..c89df08 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
@@ -71,7 +71,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB IOAPIC Base Address
*
@@ -89,7 +89,7 @@ SbGetSbIoApicBaseAddress (
return ApicBaseAddress & 0xfffffff8;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB MMIO Base Address
*
@@ -108,14 +108,14 @@ SbGetSbMmioBaseAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Alink config address
*
* @param[in] StdHeader Standard configuration header
* @retval Alink base address
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT16
SbGetAlinkIoAddress (
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index d179e20..f876b65 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable/Disable ASPM on GNB-SB link
*
@@ -103,7 +103,7 @@ SbPcieLinkAspmControl (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SB ASPM.
* Enable ASPM states on SB
@@ -112,7 +112,7 @@ SbPcieLinkAspmControl (
* @param[in] Aspm ASPM bitmap.
* @param[in] StdHeader Standard configuration header
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
SbPcieInitAspm (
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
index 0711709..d8b6dc6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
@@ -78,7 +78,7 @@ GfxInitSview (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SVIEW configuration
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
index 8f21cfd..20f1caf 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
@@ -83,7 +83,7 @@ GnbProcessTableRegisterRmw (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process table
*
@@ -311,7 +311,7 @@ GnbProcessTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Supporting function for register read modify write
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
index 4c8f91f..fda004e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
@@ -70,7 +70,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores to the Node
*
@@ -102,7 +102,7 @@ Fam15Mod1xSetTotalCores (
LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -152,7 +152,7 @@ Fam15Mod1xGetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -175,7 +175,7 @@ Fam15Mod1xGetNodeCount (
return (1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the enable compute unit status for this node.
*
@@ -206,7 +206,7 @@ Fam15Mod1xGetEnabledComputeUnits (
return ((UINT8) Enabled);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the dual core compute unit status for this node.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c
index 23ea39e..3409d56 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htFeat.c
@@ -87,7 +87,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c
index f10a690..c5f8122 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterface.c
@@ -208,7 +208,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -233,7 +233,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c
index 571b56a..760cfef 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c
@@ -96,8 +96,8 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -167,7 +167,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -233,7 +233,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c
index fab64fd..6c440c9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c
@@ -101,7 +101,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -121,7 +121,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -201,7 +201,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -229,7 +229,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -280,7 +280,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -343,7 +343,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -443,7 +443,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -481,7 +481,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
index 2417ba1..98f7603 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -152,7 +152,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -269,7 +269,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -328,7 +328,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c
index a291eda..097cfee 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c
@@ -87,7 +87,7 @@ IsBootCore (
IN STATE_DATA *State
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -193,7 +193,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -228,7 +228,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -298,7 +298,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -346,7 +346,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -385,7 +385,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -416,7 +416,7 @@ Tuning (
State->HtFeatures->TrafficDistribution (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -449,7 +449,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -477,7 +477,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
index 89c4176..ce29c5b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
@@ -152,7 +152,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -190,7 +190,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c
index 4418f44..91a2449 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -126,7 +126,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -159,7 +159,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -195,7 +195,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -230,7 +230,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -262,7 +262,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -303,7 +303,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -341,7 +341,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -376,7 +376,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -411,7 +411,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -446,7 +446,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -485,7 +485,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -524,7 +524,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -554,7 +554,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -590,7 +590,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -629,7 +629,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
index 6507165..d25c4a7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
@@ -47,7 +47,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -167,7 +167,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
index 119cccf..f810695 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
@@ -59,7 +59,7 @@ RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_IDS_DEBUG_IDSDEBUG_FILECODE
-/*--------------------------------------------------------------------------------------*/
+
/**
* IDS back-end code for AGESA_TESTPOINT
*
@@ -67,7 +67,7 @@ RDATA_GROUP (G1_PEICC)
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
-/*--------------------------------------------------------------------------------------*/
+
VOID
IdsAgesaTestPoint (
IN AGESA_TP TestPoint,
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
index 50aa2ee..ed6d099 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
@@ -351,7 +351,7 @@ IdsGetNumPstatesFamCommon (
return pstatesnum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c
index 2eea80e..1b76158 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -105,7 +105,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c
index 1c0d6a8..c4d5bf3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveChannels:
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c
index 19f46b5..03e80a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c
@@ -103,7 +103,7 @@ MemFCratSupport (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -352,7 +352,7 @@ MemFCratSupport (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 09ecd54..8b43f36 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -105,7 +105,7 @@ MemFUndoInterleaveBanks (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -200,7 +200,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -308,7 +308,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
index 6620030..626f692 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
@@ -97,7 +97,7 @@ MemFDMISupport2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -435,7 +435,7 @@ MemFDMISupport3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c
index 559abcd..d125a83 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c
@@ -94,7 +94,7 @@ MemFCheckECC (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -160,7 +160,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c
index 0c71446..f10c539 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c
@@ -92,7 +92,7 @@ MemFInitEMP (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -156,7 +156,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 070ccd7..f0272ac 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -90,7 +90,7 @@ MemFRASExcludeDIMM (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 84f69ff..698da0f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -113,7 +113,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -206,7 +206,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -480,7 +480,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -522,7 +522,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index c707e6d..a0a0d41 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemFInterleaveRegion:
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index f914c9a..d872960 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index dc7f01b..f0c35e3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -112,7 +112,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index 697787d..50d8557 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index 5203b4f..eac4668 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index ded8b32..89e3a0c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -61,7 +61,7 @@ RDATA_GROUP (G1_PEICC)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c
index 2449ff9..c623b04 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c
@@ -94,7 +94,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -198,7 +198,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -296,7 +296,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -358,7 +358,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -408,7 +408,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -508,7 +508,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -565,7 +565,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -689,7 +689,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c
index 7709002..d8615ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c
@@ -99,7 +99,7 @@ MemMFlowTN (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c
index 52551e9..9ba74ca 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mdef.c
@@ -85,7 +85,7 @@ MemMFlowDef (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -96,7 +96,7 @@ memDefRet ( VOID )
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -108,7 +108,7 @@ memDefTrue ( VOID )
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns FALSE.
@@ -119,7 +119,7 @@ memDefFalse ( VOID )
{
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function for flow control
@@ -133,7 +133,7 @@ MemMFlowDef (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns AGESA_SUCCESS.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
index 57ecb6f..556d703 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
@@ -89,7 +89,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c
index b937026..cf17f3f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/minit.c
@@ -89,7 +89,7 @@ extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c
index a52e4eb..d62e7c0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -126,7 +126,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -236,7 +236,7 @@ SetMemError (
MCTPtr->ErrCode = Errorval;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c
index 15546ea..f741a1c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c
@@ -155,7 +155,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -428,7 +428,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -477,7 +477,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -516,7 +516,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -555,7 +555,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -599,7 +599,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -657,7 +657,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c
index d757ea2..bb8f1c2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c
@@ -82,7 +82,7 @@ MemMEcc (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c
index f4c7c66..b295bca 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c
@@ -81,7 +81,7 @@ MemMRASExcludeDIMM (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
index 5f64db5..89e16b0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
@@ -83,7 +83,7 @@ MemMLvDdr3 (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
@@ -143,7 +143,7 @@ MemMLvDdr3 (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes, taken into account of the
@@ -221,7 +221,7 @@ MemMLvDdr3PerformanceEnhPre (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Finalize the VDDIO for the board for performance enhancement.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c
index 4039ef6..f7e971b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c
@@ -78,7 +78,7 @@ MemMMctMemClr (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c
index 244420d..8ac3083 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c
@@ -116,7 +116,7 @@ MemMS3Save (
*/
extern MEM_NB_SUPPORT memNBInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -231,7 +231,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -281,7 +281,7 @@ MemMContextRestore (
return RefPtr->MemRestoreCtl;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Save all memory related data for S3.
@@ -347,7 +347,7 @@ MemMS3Save (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices that contains DQS timings
*
@@ -510,7 +510,7 @@ MemMRestoreDqsTimings (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function filters out other settings and only restores DQS timings.
@@ -619,7 +619,7 @@ MemMSetCSRNb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c
index 52a3a96..f04d85e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c
@@ -79,7 +79,7 @@ MemMInterleaveNodes (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c
index e825192..2472e79 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c
@@ -76,7 +76,7 @@ MemMOnlineSpare (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c
index a596a5e..4a3640a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c
@@ -91,7 +91,7 @@ MemMParallelTraining (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
index 770d36d..9e29e2c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
@@ -85,7 +85,7 @@ MemMStandardTraining (
*/
extern BUILD_OPT_CFG UserOptions;
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
index 2aacc91..dd7ff77 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
@@ -92,7 +92,7 @@ MemMUmaAlloc (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
index f2e5848..9f94e4e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
@@ -104,7 +104,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -303,7 +303,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
index 41ba55c..9110339 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
@@ -162,7 +162,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -254,7 +254,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -284,7 +284,7 @@ MemUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -310,7 +310,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -331,7 +331,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -359,7 +359,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -391,7 +391,7 @@ MemUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -481,7 +481,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -519,7 +519,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -557,7 +557,7 @@ GetMaxSolderedDownDimmsPerChannel (
return MaxSolderedDownDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -598,7 +598,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -636,7 +636,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -675,7 +675,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -713,7 +713,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
@@ -740,7 +740,7 @@ GetVarMtrrHiMsk (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns number of memclk converted from ns
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c
index 2bff126..0319b20 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c
@@ -109,7 +109,7 @@ MemNTotalSyncComponentsTN (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ MemNAutoConfigTN (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -308,7 +308,7 @@ MemNCapSpeedBatteryLifeTN (
NBPtr->NbPsCtlReg = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -362,7 +362,7 @@ MemNGetMaxLatParamsTN (
*DlyBiasPtr = (UINT16) N;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -481,7 +481,7 @@ MemNExitPhyAssistedTrainingTN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -520,7 +520,7 @@ MemNTotalSyncComponentsTN (
return P;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -586,7 +586,7 @@ MemNProgramNbPstateDependentRegistersTN (
MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -629,7 +629,7 @@ MemNBeforeDramInitTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function modifies CS interleaving low address according to several conditions for TN.
@@ -664,7 +664,7 @@ MemNCSIntLvLowAddrAdjTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -703,7 +703,7 @@ MemNReleaseNbPstateTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -797,7 +797,7 @@ MemNMemPstateStageChangeTN (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -861,7 +861,7 @@ MemNPowerDownCtlTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
index c5bf49f..8eee467 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c
index e48bfd2..10f5b57 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c
@@ -99,7 +99,7 @@ MemNIdentifyDimmConstructorTN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c
index 077359e..25d761c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c
@@ -94,7 +94,7 @@ RDATA_GROUP (G3_DXE)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -125,7 +125,7 @@ MemNInitializeMctTN (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -240,7 +240,7 @@ MemNFinalizeMctTN (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function create the HT memory map for TN
@@ -332,7 +332,7 @@ MemNHtMemMapInitTN (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -367,7 +367,7 @@ MemNGetUmaSizeTN (
return SizeOfUma;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -413,7 +413,7 @@ MemNAllocateC6StorageTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts NB pstate norbridge voltage for TN
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
index 60b214a..e248914 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
@@ -96,7 +96,7 @@ MemNGetODTDelaysTN (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -131,7 +131,7 @@ MemNOtherTimingTN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -274,7 +274,7 @@ MemNSetOtherTimingTN (
IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO );
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c
index 5211313..0c7d320 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c
@@ -121,10 +121,10 @@ MemNRdPosTrnTN (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -284,7 +284,7 @@ MemNInitPhyCompTN (
NBPtr->SwitchDCT (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -314,7 +314,7 @@ MemNBeforeDQSTrainingTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -388,7 +388,7 @@ MemNAfterDQSTrainingTN (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based RcvEn training of TN.
@@ -410,7 +410,7 @@ MemNOverrideRcvEnSeedTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function choose the correct PllLockTime for TN
@@ -433,7 +433,7 @@ MemNAdjustPllLockTimeTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based WL for TN.
@@ -460,7 +460,7 @@ MemNOverrideWLSeedTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -484,7 +484,7 @@ MemNPFenceAdjustTN (
MULTI_MPSTATE_COPY_TSEFO (NBPtr->NBRegTable, BFPhyFence);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -528,7 +528,7 @@ MemNProgramFence2RxDllTN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if RdDqsDly needs to be restarted for Trinity
@@ -603,7 +603,7 @@ MemNRdDqsDlyRestartChkTN (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training
@@ -633,7 +633,7 @@ MemNRdPosTrnTN (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips WrDatDly training when a retrain condition is just detected
@@ -679,7 +679,7 @@ MemNHookBfWrDatTrnTN (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets up output driver and write leveling mode in MR1 during WL
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c
index 05b13aa..e5b38f8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c
@@ -98,7 +98,7 @@ STATIC CONST UINT8 InstancesPerTypeTN[8] = {8, 3, 1, 2, 2, 0, 1, 1};
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedTn
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -130,7 +130,7 @@ MemNIsIdSupportedTN (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -317,7 +317,7 @@ MemNCmnGetSetFieldTN (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
index c11e90e..35dea08 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
@@ -832,7 +832,7 @@ VOID *MemS3RegListTN[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -925,7 +925,7 @@ MemS3ResumeConstructNBBlockTN (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -976,7 +976,7 @@ MemNS3GetRegLstPtrTN (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1007,7 +1007,7 @@ MemNS3GetDeviceRegLstTN (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1047,7 +1047,7 @@ MemNS3SetDfltPhyRegTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1080,7 +1080,7 @@ MemNS3SetDynModeChangeTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1109,7 +1109,7 @@ MemNS3SetPhyStatusRegTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1160,7 +1160,7 @@ MemNS3DisableChannelTN (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1207,7 +1207,7 @@ MemNS3ChangeMemPStateContextAndFlowNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1284,7 +1284,7 @@ MemNS3GetConPCIMaskTN (
DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1333,7 +1333,7 @@ MemNS3GetCSRTN (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1398,7 +1398,7 @@ MemNS3SetCSRTN (
IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index c566061..3272d29 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -109,7 +109,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -249,7 +249,7 @@ MemConstructNBBlockTN (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -416,7 +416,7 @@ MemNInitNBDataTN (
NBPtr->FamilySpecificHook[WLMR1] = MemNWLMR1TN;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -489,7 +489,7 @@ MemNInitDefaultsTN (
RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -512,7 +512,7 @@ MemNWritePatternTN (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -535,7 +535,7 @@ MemNReadPatternTN (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for TN
@@ -563,7 +563,7 @@ memNEnableTrainSequenceTN (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
index 63195e0..e39d394 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
@@ -91,7 +91,7 @@ extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -133,7 +133,7 @@ MemNInitNBDataNb (
NBPtr->GetBitField = MemNGetBitFieldNb;
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -241,7 +241,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -285,7 +285,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow
@@ -306,7 +306,7 @@ MemNTrainingFlowNb (
return TRUE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -328,7 +328,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -479,7 +479,7 @@ MemNInsDlyCompareTestPatternNb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow for UNB
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c
index 6fc9e6b..4b0609b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c
@@ -105,7 +105,7 @@ MemNS3GetDummyReadAddr (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -214,7 +214,7 @@ MemNS3ResumeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -266,7 +266,7 @@ MemNS3ResumeClientNb (
// Errata After S3 resume sequence
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -320,7 +320,7 @@ MemNS3ResumeUNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -415,7 +415,7 @@ MemNS3GetConPCIMaskNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -486,7 +486,7 @@ MemNS3GetConPCIMaskUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -532,7 +532,7 @@ MemNS3GetCSRNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -593,7 +593,7 @@ MemNS3SetCSRNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -616,7 +616,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -639,7 +639,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -663,7 +663,7 @@ MemNS3RestoreScrubNb (
MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -693,7 +693,7 @@ MemNS3DisNbPsDbgNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -724,7 +724,7 @@ MemNS3EnNbPsDbg1Nb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -752,7 +752,7 @@ MemNS3SetDynModeChangeNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -800,7 +800,7 @@ MemNS3DisableChannelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -827,7 +827,7 @@ MemNS3SetDisAutoCompUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -854,7 +854,7 @@ MemNS3SetPreDriverCalUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -880,7 +880,7 @@ MemNS3DctCfgSelectUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -928,7 +928,7 @@ MemNS3GetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -976,7 +976,7 @@ MemNS3SetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1016,7 +1016,7 @@ MemNS3SaveNBRegiserUnb (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1056,7 +1056,7 @@ MemNS3RestoreNBRegiserUnb (
LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1090,7 +1090,7 @@ MemNS3SetMemClkFreqValUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1132,7 +1132,7 @@ MemNS3ChangeMemPStateContextNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1160,7 +1160,7 @@ MemNS3SetPhyClkDllFineClientNb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1225,7 +1225,7 @@ MemNS3ForceNBP0Unb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1273,7 +1273,7 @@ MemNS3ReleaseNBPSUnb (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1356,7 +1356,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
index a3b5d76..2ceb650 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
@@ -120,7 +120,7 @@ MemNQuarterMemClk2NClkNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -223,7 +223,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -359,7 +359,7 @@ MemNPlatformSpecNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -439,7 +439,7 @@ MemNPlatformSpecUnb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -466,7 +466,7 @@ MemNDisableDCTNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -499,7 +499,7 @@ MemNDisableDCTClientNb (
MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -539,7 +539,7 @@ MemNDisableDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -577,7 +577,7 @@ MemNStartupDCTNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -655,7 +655,7 @@ MemNStartupDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemNChangeFrequencyHy:
@@ -793,7 +793,7 @@ MemNChangeFrequencyNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency the next level if it have not reached
@@ -857,7 +857,7 @@ MemNRampUpFrequencyNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency to target frequency
@@ -896,7 +896,7 @@ MemNRampUpFrequencyUnb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1009,7 +1009,7 @@ MemNProgramCycTimingsNb (
MemNSetBitFieldNb (NBPtr, BFASR, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1117,7 +1117,7 @@ MemNProgramCycTimingsClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1228,7 +1228,7 @@ MemNProgramCycTimingsUnb (
MemNDramPowerMngTimingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1256,7 +1256,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1290,7 +1290,7 @@ MemNGetMaxLatParamsNb (
*DlyBiasPtr += 1; // add 1 NCLK
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1350,7 +1350,7 @@ MemNSetMaxLatencyNb (
MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1385,7 +1385,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1415,7 +1415,7 @@ MemNAfterStitchMemNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1437,7 +1437,7 @@ MemNGet1KTFawTkNb (
return Tab1KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1459,7 +1459,7 @@ MemNGet2KTFawTkNb (
return Tab2KTfawTK[k];
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1489,7 +1489,7 @@ MemNQuarterMemClk2NClkNb (
*SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1535,7 +1535,7 @@ MemNTotalSyncComponentsNb (
return SubTotal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1563,7 +1563,7 @@ MemNSwapBitsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1612,7 +1612,7 @@ MemNSwapBitsUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -1698,7 +1698,7 @@ MemNProgramPlatformSpecNb (
MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1738,7 +1738,7 @@ MemNGetTrdrdNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1773,7 +1773,7 @@ MemNGetTwrwrNb (
return DCTPtr->Timings.Twrwr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1818,7 +1818,7 @@ MemNGetTwrrdNb (
return DCTPtr->Timings.Twrrd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1859,7 +1859,7 @@ MemNGetTrwtTONb (
return DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1883,7 +1883,7 @@ MemNGetTrwtWBNb (
return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1903,7 +1903,7 @@ MemNGetMemClkFreqIdNb (
return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1944,7 +1944,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1964,7 +1964,7 @@ MemNGetMemClkFreqIdClientNb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1984,7 +1984,7 @@ MemNGetMemClkFreqIdUnb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2012,7 +2012,7 @@ MemNGetMemClkFreqUnb (
return MemClkFreq;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2157,7 +2157,7 @@ MemNChangeFrequencyClientNb (
MemFInitTableDrive (NBPtr, MTAfterFreqChg);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -2311,7 +2311,7 @@ MemNChangeFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -2359,7 +2359,7 @@ MemNProgramNbPstateDependentRegistersUnb (
IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
@@ -2529,7 +2529,7 @@ MemNProgramNbPstateDependentRegistersClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2606,7 +2606,7 @@ MemNTotalSyncComponentsClientNb (
return (((P * MemClkPeriod + 1) / 2) + T);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2648,7 +2648,7 @@ MemNPhyPowerSavingClientNb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2719,7 +2719,7 @@ MemNPhyPowerSavingUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2792,7 +2792,7 @@ MemNSetASRSRTNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency as below:
@@ -2897,7 +2897,7 @@ MemNBeforePhyFenceTrainingClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency foras below:
@@ -2965,7 +2965,7 @@ MemNChangeNbFrequencyUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -2993,7 +2993,7 @@ MemNGetDramTermNb (
return DramTerm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3016,7 +3016,7 @@ MemNGetDramTermTblDrvNb (
return RttNom;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3036,7 +3036,7 @@ MemNGetDynDramTermNb (
return (NBPtr->PsPtr->DynamicDramTerm);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3059,7 +3059,7 @@ MemNGetDynDramTermTblDrvNb (
return RttWr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3083,7 +3083,7 @@ MemNGetMR0CLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3105,7 +3105,7 @@ MemNGetMR0WRNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3123,7 +3123,7 @@ MemNGetMR0WRTblDrvNb (
return (UINT32) (NBPtr->PsPtr->MR0WR << 9);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3145,7 +3145,7 @@ MemNGetMR2CWLNb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns MR2[CWL] value for UNB
@@ -3166,7 +3166,7 @@ MemNGetMR2CWLUnb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets Txp and Txpdll
@@ -3232,7 +3232,7 @@ MemNAdjustTxpdllClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to handle or switch NB Pstate for UNB
@@ -3369,7 +3369,7 @@ MemNChangeNbFrequencyWrapUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3421,7 +3421,7 @@ MemNSendMrsCmdUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3439,7 +3439,7 @@ MemNGetMR0CLTblDrvNb (
return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3497,7 +3497,7 @@ MemNSlot1MaxRdLatTrainClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -3540,7 +3540,7 @@ MemNDramPowerMngTimingNb (
MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 2] - 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets Rcv Fifo
@@ -3560,7 +3560,7 @@ MemTResetRcvFifoUnb (
MemNSetBitFieldNb (TechPtr->NBPtr, BFRstRcvFifo, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c
index 3e88a69..c0d4298 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c
@@ -209,7 +209,7 @@ MemNInitCPGUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -227,7 +227,7 @@ MemNInitCPGNb (
NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions of HW Rx En Training.
@@ -243,7 +243,7 @@ MemNInitDqsTrainRcvrEnHwNb (
{
NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables member functions of Hw Rx En Training.
@@ -266,7 +266,7 @@ MemNDisableDqsTrainRcvrEnHwNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes 9 or 18 cache lines continuously using GH CPG engine
@@ -315,7 +315,7 @@ MemNContWritePatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -407,7 +407,7 @@ MemNContReadPatternNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -433,7 +433,7 @@ MemNGenHwRcvEnReadsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes cache lines continuously using TCB CPG engine
@@ -510,7 +510,7 @@ MemNContWritePatternClientNb (
MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -566,7 +566,7 @@ MemNContReadPatternClientNb (
MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -591,7 +591,7 @@ MemNGenHwRcvEnReadsClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -614,7 +614,7 @@ MemNInitCPGClientNb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -640,7 +640,7 @@ MemNCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -665,7 +665,7 @@ MemNInsDlyCompareTestPatternClientNb (
return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -782,7 +782,7 @@ MemNPrepareRcvrEnDlySeedNb (
NBPtr->FamilySpecificHook[RegAccessFence] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of MEMCLKs
@@ -800,7 +800,7 @@ MemNWaitXMemClksNb (
MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Issues dummy TCB write read to zero out CL that is used for MemClr
@@ -828,7 +828,7 @@ MemNBeforeMemClrClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Activate command
@@ -862,7 +862,7 @@ MemNRrwActivateCmd (
NBPtr->WaitXMemClks (NBPtr, 75);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Precharge
@@ -902,7 +902,7 @@ MemNRrwPrechargeCmd (
// Wait 25 MEMCLKs
NBPtr->WaitXMemClks (NBPtr, 25);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -928,7 +928,7 @@ MemNGenHwRcvEnReadsUnb (
NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of reads from DRAM using the
@@ -1036,7 +1036,7 @@ MemNContReadPatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -1129,7 +1129,7 @@ MemNContWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results
@@ -1187,7 +1187,7 @@ MemNCompareTestPatternUnb (
return Pass;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for offset comparison results
@@ -1229,7 +1229,7 @@ MemNInsDlyCompareTestPatternUnb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -1255,7 +1255,7 @@ MemNInitCPGUnb (
NBPtr->DisableInfiniteWritePattern = MemNDisableInfiniteWritePatternUnb;
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes infinite writes to DRAM using the
@@ -1333,7 +1333,7 @@ MemNEnableInfiniteWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables the infinite stream of writes to DRAM using the
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c
index a4566bf..f45241f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnflow.c
@@ -108,7 +108,7 @@ MemNGetPORFreqLimitTblDrvNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -170,7 +170,7 @@ MemNInitMCTNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -200,7 +200,7 @@ MemNPlatformSpecificFormFactorInitTblDrvNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
@@ -233,7 +233,7 @@ MemNTechBlockSwitchNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -282,7 +282,7 @@ MemNInitDCTNb (
return FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
@@ -303,7 +303,7 @@ MemNCleanupDctRegsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c
index 17fc1a7..b47ed5a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c
@@ -103,7 +103,7 @@ MemNSetMTRRrangeNb (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -241,7 +241,7 @@ MemNSyncTargetSpeedNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -271,7 +271,7 @@ MemNSyncDctsReadyNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -407,7 +407,7 @@ MemNHtMemMapInitNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -453,7 +453,7 @@ MemNSyncAddrMapToAllNodesNb (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -484,7 +484,7 @@ MemNPowerDownCtlNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -550,7 +550,7 @@ MemNGetOptimalCGDDNb (
return CGDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -614,7 +614,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -689,7 +689,7 @@ GetTrainDlyFromHeapNb (
return TrainDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -805,7 +805,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -866,7 +866,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -961,7 +961,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1021,7 +1021,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1039,7 +1039,7 @@ MemNGetUmaSizeNb (
return 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1073,7 +1073,7 @@ MemNAllocateC6StorageClientNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -1143,7 +1143,7 @@ MemNAllocateC6StorageUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function readjusts TOPMEM and MTRRs after allocating storage for C6
@@ -1194,7 +1194,7 @@ MemNC6AdjustMSRs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Family-specific hook to override the DdrMaxRate value for families with a
@@ -1224,7 +1224,7 @@ MemNGetMaxDdrRateUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1249,7 +1249,7 @@ MemNAfterSaveRestoreUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c
index 060269e..81c1aae 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c
@@ -101,7 +101,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -125,7 +125,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -150,7 +150,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -168,7 +168,7 @@ MemNPhyFenceTrainingNb (
NBPtr->MemPPhyFenceTrainingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -274,7 +274,7 @@ MemNPhyFenceTrainingUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -354,7 +354,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -438,7 +438,7 @@ MemNInitPhyCompNb (
MemNSwitchDCTNb (NBPtr, CurrDct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -492,7 +492,7 @@ MemNBeforeDQSTrainingNb (
MemTEndTraining (NBPtr->TechPtr);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -528,7 +528,7 @@ MemNGetTrainDlyParmsNb (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -558,7 +558,7 @@ MemNGetTrainDlyParmsClientNb (
Parms->Mask = 0x03E;
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -590,7 +590,7 @@ MemNGetTrainDlyParmsUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -734,7 +734,7 @@ MemNcmnGetSetTrainDlyNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets or set DQS timing during training.
@@ -856,7 +856,7 @@ MemNcmnGetSetTrainDlyClientNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1027,7 +1027,7 @@ MemNcmnGetSetTrainDlyUnb (
}
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -1114,7 +1114,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determined the settings for the Reliable Read/Write engine
@@ -1179,7 +1179,7 @@ MemNSetupHwTrainingEngineUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1207,7 +1207,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -1233,7 +1233,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -1256,7 +1256,7 @@ MemNCSPerDelayNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -1299,7 +1299,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -1339,7 +1339,7 @@ MemNPhyVoltageLevelNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1358,7 +1358,7 @@ MemNPFenceAdjustUnb (
*Value16 += 2; //The Avg PRE value is subtracted by 6 only.
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1651,7 +1651,7 @@ MemNSetSkewMemClkUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function masks the RdDqsDly Bit 0 before writing to register for UNB.
@@ -1671,7 +1671,7 @@ MemNAdjustRdDqsDlyOffsetUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1753,7 +1753,7 @@ MemNCalcWrDqDqsEarlyClientNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1845,7 +1845,7 @@ MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1983,7 +1983,7 @@ MemNPhyPowerSavingMPstateUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets RxFifo pointer during Read DQS training
@@ -2008,7 +2008,7 @@ MemNResetRxFifoPtrClientNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts WrDqsBias before seed scaling
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c
index 2f863e6..1b3191e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -123,7 +123,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -155,7 +155,7 @@ MemNDctCfgSelectUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -178,7 +178,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -202,7 +202,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -261,7 +261,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -291,7 +291,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all DCTs regardless of if they are being enabled or not on a
@@ -319,7 +319,7 @@ MemNBrdcstSetUnConditionalNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -339,7 +339,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
@@ -500,7 +500,7 @@ MemNPollBitFieldNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -540,7 +540,7 @@ MemNChangeMemPStateContextNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates buffer for NB register table
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c
index 49166bd..8aa7642 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c
@@ -94,7 +94,7 @@ MemNHwWlPart2Nb (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -127,7 +127,7 @@ MemNDQSTiming3Nb (
}
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
@@ -199,7 +199,7 @@ memNSequenceDDR3Nb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
index 2f6ef5d..550b684 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
@@ -167,7 +167,7 @@ MemPTblDrvOverrideMR10OpSpeed (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -191,7 +191,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -239,7 +239,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -295,7 +295,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
@@ -312,7 +312,7 @@ MemPGetPORFreqLimitDef (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the seed value of WL and HW RxEn pass 1 training.
@@ -346,7 +346,7 @@ MemPGetPSCPass1Seed (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -401,7 +401,7 @@ MemPPSCFlow (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -453,7 +453,7 @@ MemPConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -489,7 +489,7 @@ MemPIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -534,7 +534,7 @@ MemPGetPsRankType (
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs the action for the rest of platform specific configuration such as
@@ -632,7 +632,7 @@ MemPPSCGen (
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function proceeds Table Driven Overriding.
@@ -859,7 +859,7 @@ MemPProceedTblDrvOverride (
return RetVal16;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the speed limit.
@@ -887,7 +887,7 @@ MemPTblDrvOverrideSpeedLimit (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODTs (RttNom and RttWr).
@@ -935,7 +935,7 @@ MemPTblDrvOverrideODT (
return TgtCS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODT patterns.
@@ -975,7 +975,7 @@ MemPTblDrvOverrideODTPattern (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the Ctrl Word 2 and 8.
@@ -1019,7 +1019,7 @@ MemPTblDrvOverrideRC2IBT (
return TgtDimm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1049,7 +1049,7 @@ MemPTblDrvOverrideMR0WR (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1077,7 +1077,7 @@ MemPTblDrvOverrideMR0CL (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR10[OperatingSpeed].
@@ -1110,7 +1110,7 @@ MemPTblDrvOverrideMR10OpSpeed (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
@@ -1152,7 +1152,7 @@ MemPCheckTblDrvOverrideConfig (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c
index 30406d1..481e798 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c
index 721731e..f9b2f9c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c
index a63bdc1..4284d02 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c
@@ -87,7 +87,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c
index a9fc1dc..8a052a6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c
@@ -107,7 +107,7 @@ MemPGetMaxFreqSupported (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts the value of max frequency supported from a input table and
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c
index b9ce51d..cc40b90 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c
@@ -92,7 +92,7 @@ MemPGetMR0WrCL (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c
index 78d225e..5cad339 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c
@@ -96,7 +96,7 @@ MemPGetODTPattern (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c
index 0831575..516a981 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c
@@ -88,7 +88,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC10 operating speed value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c
index b618d77..573e909 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RC2[IBT] value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c
index 65ee6ee..a2fccbb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c
@@ -97,7 +97,7 @@ MemPGetRttNomWr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c
index 116613a..5293d5d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c
@@ -98,7 +98,7 @@ MemPGetSAO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c
index 2a4d5e6..7b35241 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function extracts WL and HW RxEn seeds from PSCFG tables
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
index 335934b..980ff2c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index a868c4b..7d0ce4d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -207,7 +207,7 @@ MemTLrdimmInitHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes LRDIMM functions.
@@ -238,7 +238,7 @@ MemTLrdimmConstructor3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a Control word command to an LRDIMM Memory Buffer
@@ -278,7 +278,7 @@ MemTSendMBCtlWord3 (
MemTSendCtlWord3 (TechPtr, Rcw, Value);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends a an Extended Control word command to an LRDIMM Memory Buffer
@@ -348,7 +348,7 @@ MemTSendExtMBCtlWord3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the value of special RCW
@@ -522,7 +522,7 @@ MemTGetSpecialMBCtlWord3 (
return Value8;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -742,7 +742,7 @@ MemTLrDimmControlRegInit3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends LRDIMM Control Words to all LRDIMMS
@@ -848,7 +848,7 @@ MemTWLPrepareLrdimm3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to all physical ranks of an LRDIMM
@@ -940,7 +940,7 @@ MemTSendAllMRCmdsLR3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value for an LRDIMM
@@ -1005,7 +1005,7 @@ MemTEMRS1Lr3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value for an LRDIMM
@@ -1234,7 +1234,7 @@ MemTLrdimmBuf2DramTrain3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function copies trained delays of the first rank of a QR LRDIMM to the third rank
@@ -1314,7 +1314,7 @@ MemTLrdimmSyncTrainedDlys (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs LRDIMM specific tasks during Dimm Presence detection
@@ -1348,7 +1348,7 @@ MemTLrdimmPresence (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns LRDIMM Buffer ID Info from the SPD
@@ -1377,7 +1377,7 @@ MemTLrDimmGetBufferID (
return BufferID;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function implements special case Initialization hooks for LRDIMMs
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c
index d21dab3..d755d60 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -112,7 +112,7 @@ MemTAdjustTwrwr3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -138,7 +138,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
index 2d30833..ee3ae76 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -148,7 +148,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -223,7 +223,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -260,7 +260,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c
index 8814841..034959f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -203,7 +203,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -328,7 +328,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -381,7 +381,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -409,7 +409,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -460,7 +460,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
index acfd71d..7fcf1ed 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -113,7 +113,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -133,7 +133,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -446,7 +446,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -526,7 +526,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -604,7 +604,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -773,7 +773,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -920,7 +920,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -953,7 +953,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -996,7 +996,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1115,7 +1115,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1150,7 +1150,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c
index 482662a..08e7027 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -83,7 +83,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c
index 1ee1735..1584e35 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -133,7 +133,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -153,7 +153,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -177,7 +177,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -205,7 +205,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -239,7 +239,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -293,7 +293,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -345,7 +345,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -392,7 +392,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -541,7 +541,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -671,7 +671,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c
index d489c19..ffdbeb1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c
@@ -90,7 +90,7 @@ MemTDefaultTechnologyHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -105,7 +105,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -133,7 +133,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -167,7 +167,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -197,7 +197,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c
index a09ca7b..d20e712 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
index 46e591a..f3183fa 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
@@ -170,7 +170,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -217,7 +217,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -367,7 +367,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -618,7 +618,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -681,7 +681,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -710,7 +710,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -780,7 +780,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -824,7 +824,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c
index a141b9d..2a35790 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c
@@ -228,7 +228,7 @@ exce856 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -351,7 +351,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -380,7 +380,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -406,7 +406,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -443,7 +443,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -502,7 +502,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -580,7 +580,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -639,7 +639,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -666,7 +666,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -698,7 +698,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -722,7 +722,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -737,7 +737,7 @@ MemTMaxByteLanesByte ( VOID )
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -752,7 +752,7 @@ MemTDlyTableWidthByte ( VOID )
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -790,7 +790,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -842,7 +842,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -914,7 +914,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -975,7 +975,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay for UNB
@@ -1044,7 +1044,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the minimum or maximum gross dly among all the bytes.
@@ -1088,7 +1088,7 @@ MemTFindMinMaxGrossDlyByte (
return MinMaxGrossDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1244,7 +1244,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1278,7 +1278,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1412,7 +1412,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
@@ -1437,7 +1437,7 @@ MemTLoadInitialRcvEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay that are trained by PMU
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c
index 49ed5e8..2f080ef 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c
@@ -93,7 +93,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -142,7 +142,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c
index 5bad8bc..460133d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c
@@ -105,7 +105,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -126,7 +126,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -157,7 +157,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -242,7 +242,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
index 3406d76..0f92e51 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -162,7 +162,7 @@ MemTTrackRxEnSeedlessRdWrSmallWindBLError (
TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE;
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the RxEn delay
@@ -184,7 +184,7 @@ MemTRdPosRxEnSeedSetDly3 (
TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay), ByteLane), RcvEnDly);
TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the currert RxEn delay settings have failed
@@ -204,7 +204,7 @@ MemTRdPosRxEnSeedCheckRxEndly3 (
TechPtr->DqsRdWrPosSaved = 0;
MemTTrainDQSEdgeDetect (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training and if fails adjusts the RxEn Gross results for
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c
index b2e6b16..d50eaf2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttml.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c
index 0d3fedd..cb69d18 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c
@@ -103,7 +103,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -128,7 +128,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
index 4ad3ea8..c71c5a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
@@ -96,7 +96,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -127,7 +127,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
index 4be78a3..df789cc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
@@ -160,7 +160,7 @@ TableName[BitFieldIndex] = ( \
#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h
index 6a7e365..ca01e88 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h
@@ -184,7 +184,7 @@ PeekEventLog (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
index 9be2350..7990105 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
@@ -75,7 +75,7 @@ typedef struct {
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_CRAT_CONFIGURATION;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to generat CRAT cache affinity structure.
*
@@ -95,7 +95,7 @@ typedef VOID F_GENERATE_CRAT_CACHE (
/// Reference to a Method.
typedef F_GENERATE_CRAT_CACHE *PF_GENERATE_CRAT_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to generat CRAT TLB affinity structure.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
index 1aaa027..d56fa30 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
@@ -80,7 +80,7 @@ BOOLEAN MemMDefRetFalse (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
index ea29d06..eb10fbf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
@@ -61,7 +61,7 @@ RDATA_GROUP (G1_PEICC)
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
@@ -127,7 +127,7 @@ AmdAgesaDispatcher (
return (Status);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The host environment interface of callout.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
index 7100818..039b924 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
@@ -81,7 +81,7 @@
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to do the warm or cold reset.
@@ -108,7 +108,7 @@ AgesaDoReset (
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to allocate buffer in main system memory.
@@ -133,7 +133,7 @@ AgesaAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
@@ -156,7 +156,7 @@ AgesaDeallocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
@@ -181,7 +181,7 @@ AgesaLocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to launch APs
*
@@ -205,7 +205,7 @@ AgesaRunFcnOnAp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -229,7 +229,7 @@ AgesaReadSpd (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to read an SPD's content.
*
@@ -253,7 +253,7 @@ AgesaReadSpdRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -277,7 +277,7 @@ AgesaHookBeforeDramInitRecovery (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -300,7 +300,7 @@ AgesaHookBeforeDramInit (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -323,7 +323,7 @@ AgesaHookBeforeDQSTraining (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -346,7 +346,7 @@ AgesaHookBeforeExitSelfRefresh (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call the host environment interface to provide a user hook opportunity.
*
@@ -372,7 +372,7 @@ AgesaGetIdsData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE slot reset control
*
@@ -394,7 +394,7 @@ AgesaPcieSlotResetControl (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get VBIOS image
*
@@ -416,7 +416,7 @@ AgesaGetVbiosImage (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* OEM callout function for FCH data override
*
@@ -435,7 +435,7 @@ AgesaFchOemCallout (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Optional call to the host environment interface to change the external Vref for 2D Training.
*
@@ -457,7 +457,7 @@ AgesaExternal2dTrainVrefChange (
return Status;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Call to the host environment interface to change an external Voltage
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
index e774a0f..6b0b35d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
@@ -89,7 +89,7 @@ HeapGetBaseAddressInTempMem (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToTempRamAtPost
@@ -268,7 +268,7 @@ CopyHeapToTempRamAtPost (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CopyHeapToMainRamAtPost
@@ -395,7 +395,7 @@ CopyHeapToMainRamAtPost (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* HeapGetBaseAddressInTempMem
diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
index 19d1125..cfb8e60 100644
--- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
@@ -475,7 +475,7 @@ LibAmdFinit()
/* TODO: finit */
__asm__ volatile ("finit");
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -513,7 +513,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -551,7 +551,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -581,7 +581,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -614,7 +614,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -652,7 +652,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -690,7 +690,7 @@ LibAmdMemWrite (
break;
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -720,7 +720,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -753,7 +753,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -804,7 +804,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -859,7 +859,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -889,7 +889,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -922,7 +922,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -957,7 +957,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -990,7 +990,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1030,7 +1030,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1104,7 +1104,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1130,7 +1130,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1158,7 +1158,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1194,7 +1194,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1244,7 +1244,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1266,7 +1266,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1310,7 +1310,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
index 8b07c96..5bac879 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
@@ -96,7 +96,7 @@ F16KbInitializeC6 (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is C6 supported on this CPU
*
@@ -121,7 +121,7 @@ F16KbIsC6Supported (
return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable C6 on a family 16h Kabini CPU.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
index 6e2067a..8c66e63 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
@@ -100,7 +100,7 @@ SetF16KbCacheFlushOnHaltRegister (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Enable Cpu Cache Flush On Halt Function
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
index 4be045d..8ced05c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
@@ -91,7 +91,7 @@ F16KbPmCoreAfterResetPhase2OnCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 16h Kabini core 0 entry point for performing the necessary steps for core
* P-states after a warm reset has occurred.
@@ -156,7 +156,7 @@ F16KbPmCoreAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
* cores of a family 16h socket.
@@ -208,7 +208,7 @@ F16KbPmCoreAfterResetPhase1OnCore (
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
* cores of a family 16h socket.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
index 6961807..a38758b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
@@ -94,7 +94,7 @@ F16KbInitializeCpb (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for checking whether or not CPB is supported.
*
@@ -135,7 +135,7 @@ F16KbIsCpbSupported (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for enabling Core Performance Boost.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
index 6ed7006..e608a26 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
@@ -133,7 +133,7 @@ DmiF16KbGetExtClock (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16KbGetInfo
@@ -196,7 +196,7 @@ DmiF16KbGetInfo (
CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16KbGetT4ProcFamily
@@ -251,7 +251,7 @@ DmiF16KbGetT4ProcFamily (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16KbGetVoltage
@@ -293,7 +293,7 @@ DmiF16KbGetVoltage (
return (Voltage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16KbGetMemInfo
@@ -323,7 +323,7 @@ DmiF16KbGetMemInfo (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16KbGetExtClock
@@ -343,7 +343,7 @@ DmiF16KbGetExtClock (
return (EXTERNAL_CLOCK_100MHZ);
}
-/* -----------------------------------------------------------------------------*/
+
CONST PROC_FAMILY_TABLE ROMDATA ProcFamily16KbDmiTable =
{
// This table is for Processor family 16h Kabini
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
index 7b944cb..03bddf2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
@@ -84,7 +84,7 @@ STATIC CONST UINT16 ROMDATA stu1[] =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate microcode patch equivalent ID table.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
index fbf0baa..a159694 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
@@ -92,7 +92,7 @@ F16KbInitializeHtc (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
index 021d732..711792e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
@@ -97,7 +97,7 @@ F16KbLoadMicrocodePatchAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly (Before AP launch) to return the steps that a
* processor that uses the standard initialization steps should take.
@@ -121,7 +121,7 @@ GetF16KbEarlyInitBeforeApLaunchOnCoreTable (
*Table = F16KbEarlyInitBeforeApLaunchOnCoreTable;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that may be invoked at AmdCpuEarly (After AP launch) to return the steps that a
* processor that uses the standard initialization steps should take.
@@ -145,7 +145,7 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable (
*Table = F16KbEarlyInitAfterApLaunchOnCoreTable;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor for Family16h KB.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
index ea0fa5b..5e6bd35 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
@@ -89,7 +89,7 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate on a family 16h Kabini CPU.
* Implement BIOS Requirements for Initialization of C-states
@@ -141,7 +141,7 @@ F16KbInitializeIoCstate (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable CState on a family 16h Kabini core.
*
@@ -160,7 +160,7 @@ F16KbInitializeIoCstateOnCore (
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the size of CST object
*
@@ -204,7 +204,7 @@ F16KbGetAcpiCstObj (
return CStateAcpiObjSize;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to generate the C-State ACPI objects
*
@@ -333,7 +333,7 @@ F16KbCreateAcpiCstObj (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Routine to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
index 576d9ac..6fd67e1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
@@ -81,7 +81,7 @@ GetF16KbMicroCodePatchesStruct (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns a table containing the appropriate microcode patches.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
index 96b9b04..440487f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
@@ -230,7 +230,7 @@ CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* MSR special programming requirements for MSR_0000_0413
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
index b5712a3..2bc013c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
@@ -111,7 +111,7 @@ WaitForNbTransitionToComplete (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 16h Kabini core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
@@ -184,7 +184,7 @@ F16KbPmNbAfterReset (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 16h socket.
@@ -258,7 +258,7 @@ F16KbPmNbAfterResetOnCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmNbAfterResetOnCore to transition to the low NB P-state.
*
@@ -292,7 +292,7 @@ TransitionToNbLow (
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmNbAfterResetOnCore to transition to the high NB P-state.
*
@@ -324,7 +324,7 @@ TransitionToNbHigh (
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Support routine for F16KbPmAfterResetCore to wait for NB FID and DID to
* match a specific P-state.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
index 568fb10..02c87ed 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
@@ -1018,7 +1018,7 @@ CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable = {
(TABLE_ENTRY_FIELDS *) F16KbPciWorkarounds,
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Kabini processors.
*
@@ -1047,7 +1047,7 @@ SetDisCstateBoostBlockPstateUp (
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg1Low, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Kabini processors.
*
@@ -1091,7 +1091,7 @@ ScalingApmParamBaseOnCSampleTimer (
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&var1, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Workaround for Kabini processors.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
index 619eba6..ead32d2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
@@ -99,7 +99,7 @@ F16KbTransitionPstateCore (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family 16h Kabini core 0 entry point for performing the family 16h Processor-
* Systemboard Power Delivery Check.
@@ -291,7 +291,7 @@ F16KbPmPwrCheck (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Error handler called if any p-states were determined to be out
* of range for the mother board.
@@ -448,7 +448,7 @@ F16KbPmPwrCheckErrorHandler (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copies the contents of one P-State MSR to another.
*
@@ -471,7 +471,7 @@ F16KbPmPwrChkCopyPstate (
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Core-level transition Pstate
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
index c60a53b..054719b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
@@ -85,7 +85,7 @@ GetF16KbSysPmTable (
*/
/* Family 16h Kabini Only Table */
-/* ---------------------- */
+
CONST SYS_PM_TBL_STEP ROMDATA CpuF16KbSysPmTableArray[] =
{
/// @todo
@@ -123,7 +123,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF16KbSysPmTableArray[] =
IDS_F16_KB_PM_CUSTOM_STEP
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
index 77ecddf..3492840 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
@@ -88,7 +88,7 @@ F16KbPmVrmLowPowerModeEnable (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Power Status Indicator
*
@@ -125,7 +125,7 @@ F16KbInitializePsi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up PSI_L operation.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
index cec9aa4..daecea7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
@@ -140,7 +140,7 @@ F16KbGetPstateRegisterInfo (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
@@ -166,7 +166,7 @@ F16KbIsPstatePsdDependent (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get Pstate Transition Latency.
*
@@ -264,7 +264,7 @@ F16KbGetPstateTransLatency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
@@ -336,7 +336,7 @@ F16KbGetPstateFrequency (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
@@ -401,7 +401,7 @@ F16KbGetPstatePower (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate max state.
*
@@ -447,7 +447,7 @@ F16KbGetPstateMaxState (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to get CPU pstate register information.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
index e405162..3b38e7c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
@@ -141,7 +141,7 @@ F16KbSetDownCoreRegister (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get CPU pstate current.
*
@@ -192,7 +192,7 @@ F16KbGetProcIddMax (
return IsPstateEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set down core register on Kabini
*
@@ -292,7 +292,7 @@ CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F16KbCoreLeveling =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -328,7 +328,7 @@ F16KbGetCurrentNbFrequency (
return ReturnCode;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the node's minimum and maximum northbridge frequency.
*
@@ -423,7 +423,7 @@ F16KbGetMinMaxNbFrequency (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the NB clock on the desired node.
*
@@ -492,7 +492,7 @@ F16KbGetNbPstateInfo (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB pstate current.
*
@@ -543,7 +543,7 @@ F16KbGetNbIddMax (
return IsNbPsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of physical cores of current processor.
*
@@ -570,7 +570,7 @@ F16KbGetNumberOfPhysicalCores (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
@@ -600,7 +600,7 @@ F16KbGetApMailboxFromHardware (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get this AP's system core number from hardware.
*
@@ -626,7 +626,7 @@ F16KbGetApCoreNumber (
return ((Cpuid.EBX_Reg >> 24) & 0xFF);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -678,7 +678,7 @@ F16KbIsNbPstateEnabled (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state.
* - clear F5x1[6C:64]
@@ -809,7 +809,7 @@ F16KbNbPstateDis (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disable NB P-state on core.
* - clear MSRC001_00[6B:64][NbPstate].
@@ -838,7 +838,7 @@ F16KbNbPstateDisCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB Frequency Numerator in MHz
*
@@ -860,7 +860,7 @@ F16KbGetNbFreqNumeratorInMHz (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get NB Frequency Divisor
*
@@ -882,7 +882,7 @@ F16KbGetNbFreqDivisor (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate NB Frequency in MHz
*
@@ -918,7 +918,7 @@ F16KbCalculateNbFrequencyInMHz (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Convert VID to microvolts(uV)
*
@@ -941,7 +941,7 @@ F16KbCovertVidInuV (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Core/NB Idd Divisor
*
@@ -979,7 +979,7 @@ F16KbCmnGetIddDivisor (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate Core/NB current in mA
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
index bbc773f..dc94085 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
@@ -77,7 +77,7 @@ RDATA_GROUP (G3_DXE)
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Entry point for enabling Application Power Management
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
index c571b00..7afdd2b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
@@ -93,7 +93,7 @@ CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the Processor Name String register based on F5x194/198
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
index b455327..22c0edf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
@@ -99,7 +99,7 @@ CONST CACHE_INFO ROMDATA CpuF16CacheInfo =
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific properties of the cache, and its usage.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c
index 1529420..761a472 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c
@@ -78,7 +78,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DmiF16GetMaxSpeed
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
index 4d3fb74..6441e9a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -79,7 +79,7 @@ STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* BSC entry point for for adding MMIO map
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
index 43605e2..c480664 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
@@ -84,7 +84,7 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Disables the desired P-state.
*
@@ -112,7 +112,7 @@ F16DisablePstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
@@ -148,7 +148,7 @@ F16TransitionPstate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
@@ -189,7 +189,7 @@ F16GetTscRate (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initially launches the desired core to run from the reset vector.
*
@@ -243,7 +243,7 @@ F16LaunchApCore (
return (LaunchFlag);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
@@ -269,7 +269,7 @@ F16GetNbCofVidUpdate (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the Northbridge PState feature enabled?
*
@@ -315,7 +315,7 @@ F16IsNbPstateEnabled (
return FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set warm reset status and count
*
@@ -352,7 +352,7 @@ F16SetAgesaWarmResetFlag (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get warm reset status and count
*
@@ -384,7 +384,7 @@ F16GetAgesaWarmResetFlag (
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
index 69c2805..635e77d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
@@ -98,7 +98,7 @@ AMD_WHEA_INIT_DATA F16WheaInitData = {
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the family specific WHEA table properties.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c
index 9cf6393..c3db862 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c
@@ -79,7 +79,7 @@ EnableApmOnSocket (
*/
extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Application Power Management (APM) be enabled
*
@@ -116,7 +116,7 @@ IsApmFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Application Power Management (APM)
*
@@ -162,7 +162,7 @@ InitializeApmFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable APM
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h
index 2020694..8d1a0ff 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Application Power Management (APM) is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_APM_IS_SUPPORTED (
/// Reference to a Method.
typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable APM.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c
index 95bd0d7..4de545e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c
@@ -89,7 +89,7 @@ EnableC6OnSocket (
extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should C6 be enabled
*
@@ -127,7 +127,7 @@ IsC6FeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable the C6 C-state
*
@@ -202,7 +202,7 @@ InitializeC6Feature (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable C6 on it's socket.
*
@@ -231,7 +231,7 @@ EnableC6OnSocket (
StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h
index 074c072..3585f03 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if C6 is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_C6_IS_SUPPORTED (
/// Reference to a Method.
typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable C6.
*
@@ -104,7 +104,7 @@ typedef AGESA_STATUS F_C6_INIT (
/// Reference to a Method.
typedef F_C6_INIT *PF_C6_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to reload microcode patch after memory is initialized.
*
@@ -133,7 +133,7 @@ struct _C6_FAMILY_SERVICES {
PF_C6_RELOAD_MICROCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
};
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reload microcode patch after memory is initialized.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
index 49d6e16..ec4b2ab 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -107,7 +107,7 @@ InitializeCacheFlushOnHaltFeature (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should cache flush on halt be enabled
*
@@ -127,7 +127,7 @@ IsCFOHEnabled (
{
return (TRUE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InitializeCacheFlushOnHaltFeature
@@ -164,7 +164,7 @@ InitializeCacheFlushOnHaltFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
index b5a38b8..ad9110a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
@@ -142,7 +142,7 @@ IsPowerOfTwo (
IN UINT32 TestNumber
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will setup ROM execution cache.
*
@@ -428,7 +428,7 @@ AllocateExecutionCache (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates available L2 cache space for ROM execution.
*
@@ -521,7 +521,7 @@ AmdGetAvailableExeCacheSize (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function rounds a quotient up if the remainder is not zero.
*
@@ -546,7 +546,7 @@ Ceiling (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function calculates the amount of cache that has already been allocated on the
* executing core.
@@ -594,7 +594,7 @@ CalculateOccupiedExeCache (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function compares two memory regions for overlap and returns the combined
* Base,Size to describe the new combined region.
@@ -722,7 +722,7 @@ CompareRegions (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This local function tests the parameter for being an even power of two
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
index 5a30889..e14935c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
@@ -123,7 +123,7 @@ GetAcpiCditMain (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete CDIT table into a memory buffer.
@@ -147,7 +147,7 @@ CreateAcpiCdit (
return ((*(OptionCditConfiguration.CditFeature)) (StdHeader, PlatformConfig, CditPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the CDIT option is NOT requested.
@@ -172,7 +172,7 @@ GetAcpiCditStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete CDIT table into a memory buffer.
@@ -313,7 +313,7 @@ GetAcpiCditMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
index 57673ec..87d5670 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -98,7 +98,7 @@ CoreLevelingAtEarly (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should core leveling be enabled
*
@@ -126,7 +126,7 @@ IsCoreLevelingEnabled (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs core leveling for the system.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c
index 1071a3e..6e58af5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c
@@ -73,7 +73,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should CPB be enabled
*
@@ -115,7 +115,7 @@ IsCpbFeatureEnabled (
return IsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable core performance boost
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h
index ee6b350..c1e1d25 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if CPB is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_CPB_IS_SUPPORTED (
/// Reference to a Method.
typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable CPB.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
index 61946dc..c3bc6eb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
@@ -141,7 +141,7 @@ STATIC CRAT_HEADER ROMDATA CratHeaderStruct =
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Component Resource Affinity Table
@@ -164,7 +164,7 @@ CreateAcpiCrat (
return ((*(OptionCratConfiguration.CratFeature)) (StdHeader, CratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the CRAT option is NOT requested.
@@ -187,7 +187,7 @@ GetAcpiCratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Component Resource Affinity Table
@@ -256,7 +256,7 @@ GetAcpiCratMain (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add HSA Processing Unit entry.
*
@@ -312,7 +312,7 @@ MakeHSAProcUnitEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add memory entry.
*
@@ -388,7 +388,7 @@ MakeMemoryEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add cache entry.
*
@@ -411,7 +411,7 @@ MakeCacheEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add TLB entry.
*
@@ -434,7 +434,7 @@ MakeTLBEntry (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add CRAT entry.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
index e7bbc4d..59190fb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
@@ -117,7 +117,7 @@ ReleaseDmiBuffer (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* CreateDmiRecords
@@ -144,7 +144,7 @@ CreateDmiRecords (
return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoStub
*
@@ -170,7 +170,7 @@ GetDmiInfoStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* GetDmiInfoMain
*
@@ -438,7 +438,7 @@ GetDmiInfoMain (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetType4Type7Info
@@ -616,7 +616,7 @@ GetType4Type7Info (
return (Flag);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* DmiGetT4ProcFamilyFromBrandId
*
@@ -655,7 +655,7 @@ DmiGetT4ProcFamilyFromBrandId (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetNameString
@@ -690,7 +690,7 @@ GetNameString (
String[StringIndex] = '\0';
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IsSourceStrContainTargetStr
@@ -747,7 +747,7 @@ IsSourceStrContainTargetStr (
return IsContained;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* AdjustGranularity
@@ -782,7 +782,7 @@ AdjustGranularity (
return (CacheSize);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBufferStub
*
@@ -803,7 +803,7 @@ ReleaseDmiBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseDmiBuffer
*
@@ -826,7 +826,7 @@ ReleaseDmiBuffer (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* IntToString
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
index 8c56388..22b95b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -111,7 +111,7 @@ GetGlobalCpuFeatureListAddress (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* FeatureLeveling
@@ -187,7 +187,7 @@ FeatureLeveling (
*----------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* SaveFeatures
@@ -212,7 +212,7 @@ SaveFeatures (
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* WriteFeatures
@@ -237,7 +237,7 @@ WriteFeatures (
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetGlobalCpuFeatureListAddress
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h
index 1872aa2..bbf6931 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h
@@ -187,7 +187,7 @@ typedef enum {
MaxCpuFeature ///< Not a valid value, used for verifying input
} DISPATCHABLE_CPU_FEATURES;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Feature specific call to check if it is supported by the system.
*
@@ -206,7 +206,7 @@ typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
/// Reference to a Method.
typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* The feature's main entry point for enablement.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c
index 29d0b29..d5fe071 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c
@@ -84,7 +84,7 @@ EnableHtcOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE HtcFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Hardware Thermal Control (HTC) be enabled
*
@@ -121,7 +121,7 @@ IsHtcFeatureEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Hardware Thermal Control (HTC)
*
@@ -160,7 +160,7 @@ InitializeHtcFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable HTC
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h
index d6360b9..f66a847 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (HTC_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Hardware Thermal Control (HTC) is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_HTC_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HTC_IS_SUPPORTED *PF_HTC_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable HTC.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c
index 8ebdcc5..b595acf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c
@@ -85,7 +85,7 @@ EnableIoCstateOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should IO Cstate be enabled
* If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
@@ -132,7 +132,7 @@ IsIoCstateFeatureSupported (
return IsSupported;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable IO Cstate feature
*
@@ -168,7 +168,7 @@ InitializeIoCstateFeature (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* 'Local' core 0 task to enable IO Cstate on it's socket.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h
index a1d1e54..7eb1913 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h
@@ -166,7 +166,7 @@ typedef struct _ACPI_CST_GET_INPUT {
} ACPI_CST_GET_INPUT ;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if IO Cstate is supported.
*
@@ -184,7 +184,7 @@ typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable IO Cstate.
*
@@ -203,7 +203,7 @@ typedef AGESA_STATUS F_IO_CSTATE_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to return the size of ACPI C-State Objects
*
@@ -220,7 +220,7 @@ typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to create ACPI C-State Objects
*
@@ -237,7 +237,7 @@ typedef VOID F_IO_CSTATE_CREATE_CST (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check whether CSD object should be created.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h
index b012584..69cb5d2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h
@@ -63,7 +63,7 @@ AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES);
*/
#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if L3 Features are supported.
*
@@ -84,7 +84,7 @@ typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook before L3 features are initialized.
*
@@ -102,7 +102,7 @@ typedef VOID F_L3_FEATURE_BEFORE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -120,7 +120,7 @@ typedef VOID F_L3_FEATURE_DISABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to disable cache.
*
@@ -138,7 +138,7 @@ typedef VOID F_L3_FEATURE_ENABLE_CACHE (
/// Reference to a Method.
typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize L3 Features
*
@@ -156,7 +156,7 @@ typedef VOID F_L3_FEATURE_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific hook after L3 Features are initialized.
*
@@ -174,7 +174,7 @@ typedef VOID F_L3_FEATURE_AFTER_INIT (
/// Reference to a Method.
typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to save the L3 scrubber.
*
@@ -194,7 +194,7 @@ typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to restore the L3 scrubber.
*
@@ -214,7 +214,7 @@ typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL (
/// Reference to a Method.
typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if HT Assist is supported.
*
@@ -235,7 +235,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize HT Assist
*
@@ -253,7 +253,7 @@ typedef VOID F_HT_ASSIST_INIT (
/// Reference to a Method.
typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to provide non_optimal HT Assist support
*
@@ -274,7 +274,7 @@ typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
/// Reference to a Method.
typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if ATM Mode is supported.
*
@@ -295,7 +295,7 @@ typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize ATM mode
*
@@ -313,7 +313,7 @@ typedef VOID F_ATM_MODE_INIT (
/// Reference to a Method.
typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Neighbor Cache Mode is supported.
*
@@ -334,7 +334,7 @@ typedef BOOLEAN F_NBR_CACHE_IS_SUPPORTED (
/// Reference to a Method.
typedef F_NBR_CACHE_IS_SUPPORTED *PF_NBR_CACHE_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to Initialize Neighbor Cache
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h
index 0546639..b45bb2c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -58,7 +58,7 @@ AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if message-based C1e is supported.
*
@@ -79,7 +79,7 @@ typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
/// Reference to a Method.
typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable hardware C1e.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h
index 98f3df6..01dc567 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h
@@ -61,7 +61,7 @@ AGESA_FORWARD_DECLARATION (PREFETCH_MODE_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable prefetch mode.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c
index 50ddc31..355e587 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c
@@ -84,7 +84,7 @@ EnablePsiOnSocket (
extern CPU_FAMILY_SUPPORT_TABLE PsiFamilyServiceTable;
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Should Power Status Indicator (PSI) be enabled
*
@@ -133,7 +133,7 @@ IsPsiFeatureEnabled (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Enable Power Status Indicator (PSI)
*
@@ -172,7 +172,7 @@ InitializePsiFeature (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to enable PSI
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h
index 53cf75a..45d8c76 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h
@@ -59,7 +59,7 @@ AGESA_FORWARD_DECLARATION (PSI_FAMILY_SERVICES);
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Power Status Indicator (PSI) is supported.
*
@@ -82,7 +82,7 @@ typedef BOOLEAN F_PSI_IS_SUPPORTED (
/// Reference to a Method.
typedef F_PSI_IS_SUPPORTED *PF_PSI_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable PSI.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h
index dd27fa6..e1d9aca 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h
@@ -57,7 +57,7 @@ AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES);
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable P-state HPC mode
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c
index ab135b9..ac7a3bc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -964,7 +964,7 @@ CorePstateRegModify (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set msr on all cores of all nodes.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
index b744e07..2505a1e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
@@ -99,7 +99,7 @@ typedef struct {
IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
} S_CPU_AMD_PSTATE;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if PSD need to be generated.
*
@@ -121,7 +121,7 @@ typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if Pstate PSD is dependent.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c
index d2315f9..a6a0691 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c
@@ -133,7 +133,7 @@ ReleaseSlitBuffer (
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -157,7 +157,7 @@ CreateAcpiSlit (
return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SLIT option is NOT requested.
@@ -182,7 +182,7 @@ GetAcpiSlitStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function generates a complete SLIT table into a memory buffer.
@@ -320,7 +320,7 @@ GetAcpiSlitMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Find out the pointer to the BufferHandle which contains
@@ -348,7 +348,7 @@ AcpiSlitHBufferFind (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBufferStub
*
@@ -369,7 +369,7 @@ ReleaseSlitBufferStub (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* ReleaseSlitBuffer
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
index aa71216..8351adf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
@@ -141,7 +141,7 @@ STATIC
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -164,7 +164,7 @@ CreateAcpiSrat (
return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the SRAT option is NOT requested.
@@ -187,7 +187,7 @@ GetAcpiSratStub (
{
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will generate a complete Static Resource Affinity Table
@@ -300,7 +300,7 @@ GetAcpiSratMain (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will build Memory entry for current node.
@@ -511,7 +511,7 @@ STATIC
} // FillMemoryForCurrentNode()
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will add APIC entry.
*
@@ -547,7 +547,7 @@ STATIC
} // MakeApicEntry
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function will add Memory entry.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h
index 2bf6ba4..9b2bd54 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h
@@ -60,7 +60,7 @@ AGESA_FORWARD_DECLARATION (TDP_LIMIT_FAMILY_SERVICES);
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to check if TDP limiting is supported.
*
@@ -83,7 +83,7 @@ typedef BOOLEAN F_TDP_LIMIT_IS_SUPPORTED (
/// Reference to a Method.
typedef F_TDP_LIMIT_IS_SUPPORTED *PF_TDP_LIMIT_IS_SUPPORTED;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to enable TDP limiting.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
index 9aaae0c..03f6ab0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
@@ -97,7 +97,7 @@ GetAcpiWheaMain (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI table of WHEA and return the pointer to the table.
@@ -119,7 +119,7 @@ CreateAcpiWhea (
return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This is the default routine for use when the WHEA option is NOT requested.
@@ -145,7 +145,7 @@ GetAcpiWheaStub (
return AGESA_UNSUPPORTED;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create the ACPI tale of WHEA and return the pointer to the table.
@@ -248,7 +248,7 @@ GetAcpiWheaMain (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* It will create Bank structure for Hest table
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
index 9f303fc..151c045 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
@@ -149,7 +149,7 @@ RestoreConditionalMsrDevice (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -182,7 +182,7 @@ SaveDeviceListContext (
SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves all devices in the given device list.
*
@@ -279,7 +279,7 @@ SaveDeviceContext (
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a PCI device.
*
@@ -371,7 +371,7 @@ SavePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' PCI device.
*
@@ -466,7 +466,7 @@ SaveConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of an MSR device.
*
@@ -509,7 +509,7 @@ SaveMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Saves the context of a 'conditional' MSR device.
*
@@ -555,7 +555,7 @@ SaveConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the maximum amount of space required to store all raw register
* values for the given device list.
@@ -639,7 +639,7 @@ GetWorstCaseContextSize (
return (WorstCaseSize);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'before exiting self-refresh.'
*
@@ -700,7 +700,7 @@ RestorePreESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores all devices marked as 'after exiting self-refresh.'
*
@@ -760,7 +760,7 @@ RestorePostESRContext (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a PCI device.
*
@@ -877,7 +877,7 @@ RestorePciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' PCI device.
*
@@ -996,7 +996,7 @@ RestoreConditionalPciDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of an MSR device.
*
@@ -1059,7 +1059,7 @@ RestoreMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Restores the context of a 'conditional' MSR device.
*
@@ -1125,7 +1125,7 @@ RestoreConditionalMsrDevice (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1146,7 +1146,7 @@ GetNonMemoryRelatedDeviceList (
*NonMemoryRelatedDeviceList = NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to PCI register list translator.
*
@@ -1170,7 +1170,7 @@ S3GetPciDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' PCI register list translator.
*
@@ -1195,7 +1195,7 @@ S3GetCPciDeviceRegisterList (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to MSR register list translator.
*
@@ -1219,7 +1219,7 @@ S3GetMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Unique device ID to 'conditional' MSR register list translator.
*
@@ -1243,7 +1243,7 @@ S3GetCMsrDeviceRegisterList (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_PARAMS structure.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
index f293f0f..61e63bf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
@@ -96,7 +96,7 @@ SetRegistersFromTablesAfterApLaunch (
extern BUILD_OPT_CFG UserOptions;
extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
* An iterator for all the Family and Model Register Tables.
*
@@ -159,7 +159,7 @@ STATIC
return Entries;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compare counts to a pair of ranges.
*
@@ -190,7 +190,7 @@ IsEitherCountInRange (
((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
}
-/*-------------------------------------------------------------------------------------*/
+
/**
* Returns the performance profile features list of the currently running processor core.
*
@@ -263,7 +263,7 @@ GetPerformanceFeatures (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the MSR Register Entry.
*
@@ -294,7 +294,7 @@ SetRegisterForMsrEntry (
LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the PCI Register Entry.
*
@@ -345,7 +345,7 @@ SetRegisterForPciEntry (
LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Family Specific Workaround Register Entry.
*
@@ -374,7 +374,7 @@ SetRegisterForFamSpecificWorkaroundEntry (
Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Performance Profile PCI Register Entry.
*
@@ -413,7 +413,7 @@ SetRegisterForPerformanceProfileEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Core Counts Performance PCI Register Entry.
*
@@ -454,7 +454,7 @@ SetRegisterForCoreCountsPerformanceEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Processor Counts PCI Register Entry.
*
@@ -495,7 +495,7 @@ SetRegisterForProcessorCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts PCI Register Entry.
*
@@ -536,7 +536,7 @@ SetRegisterForComputeUnitCountsEntry (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the Compute Unit Counts MSR Register Entry.
*
@@ -569,7 +569,7 @@ SetMsrForComputeUnitCountsEntry (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Returns the platform features list of the currently running processor core.
*
@@ -663,7 +663,7 @@ GetPlatformFeatures (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks if a register table entry applies to the executing core.
*
@@ -711,7 +711,7 @@ DoesEntryMatchPlatform (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Checks register table entry type specific criteria to the platform.
*
@@ -755,7 +755,7 @@ DoesEntryTypeSpecificInfoMatch (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determine this core's Selector matches.
*
@@ -790,7 +790,7 @@ IsCoreSelector (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -875,7 +875,7 @@ SetRegistersFromTables (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
@@ -898,7 +898,7 @@ SetRegistersFromTablesBeforeApLaunch (
SetRegistersFromTables (&EarlyParams->PlatformConfig, PERFORM_TP_BEFORE_AP_LAUNCH, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
index 1f6341a..b4ecc5d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
@@ -120,11 +120,11 @@
*
*/
-/*------------------------------------------------------------------------------------------*/
+
/*
* Define the supported table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* These are the available types of table entries.
@@ -162,11 +162,11 @@ typedef enum {
TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
} TABLE_ENTRY_TYPE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Useful types and defines: Selectors, Platform Features, and type specific features.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Select tables for the current core.
@@ -640,11 +640,11 @@ typedef union {
COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
} HT_FREQ_COUNTS;
-/*------------------------------------------------------------------------------------------*/
+
/*
* The specific data for each table entry.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Make an extra type so we can use compilers that don't support designated initializers.
@@ -914,11 +914,11 @@ typedef struct {
PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
} HT_LINK_PCI_TYPE_ENTRY_DATA;
-/*------------------------------------------------------------------------------------------*/
+
/*
* A complete register table and table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* All the available entry data types.
@@ -969,11 +969,11 @@ typedef struct {
CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
} REGISTER_TABLE;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Describe implementers for table entries.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Implement the semantics of a Table Entry Type.
@@ -1000,11 +1000,11 @@ typedef struct {
PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
} TABLE_ENTRY_TYPE_DESCRIPTOR;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Non-union initializers for entry data which is not just UINT32.
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* A union of data types, that can be initialized with MSR data.
@@ -1066,11 +1066,11 @@ typedef struct {
FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-/*------------------------------------------------------------------------------------------*/
+
/*
* Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
*/
-/*------------------------------------------------------------------------------------------*/
+
/**
* Set the registers for this core based on entries in a list of Register Tables.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c
index 6213a7a..3ed0adb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c
@@ -197,7 +197,7 @@ ExecuteFinalHltInstruction (
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC.
*
@@ -281,7 +281,7 @@ LocalApicInitialization (
LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize the Local APIC at the AmdInitEarly entry point.
*
@@ -305,7 +305,7 @@ LocalApicInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for all APs in the system.
*
@@ -453,7 +453,7 @@ ApEntry (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'control byte' on the designated remote core.
*
@@ -482,7 +482,7 @@ ApUtilReadRemoteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'control byte' on the executing core.
*
@@ -507,7 +507,7 @@ ApUtilWriteControlByte (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the 'data dword' on the designated remote core.
*
@@ -531,7 +531,7 @@ ApUtilReadRemoteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes the 'data dword' on the executing core.
*
@@ -552,7 +552,7 @@ ApUtilWriteDataDword (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on the specified local core.
*
@@ -658,7 +658,7 @@ ApUtilRunCodeOnSocketCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Waits for a remote core's control byte value to either be equal or
* not equal to any number of specified values.
@@ -710,7 +710,7 @@ ApUtilWaitForCoreStatus (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the AP task on the executing core.
*
@@ -777,7 +777,7 @@ ApUtilTaskOnExecutingCore (
return (ReturnCode);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
*
@@ -823,7 +823,7 @@ ApUtilSetupIdtForHlt (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate the APIC ID for a given core.
*
@@ -898,7 +898,7 @@ GetLocalApicIdForCore (
*LocalApicId = CurrentLocalApicId;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely passes a buffer to the designated remote core.
*
@@ -979,7 +979,7 @@ ApUtilTransmitBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a buffer from the designated remote core.
*
@@ -1126,7 +1126,7 @@ RelinquishControlOfAllAPs (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* The last AGESA code that an AP performs
*
@@ -1175,7 +1175,7 @@ PerformFinalHalt (
ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads the APIC register on the designated remote core.
*
@@ -1223,7 +1223,7 @@ ApUtilRemoteRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes an APIC register on the executing core.
*
@@ -1252,7 +1252,7 @@ ApUtilLocalWrite (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Reads an APIC register on the executing core.
*
@@ -1283,7 +1283,7 @@ ApUtilLocalRead (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the 64-bit base address of the executing core's local APIC.
*
@@ -1305,7 +1305,7 @@ ApUtilGetLocalApicBase (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the unique ID of the input Socket/Core.
*
@@ -1338,7 +1338,7 @@ ApUtilCalculateUniqueId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Wakes up a core from the halted state.
*
@@ -1363,7 +1363,7 @@ ApUtilFireDirectedNmi (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely receives a pointer from the designated remote core.
*
@@ -1405,7 +1405,7 @@ ApUtilReceivePointer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Securely transmits a pointer to the designated remote core.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c
index 2c68971..9e30d67 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c
@@ -72,7 +72,7 @@ GetBistResults (
*----------------------------------------------------------------------------------------
*/
- /*---------------------------------------------------------------------------------------*/
+
/**
*
* This function checks the status of BIST and places the error status in the event log
@@ -145,7 +145,7 @@ CheckBistStatus (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Reads the lower 32 bits of the BIST register
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c
index d00a96f..db2980e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c
@@ -106,7 +106,7 @@ EarlyTableAfterApLaunch (
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
@@ -129,7 +129,7 @@ AmdCpuEarlyInitializer (
CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the early entry point
*
@@ -282,7 +282,7 @@ AmdCpuEarly (
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform early init table
*
@@ -314,7 +314,7 @@ PerformEarlyInitTable (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -358,7 +358,7 @@ McaInitialization (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform early init table after AP launch
*
@@ -381,7 +381,7 @@ EarlyTableAfterApLaunch (
PerformEarlyInitTable (EarlyTableOnCore, FamilySpecificServices, CpuEarlyParams, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize Machine Check Architecture registers
*
@@ -403,7 +403,7 @@ McaInitializationAtEarly (
McaInitialization (StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
@@ -439,7 +439,7 @@ ApUtilRunCodeOnAllLocalCoresAtEarly (
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c
index 53e6036..b846742 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c
@@ -94,7 +94,7 @@ GetEventLogHeapPointer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* External AGESA interface to read an Event from the Event Log.
*
@@ -131,7 +131,7 @@ AmdReadEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function prepares the Event Log for use.
@@ -168,7 +168,7 @@ EventLogInitialization (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function logs AGESA events into the event log.
@@ -246,7 +246,7 @@ PutEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer.
@@ -300,7 +300,7 @@ GetEventLog (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets event logs from the circular buffer without flushing the entry.
@@ -362,7 +362,7 @@ PeekEventLog (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This function gets the Event Log pointer.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c
index 46646ec..5b553d3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c
@@ -129,7 +129,7 @@ GetCpuServices (
extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the desired processor. This will be obtained by
@@ -168,7 +168,7 @@ GetLogicalIdOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of the executing core. This will be obtained by reading
@@ -191,7 +191,7 @@ GetLogicalIdOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Returns the logical ID of a processor with the given CPUID value. This
@@ -263,7 +263,7 @@ GetLogicalIdFromCpuid (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -290,7 +290,7 @@ GetCpuServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the desired processor's family specific services structure.
@@ -316,7 +316,7 @@ GetFeatureServicesOfSocket (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the executing core's family specific services structure.
@@ -339,7 +339,7 @@ GetCpuServicesOfCurrentCore (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -364,7 +364,7 @@ GetFeatureServicesOfCurrentCore (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -391,7 +391,7 @@ GetCpuServicesFromLogicalId (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Retrieves a pointer to the family specific services structure for a processor
@@ -415,7 +415,7 @@ GetFeatureServicesFromLogicalId (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Finds a family match in the given table, and returns the pointer to the
@@ -458,7 +458,7 @@ GetCpuServices (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Used to stub out various family specific tables of information.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
index de74390..1602734 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
@@ -846,7 +846,7 @@ typedef BOOLEAN F_GET_INTERNAL_LINK_EXTENDED_CAPABILITY (
typedef F_GET_INTERNAL_LINK_EXTENDED_CAPABILITY *PF_GET_INTERNAL_LINK_EXTENDED_CAPABILITY;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the interface to all cpu Family Specific Services.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c
index 7ec2c7a..3d10f5c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c
@@ -184,7 +184,7 @@ AmdIdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get a specified Core's APIC ID.
*
@@ -228,7 +228,7 @@ GetApicId (
return ReturnValue;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get Processor Module's PCI Config Space address.
*
@@ -272,7 +272,7 @@ GetPciAddress (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* "Who am I" for the current running core.
*
@@ -314,7 +314,7 @@ IdentifyCore (
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current Platform's number of Sockets, regardless of how many are populated.
*
@@ -333,7 +333,7 @@ GetPlatformNumberOfSockets ( VOID )
return TopologyConfiguration.PlatformNumberOfSockets;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the number of Modules to check presence in each Processor.
*
@@ -351,7 +351,7 @@ GetPlatformNumberOfModules ( VOID )
return TopologyConfiguration.PlatformNumberOfModules;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is a processor present in Socket?
*
@@ -395,7 +395,7 @@ IsProcessorPresent (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provide the number of installed processors (not Nodes! and not Sockets!)
*
@@ -438,7 +438,7 @@ GetNumberOfProcessors (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* For a specific Node, get its Socket and Module ids.
*
@@ -483,7 +483,7 @@ GetSocketModuleOfNode (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the current core's Processor APIC Index.
*
@@ -526,7 +526,7 @@ GetProcessorApicIndex (
return ProcessorApicIndex;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node number
*
@@ -548,7 +548,7 @@ GetCurrentNodeNum (
*Node = ApMailboxInfo.Fields.Node;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns Total number of active cores in the current socket
*
@@ -570,7 +570,7 @@ GetActiveCoresInCurrentSocket (
*CoreCount = TotalCoresCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the current core's node.
*
@@ -652,7 +652,7 @@ GetNumberOfCompUnitsInCurrentModule (
return ComputeUnitCount;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the Total number of active cores in the given socket.
*
@@ -691,7 +691,7 @@ GetActiveCoresInGivenSocket (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Provides the range of Cores in a Processor which are in a Module.
*
@@ -738,7 +738,7 @@ GetGivenModuleCoreRange (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the current running core number.
*
@@ -777,7 +777,7 @@ GetCurrentCore (
(MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns current node, and core number.
*
@@ -800,7 +800,7 @@ GetCurrentNodeAndCore (
GetCurrentCore (Core, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is the current core a primary core of it's node?
*
@@ -834,7 +834,7 @@ IsCurrentCorePrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns node id based on SocketId and ModuleId.
*
@@ -874,7 +874,7 @@ GetNodeId (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the cached AP Mailbox Info if available, or read the info from the hardware.
*
@@ -923,7 +923,7 @@ GetApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the Ap Mailbox info in our local heap for later use.
*
@@ -963,7 +963,7 @@ CacheApMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Cache the mailboxes for all nodes and store them in the BSP's heap
*
@@ -1016,7 +1016,7 @@ CacheBspMailbox (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Compute the degree of the system.
*
@@ -1054,7 +1054,7 @@ GetSystemDegree (
return ApMailboxes[Node].ApMailExtInfo.Fields.SystemDegree;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Spins until the number of microseconds specified have
* expired regardless of CPU operational frequency.
@@ -1084,7 +1084,7 @@ WaitMicroseconds (
} while ((CurrentTsc - InitialTsc) < NumberOfTicks);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* A boolean function determine executed CPU is BSP core.
*
@@ -1113,7 +1113,7 @@ IsBsp (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the compute unit mapping algorithm.
*
@@ -1186,7 +1186,7 @@ GetComputeUnitMapping (
return Result;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is current core the primary core of its compute unit?
*
@@ -1249,7 +1249,7 @@ IsCoreComputeUnitPrimary (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* This routine programs the registers necessary to get the PCI MMIO mechanism
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
index 7000a6e..fbd3faf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
@@ -80,7 +80,7 @@ DisableCf8ExtCfg (
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the late entry point
*
@@ -104,7 +104,7 @@ AmdCpuLate (
return (AGESA_SUCCESS);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clear EnableCf8ExtCfg on all socket
*
@@ -147,7 +147,7 @@ DisableCf8ExtCfg (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Calculate an ACPI style checksum
*
@@ -178,7 +178,7 @@ ChecksumAcpiTable (
Table->Checksum = Checksum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on every AP in the system.
@@ -233,7 +233,7 @@ RunLateApTaskOnAllAPs (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Run code on core 0 of every socket in the system.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
index 62404ad..35282ab 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
@@ -92,7 +92,7 @@ LoadMicrocodePatchAtEarly (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/* -----------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
@@ -163,7 +163,7 @@ LoadMicrocodePatch (
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* LoadMicrocode
@@ -207,7 +207,7 @@ LoadMicrocode (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* GetPatchEquivalentId
@@ -266,7 +266,7 @@ GetPatchEquivalentId (
return (FALSE);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* ValidateMicrocode
@@ -375,7 +375,7 @@ ValidateMicrocode (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* GetMicrocodeVersion
@@ -403,7 +403,7 @@ GetMicrocodeVersion (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Update microcode patch in current processor.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
index c32bae0..c0cff98 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
@@ -104,7 +104,7 @@ PstateCreateHeapInfo (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs CPU related initialization at the POST entry point
*
@@ -177,7 +177,7 @@ AmdCpuPost (
*---------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the address in system DRAM that should be used for p-state data
* gather and leveling.
@@ -204,7 +204,7 @@ GetPstateGatherDataAddressAtPost (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* AP task to sync memory subsystem MSRs with the BSC
*
@@ -231,7 +231,7 @@ SyncAllApMtrrToBsc (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Creates p-state information on the heap
*
@@ -349,7 +349,7 @@ SyncApMsrsToBsc (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* SyncVariableMTRR
*
@@ -389,7 +389,7 @@ SyncVariableMTRR (
SyncApMsrsToBsc (ApMsrSync, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* The function suppose to do any thing need to be done at the end of AmdInitPost.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c
index c377787..c51728e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c
@@ -99,7 +99,7 @@ GoToMemInitPstateCore (
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
@@ -156,7 +156,7 @@ PmInitializationAtEarly (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Performs the next step in the executing core 0's family specific power
* management table.
@@ -219,7 +219,7 @@ PerformThisPmStep (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing processor to the desired P-state.
*
@@ -246,7 +246,7 @@ GoToMemInitPstateCore0 (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Transitions the executing core to the desired P-state.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c
index 7cdb78e..0342e33 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
*
@@ -104,7 +104,7 @@ RunCodeOnAllSystemCore0sSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket BSC call to determine the maximum number of steps that any single
* processor needs to execute.
@@ -129,7 +129,7 @@ GetNumberOfSystemPmStepsPtrSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the frequency that the northbridges must run.
*
@@ -178,7 +178,7 @@ GetSystemNbCofSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
@@ -207,7 +207,7 @@ GetSystemNbCofVidUpdateSingle (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Single socket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
@@ -276,7 +276,7 @@ GetMinNbCofSingle (
ASSERT ((MinSysNbFreq != 0) && (MinP0NbFreq != 0));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get PCI Config Space Address for the current running core.
*
@@ -297,7 +297,7 @@ GetCurrPciAddrSingle (
return TRUE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Writes to all nodes on the executing core's socket.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
index acdf4ca..ab737c7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
@@ -72,7 +72,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits.
*
@@ -98,7 +98,7 @@ SetWarmResetFlag (
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will get the CPU register warm reset bits.
*
@@ -143,7 +143,7 @@ GetWarmResetFlag (
-/*---------------------------------------------------------------------------------------*/
+
/**
* Is this boot a warm reset?
*
@@ -193,7 +193,7 @@ IsWarmReset (
return WarmReset;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
index 68665fd..3ff31c2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
@@ -106,7 +106,7 @@ HeapGetBaseAddressInTempMem (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function initializes the heap for each CPU core.
*
@@ -235,7 +235,7 @@ HeapManagerInit (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -428,7 +428,7 @@ HeapAllocateBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Deallocates a previously allocated buffer in the heap
*
@@ -560,7 +560,7 @@ HeapDeallocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
@@ -668,7 +668,7 @@ HeapLocateBuffer (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get the heap base address
*
@@ -732,7 +732,7 @@ HeapGetBaseAddress (
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* DeleteFreeSpaceNode
@@ -791,7 +791,7 @@ DeleteFreeSpaceNode (
return;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* InsertFreeSpaceNode
@@ -844,7 +844,7 @@ InsertFreeSpaceNode (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Determines the base address of the executing core's heap.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
index 9fbce03..beca0df 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
@@ -95,7 +95,7 @@ typedef struct _AMD_ADD_MMIO_PARAMS {
AMD_MMIO_ATTRIBUTE Attributes;///< This indicates the attributes of the requested range.
} AMD_ADD_MMIO_PARAMS;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Family specific call to MMIO map manager.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c
index 7abb906..6a7ec7e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c
@@ -97,7 +97,7 @@ AllocateExecutionCacheInitializer (
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitEarly stage platform profile and user option input.
*
@@ -117,7 +117,7 @@ AmdEarlyPlatformConfigInit (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -145,7 +145,7 @@ AllocateExecutionCacheInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
*
* Initializer routine that will be invoked by the wrapper to initialize the input
@@ -180,7 +180,7 @@ AmdInitEarlyInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Perform initialization services required at the Early Init POST time point.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
index 35d856e..2cd839c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
@@ -112,7 +112,7 @@ AmdInitEnvInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_ENV function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
index 3aa7606..f808314 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
@@ -89,7 +89,7 @@ AmdLatePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitLate stage platform profile and user option input.
*
@@ -186,7 +186,7 @@ AmdInitLateDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_LATE function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
index b49ae31..3a0d2eb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
@@ -110,7 +110,7 @@ AmdInitMidInitializer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_MID function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
index 6409860..779f257 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
@@ -90,7 +90,7 @@ AmdPostPlatformConfigInit (
extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdInitPost stage platform profile and user option input.
*
@@ -198,7 +198,7 @@ AmdInitPostDestructor (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_POST function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
index 3de98a8..562cb36 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
@@ -87,7 +87,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
@@ -111,7 +111,7 @@ AmdInitResetExecutionCacheAllocateInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESET function.
*
@@ -222,7 +222,7 @@ AmdInitReset (
return AgesaStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Initialize defaults and options for Amd Init Reset.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c
index f742a88..7070502 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c
@@ -84,7 +84,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_INIT_RESUME function.
*
@@ -173,7 +173,7 @@ AmdInitResume (
return (AmdInitResumeStatus);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_INIT_RESUME function.
*
@@ -204,7 +204,7 @@ AmdInitResumeInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_INIT_RESUME function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
index 0f75e48..6cc7e00 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G3_DXE)
*/
extern CONST DISPATCH_TABLE ApDispatchTable[];
-/*---------------------------------------------------------------------------------------*/
+
/**
* Application Processor perform a function as directed by the BSC.
*
@@ -123,7 +123,7 @@ AmdLateRunApTask (
return ApLateTaskStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_LATE_RUN_AP_TASK function.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
index 1683353..2696225 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
@@ -84,7 +84,7 @@ AmdS3LateRestorePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
@@ -159,7 +159,7 @@ AmdS3LateRestore (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3LATE_RESTORE function.
*
@@ -191,7 +191,7 @@ AmdS3LateRestoreInitializer (
return AGESA_SUCCESS;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3LateRestore stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c
index 6e616e1..460c906 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c
@@ -102,7 +102,7 @@ AmdS3SavePlatformConfigInit (
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Main entry point for the AMD_S3_SAVE function.
*
@@ -313,7 +313,7 @@ AmdS3Save (
return ReturnStatus;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Constructor for the AMD_S3_SAVE function.
*
@@ -346,7 +346,7 @@ AmdS3SaveInitializer (
return AGESA_SUCCESS;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Destructor for the AMD_S3_SAVE function.
*
@@ -398,7 +398,7 @@ AmdS3SaveDestructor (
return ReturnStatus;
}
-/*------------------------------------------------------------------------------------*/
+
/**
* Initialize AmdS3Save stage platform profile and user option input.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
index add17da..9940100 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
@@ -73,7 +73,7 @@ extern BUILD_OPT_CFG UserOptions;
*----------------------------------------------------------------------------------------
*/
-/*------------------------------------------------------------------------------------*/
+
/**
* Common routine to initialize PLATFORM_CONFIGURATION.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
index c2f88bf..9997fdf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
@@ -76,7 +76,7 @@ FchTaskDummy (
IN VOID *DataPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return TRUE.
*
@@ -89,7 +89,7 @@ CommonReturnTrue ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return False.
*
@@ -101,7 +101,7 @@ CommonReturnFalse ( VOID )
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)zero.
*
@@ -114,7 +114,7 @@ CommonReturnZero8 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)zero.
*
@@ -127,7 +127,7 @@ CommonReturnZero32 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)zero.
*
@@ -140,7 +140,7 @@ CommonReturnZero64 ( VOID )
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT8)one.
*
@@ -153,7 +153,7 @@ CommonReturnOne8 ( VOID )
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT32)one.
*
@@ -166,7 +166,7 @@ CommonReturnOne32 ( VOID )
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return (UINT64)one.
*
@@ -178,7 +178,7 @@ CommonReturnOne64 ( VOID )
{
return 1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return NULL
*
@@ -190,7 +190,7 @@ CommonReturnNULL ( VOID )
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
@@ -202,7 +202,7 @@ CommonReturnAgesaSuccess ( VOID )
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_ERROR.
*
@@ -215,7 +215,7 @@ CommonReturnAgesaError ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Do Nothing.
*
@@ -225,7 +225,7 @@ CommonVoid ( VOID )
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ASSERT if this routine is called.
*
@@ -237,7 +237,7 @@ CommonAssert ( VOID )
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return AGESA_SUCCESS.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c
index fabfa85..97d887c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c
@@ -77,7 +77,7 @@ extern CONST UINTN InitializerCount;
*/
extern BUILD_OPT_CFG UserOptions;
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocate and initialize Config headers and Service Interface structures.
*
@@ -222,7 +222,7 @@ AmdCreateStruct (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Clears storage space from allocation for a parameter block of an
* AGESA software call entry.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
index 0b62877..fb0c3e3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
@@ -82,7 +82,7 @@ S3RestoreStateFromTable (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -99,7 +99,7 @@ S3ScriptRestore (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -116,7 +116,7 @@ S3ScriptRestoreStateStub (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -142,7 +142,7 @@ S3ScriptRestoreState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
index 02402c4..2c37c13 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
@@ -78,7 +78,7 @@ S3SaveStateExtendTableLenth (
IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -94,7 +94,7 @@ S3ScriptInit (
return OptionS3ScriptConfiguration.Init (StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -110,7 +110,7 @@ S3ScriptInitStateStub (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -138,7 +138,7 @@ S3ScriptInitState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -192,7 +192,7 @@ S3SaveStateExtendTableLenth (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize S3 Script framework
*
@@ -220,7 +220,7 @@ S3ScriptGetS3SaveTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -284,7 +284,7 @@ S3SaveStateSaveWriteOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 write opcode
*
@@ -358,7 +358,7 @@ S3SaveStateSaveReadWriteOp (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 poll opcode
*
@@ -434,7 +434,7 @@ S3SaveStateSavePollOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 info opcode
*
@@ -490,7 +490,7 @@ S3SaveStateSaveInfoOp (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 dispatch opcode
*
@@ -554,7 +554,7 @@ S3SaveStateSaveDispatchOp (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
@@ -599,7 +599,7 @@ S3SaveDebugOpcodeString (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save S3 debug support
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c
index 091552a..ead3e55 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c
@@ -325,7 +325,7 @@ RwAlink (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -356,7 +356,7 @@ ReadPmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO
*
@@ -387,7 +387,7 @@ WritePmio (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio - Read/Write PMIO
*
@@ -417,7 +417,7 @@ RwPmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO2
*
@@ -449,7 +449,7 @@ ReadPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO 2
*
@@ -481,7 +481,7 @@ WritePmio2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwPmio2 - Read/Write PMIO2
*
@@ -511,7 +511,7 @@ RwPmio2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read BIOSRAM
*
@@ -542,7 +542,7 @@ ReadBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write BIOSRAM
*
@@ -573,7 +573,7 @@ WriteBiosram (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Record SMI Status
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c
index 0905557..8b8d55f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c
@@ -43,7 +43,7 @@
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
*
@@ -89,7 +89,7 @@ ProgramPciByteTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
*
@@ -125,7 +125,7 @@ ProgramFchAcpiMmioTbl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
*
@@ -157,7 +157,7 @@ ProgramFchGpioTbl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
*
@@ -229,7 +229,7 @@ IsImcEnabled (
-/*----------------------------------------------------------------------------------------*/
+
/**
* SbSleepTrapControl - SB Sleep Trap Control
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c
index e187900..65c6838 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c
@@ -61,7 +61,7 @@ FchInitEnvEc (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* EnterEcConfig - Force EC into Config mode
*
@@ -83,7 +83,7 @@ EnterEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ExitEcConfig - Force EC exit Config mode
*
@@ -105,7 +105,7 @@ ExitEcConfig (
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ReadEc8 - Read EC register data
*
@@ -131,7 +131,7 @@ ReadEc8 (
LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RwEc8 - Read/Write EC register
*
@@ -158,7 +158,7 @@ RwEc8 (
WriteEc8 (Address, &Result, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* WriteEc8 - Write date into EC register
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
index f1ce3ab..e84e5c1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
@@ -63,7 +63,7 @@ AGESA_STATUS
FchEnvConstructor (
IN AMD_ENV_PARAMS *EnvParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitEnv - Config Fch before PCI emulation
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
index 1f1bdc1..db0b6dd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
@@ -58,7 +58,7 @@ AGESA_STATUS
FchLateConstructor (
IN AMD_LATE_PARAMS *LateParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitLate - Prepare Fch to boot to OS.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
index a44fa0c..1bb5bfa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
@@ -47,7 +47,7 @@
extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[];
extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[];
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
*
@@ -69,7 +69,7 @@ FchInitS3EarlyRestore (
FchDataPtr->Misc.S3Resume = 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c
index 16476db..e40cc51 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c
@@ -75,7 +75,7 @@ GnbLibDispatchFeatures (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dispatch feature table
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c
index e47f9d1..ad84b38 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c
@@ -80,7 +80,7 @@ GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early
*
@@ -100,7 +100,7 @@ GnbInitAtEarly (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Early before CPU
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c
index e8a6fe4..04dae5b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c
@@ -76,7 +76,7 @@ AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -114,7 +114,7 @@ GnbInitDataStructAtEnvDef (
GnbEnvConfigPtr->DpFixedVoltSwingType = UserOptions.CfgDpFixedVoltSwingType;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Env
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c
index 2385837..2385d48 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c
@@ -82,7 +82,7 @@ GnbInitAtLate (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Late
*
@@ -112,7 +112,7 @@ GnbInitDataStructAtLateDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Late post
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c
index 1606e53..3ed189e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c
@@ -76,7 +76,7 @@ AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Mid
*
@@ -94,7 +94,7 @@ GnbInitDataStructAtMidDef (
GnbMidConfigPtr->GnbIoapicAddress = UserOptions.CfgGnbIoapicAddress;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Mid post
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c
index 89c0c5e..3872615 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c
@@ -86,7 +86,7 @@ GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Default constructor of GNB configuration at Env
*
@@ -105,7 +105,7 @@ GnbInitDataStructAtPostDef (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post
*
@@ -126,7 +126,7 @@ GnbInitAtPost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Post after DRAM init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c
index c7d4710..deabfef 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c
@@ -68,7 +68,7 @@ GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at Reset
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c
index d705c7e..4cfade2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c
@@ -70,7 +70,7 @@ GnbInitAtS3Save (
IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GNB at S3 save
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 8f72255..e6b5317 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -84,7 +84,7 @@ GnbLibPciIndirectReadField (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers
*
@@ -110,7 +110,7 @@ GnbLibPciIndirectRead (
GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read GNB indirect registers field
*
@@ -139,7 +139,7 @@ GnbLibPciIndirectReadField (
*Value = (*Value >> FieldOffset) & Mask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers
*
@@ -167,7 +167,7 @@ GnbLibPciIndirectWrite (
GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write GNB indirect registers field
*
@@ -201,7 +201,7 @@ GnbLibPciIndirectWriteField (
GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write GNB indirect registers field
*
@@ -237,7 +237,7 @@ GnbLibPciIndirectRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI registers
*
@@ -264,7 +264,7 @@ GnbLibPciRMW (
GnbLibPciWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write I/O registers
*
@@ -291,7 +291,7 @@ GnbLibIoRMW (
GnbLibIoWrite (Address, Width, &Data, Config);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Indirect IO block read
*
@@ -325,7 +325,7 @@ GnbLibIndirectIoBlockRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOAPIC ID
*
@@ -347,7 +347,7 @@ GnbLiGetIoapicId (
return (UINT8) (Value >> 24);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write MMIO registers
*
@@ -376,7 +376,7 @@ GnbLibMemRMW (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate power of number
*
@@ -403,7 +403,7 @@ GnbLibPowerOf (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search buffer for pattern
*
@@ -441,7 +441,7 @@ GnbLibFind (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
@@ -493,7 +493,7 @@ GnbLibDebugDumpBuffer (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump buffer to HDTOUT
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index 2d93c3a..6114101 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -81,7 +81,7 @@ GnbLibCpuPciIndirectWrite (
IN VOID *Config
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU (DCT) indirect registers
*
@@ -109,7 +109,7 @@ GnbLibCpuPciIndirectRead (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write CPU (DCT) indirect registers
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index 061ae30..daef054 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -82,7 +82,7 @@ GnbLocateHeapBuffer (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap
*
@@ -116,7 +116,7 @@ GnbAllocateHeapBuffer (
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Allocates space for a new buffer in the heap and clear it
*
@@ -144,7 +144,7 @@ GnbAllocateHeapBufferAndClear (
return Buffer;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locates a previously allocated buffer on the heap.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index d0080f8..67d22de 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -67,10 +67,10 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*---------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
+
/**
* Write I/O Port
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 5d6e08f..e8948c5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write Memory/MMIO registers
*
@@ -94,7 +94,7 @@ GnbLibMemWrite (
LibAmdMemWrite (Width, Address, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Memory/MMIO registers
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
index 10ef0a3..6be31a6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -53,7 +53,7 @@
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device present
*
@@ -81,7 +81,7 @@ GnbLibPciIsDevicePresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is bridge
*
@@ -108,7 +108,7 @@ GnbLibPciIsBridgeDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is multifunction
*
@@ -135,7 +135,7 @@ GnbLibPciIsMultiFunctionDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if device is PCIe device
*
@@ -162,7 +162,7 @@ GnbLibPciIsPcieDevice (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCI capability pointer
*
@@ -200,7 +200,7 @@ GnbLibFindPciCapability (
}
return CapabilityPtr;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCIe extended capability pointer
*
@@ -238,7 +238,7 @@ GnbLibFindPcieExtendedCapability (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Scan range of device on PCI bus.
*
@@ -249,7 +249,7 @@ GnbLibFindPcieExtendedCapability (
* @param[in] ScanData Supporting data
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
@@ -306,7 +306,7 @@ GnbLibPciScan (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan all subordinate buses
*
@@ -332,7 +332,7 @@ GnbLibPciScanSecondaryBus (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe device type
*
@@ -343,7 +343,7 @@ GnbLibPciScanSecondaryBus (
*
* @retval PCIE_DEVICE_TYPE
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_DEVICE_TYPE
GnbLibGetPcieDeviceType (
@@ -362,7 +362,7 @@ GnbLibGetPcieDeviceType (
return PcieNotPcieDevice;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Save config space area
*
@@ -375,7 +375,7 @@ GnbLibGetPcieDeviceType (
* @param[in] StdHeader Standard header.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
GnbLibS3SaveConfigSpace (
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
index 460c40a..4f21f26 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -68,7 +68,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI registers
*
@@ -95,7 +95,7 @@ GnbLibPciWrite (
LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI registers
*
@@ -122,7 +122,7 @@ GnbLibPciRead (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll PCI reg
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
index bbbede8..c44aa77 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
@@ -59,7 +59,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall and save to script table
*
@@ -80,7 +80,7 @@ GnbLibStallS3Save (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Stall
*
@@ -107,7 +107,7 @@ GnbLibStall (
} while (TimeStampDelta < Microsecond);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Stall S3 script
*
@@ -127,7 +127,7 @@ GnbLibStallS3Script (
GnbLibStall (* ((UINT32*) Context), StdHeader);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific time stamp function
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index 3d1dbf2..77fce4c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -69,7 +69,7 @@
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -104,7 +104,7 @@ PcieFmConfigureEnginesLaneAllocation (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -141,7 +141,7 @@ PcieFmGetCoreConfigurationValue (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -176,7 +176,7 @@ PcieFmCheckPortPciDeviceMapping (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -208,7 +208,7 @@ PcieFmDebugGetCoreConfigurationString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -238,7 +238,7 @@ PcieFmDebugGetWrapperNameString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -269,7 +269,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
@@ -304,7 +304,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -335,7 +335,7 @@ PcieFmMapPortPciAddress (
return AGESA_ERROR;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get total number of silicons/wrappers/engines for this complex
*
@@ -366,7 +366,7 @@ PcieFmGetComplexDataLength (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -393,7 +393,7 @@ PcieFmBuildComplexConfiguration (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -424,7 +424,7 @@ PcieFmGetLinkSpeedCap (
return PcieGen1;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get native PHY lane bitmap
*
@@ -454,7 +454,7 @@ PcieFmGetNativePhyLaneBitmap (
return 0x0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -483,7 +483,7 @@ PcieFmSetLinkSpeedCap (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SB port info
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
index 8ec5ba8..e54ffd3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
@@ -72,7 +72,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if IOMMU unit present and enabled
*
@@ -99,7 +99,7 @@ GnbFmCheckIommuPresent (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create IVRS entry
*
@@ -129,7 +129,7 @@ GnbFmCreateIvrsEntry (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map graphics engine to display path
*
@@ -160,7 +160,7 @@ GfxFmMapEngineToDisplayPath (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate COF for DFS out of Main PLL
*
@@ -189,7 +189,7 @@ GfxFmCalculateClock (
return 200*100;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable GFX controller
*
@@ -214,7 +214,7 @@ GfxFmDisableController (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set idle voltage mode for GFX
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
index 258d460..892f631 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -79,7 +79,7 @@ GfxConfigEnvInterface (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
index ed2c94c..01c9644 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -95,7 +95,7 @@ GfxConfigDebugDump (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable GMM Access
*
@@ -158,7 +158,7 @@ GfxEnableGmmAccess (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get UMA info
*
@@ -188,7 +188,7 @@ GfxGetUmaInfo (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate UMA configuration data
*
@@ -216,7 +216,7 @@ GfxLocateConfigData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Debug dump
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
index 56d1b5b..8ba1ab3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
@@ -76,7 +76,7 @@ GfxConfigMidInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update GFX config info at ENV
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index e5a163b..cc5cf18 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -78,7 +78,7 @@ GfxConfigPostInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate UMA configuration data
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
index 08c12c0..79c1351 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -85,7 +85,7 @@ GfxScanPcieDevice (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get information about all discrete GFX card in system
*
@@ -116,7 +116,7 @@ GfxGetDiscreteCardInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index 74eba23..884f42d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -234,7 +234,7 @@ UINT8 ConnectorNumerArray[] = {
// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, DP-to-LVDS)
6, 1, 6, 6, 6, 1, 1, 2
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -308,7 +308,7 @@ EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
0x260,
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -342,7 +342,7 @@ GfxIntegratedExtDisplayDeviceInfo (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors
*
@@ -390,7 +390,7 @@ GfxIntegratedEnumerateAllConnectors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -428,7 +428,7 @@ GfxIntegratedDdiInterfaceCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate all display connectors for specific display device type.
*
@@ -508,7 +508,7 @@ GfxIntegratedEnumConnectorsForDevice (
return ConnectorEnumInfo.Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -566,7 +566,7 @@ GfxIntegratedCopyDisplayInfo (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump display path settings
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
index 5eea787..16098d9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
@@ -96,7 +96,7 @@ GfxInitSsid (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
*
*
@@ -112,7 +112,7 @@ GfxLibIsControllerPresent (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Gfx SSID Registers
*
@@ -159,7 +159,7 @@ GfxInitSsid (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
@@ -190,7 +190,7 @@ GfxLibCopyMemToFb (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set iGpu VGA mode
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
index ac7659c..f5d431d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
@@ -83,7 +83,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init V3 Support for eDP to Lvds translators
*
@@ -121,7 +121,7 @@ GfxIntegrateducEDPToLVDSRxIdCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate V3 NCLK clock
*
@@ -151,7 +151,7 @@ GfxLibGetNclkV3 (
return ((10000 * (NbFid + 4)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init V3 Nb p-State MemclkFreq
*
@@ -193,7 +193,7 @@ GfxFillNbPstateMemclkFreqV3 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init V3 NbPstateVid
*
@@ -218,7 +218,7 @@ GfxFillNbPStateVidV3 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy memory content to FB
*
@@ -264,7 +264,7 @@ GfxIntegratedInfoTable289_fun (
}
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC VOID
GfxIntegratedInfoTable318_fun (
@@ -313,7 +313,7 @@ GfxIntegratedInfoTable318_fun (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
*
@@ -469,7 +469,7 @@ GfxIntInfoTableInitV3 (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump gfx integrated info table
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
index 3a4fa1d..6530688 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
@@ -78,7 +78,7 @@ CONST UINT16 GfxMemClockFrequencyDefinitionTableV3 [][8] = {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Extract DRAM frequency
*
@@ -101,7 +101,7 @@ GfxLibExtractDramFrequencyV3 (
return GfxMemClockFrequencyDefinitionTableV3[Encoding / 8][Encoding % 8];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable GMM Access for gBIF BAR Arrangement
*
@@ -148,7 +148,7 @@ GfxEnableGmmAccessV3 (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power Up/Down iGPU
*
@@ -176,7 +176,7 @@ GfxRequestGPUPowerV3 (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine number of audio ports for each connector
*
@@ -211,7 +211,7 @@ GfxIntAudioEpEnumCallback (
IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enumerate audio endpoint in all display connectors.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
index 4bccb13..c19ee8e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
@@ -122,7 +122,7 @@ GfxIntDebugDumpPpTable (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create new software state
*
@@ -146,7 +146,7 @@ GfxPwrPlayCreateSwState (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC UINT8
GfxPwrPlayTable192_fun (
@@ -169,7 +169,7 @@ GfxPwrPlayTable192_fun (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC UINT8
GfxPwrPlayTable224_fun (
@@ -204,7 +204,7 @@ GfxPwrPlayTable256_fun (
SwStateArray->SW_STATE_fld7[SwStateArray->SW_STATE_fld6++] = DpmStateIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy SW state info to PPTable
*
@@ -241,7 +241,7 @@ GfxPwrPlayAttachStateInfoBlock (
PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray);
return StateArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy clock info to PPTable
*
@@ -274,7 +274,7 @@ GfxPwrPlayAttachClockInfoBlock (
return ClockInfoArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Copy non clock info to PPTable
*
@@ -309,7 +309,7 @@ GfxPwrPlayAttachNonClockInfoBlock (
return NonClockInfoArray;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if state valid
*
@@ -334,7 +334,7 @@ GfxPwrPlayIsF1dStateValid (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC VOID
GfxPwrPlayTable437_fun (
@@ -412,7 +412,7 @@ GfxPwrPlayTable437_fun (
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC UINT8
GfxPwrPlayAddEclkState (
@@ -437,7 +437,7 @@ GfxPwrPlayAddEclkState (
return PpWorkspace->NumOfVceClockEnties++;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add ECLK state
*
@@ -467,7 +467,7 @@ GfxPwrPlayAddEclkVoltageRecord (
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC UINT8
GfxPwrPlayTable588_fun (
@@ -498,7 +498,7 @@ GfxPwrPlayTable588_fun (
return PpWorkspace->NumOfUvdClockEntries++;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add Uvd voltage record
*
@@ -528,7 +528,7 @@ GfxPwrPlayAddUvdVoltageRecord (
return PpWorkspace->NumOfUvdClkVoltLimitEntries++;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Add Samu voltage record
*
@@ -567,7 +567,7 @@ GfxPwrPlayAddSamuVoltageRecord (
return PpWorkspace->PP_WORKSPACE_V2_fld15++;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach extended header
*
@@ -588,7 +588,7 @@ GfxPwrPlayAttachExtendedHeaderBlock (
return ExtendedHeader;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach Vce Rev Block
*
@@ -608,7 +608,7 @@ GfxPwrPlayAttachVceTableRevBlock (
return VceTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE clock info block
*
@@ -638,7 +638,7 @@ GfxPwrPlayAttachVceClockInfoBlock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE voltage limit block
*
@@ -668,7 +668,7 @@ GfxPwrPlayAttachVceVoltageLimitBlock (
return VceClockVoltageLimitTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach VCE state block
*
@@ -697,7 +697,7 @@ GfxPwrPlayAttachVceStateTableBlock (
return VceStateTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach Uvd Rev Block
*
@@ -717,7 +717,7 @@ GfxPwrPlayAttachUvdTableRevBlock (
return UvdTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach UVD clock info block
*
@@ -747,7 +747,7 @@ GfxPwrPlayAttachUvdClockInfoBlock (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach UVD voltage limit block
*
@@ -777,7 +777,7 @@ GfxPwrPlayAttachUvdVoltageLimitBlock (
return UvdClockVoltageLimitTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach SAMU Rev Block
*
@@ -798,7 +798,7 @@ GfxPwrPlayAttachSamuTableRevBlock (
return VceTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach SAMU voltage limit block
*
@@ -829,7 +829,7 @@ GfxPwrPlayAttachSamuVoltageLimitBlock (
return SamuClockVoltageLimitTable;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach Sclk Volt Dep Block
*
@@ -864,7 +864,7 @@ GfxPwrPlayTable956_fun (
return v0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build VCE state info
*
@@ -926,7 +926,7 @@ GfxPwrPlayBuildVceStateTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC VOID
GfxPwrPlayBuildUvdClockTable (
@@ -956,7 +956,7 @@ GfxPwrPlayBuildUvdClockTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build SAMU info
*
@@ -985,7 +985,7 @@ GfxPwrPlayBuildSamuTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC VOID
GfxPwrPlayTable1122_fun (
@@ -1014,7 +1014,7 @@ GfxPwrPlayTable1122_fun (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build PP table
*
@@ -1117,7 +1117,7 @@ GfxPwrPlayBuildTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Dump PP table
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c
index 1f45bf9..8127f29 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c
@@ -71,7 +71,7 @@ PcieAlibGetBaseTableKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get base SSDT table
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c
index 6e6d138..ace509f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c
@@ -87,7 +87,7 @@ GfxEnvInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GFX straps.
*
@@ -166,7 +166,7 @@ GfxStrapsEnvInitKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Env Post.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c
index 9271fce..43fe827 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c
@@ -82,7 +82,7 @@ extern GNB_TABLE ROMDATA GfxGmcFeature1EnableKB [];
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize Fb location
*
@@ -123,7 +123,7 @@ GfxGmcInitializeFbLocationKB (
IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitializeFbLocationKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize sequencer model
*
@@ -150,7 +150,7 @@ GfxGmcInitializeHubAndCitfSteeringKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Stutter Mode with/without power-gating
*
@@ -197,7 +197,7 @@ GfxGmcEnableStutterModePowerGatingKB (
IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcEnableStutterModePowerGatingKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*
*
@@ -226,7 +226,7 @@ GfxGmcSecureGarlicAccessKB (
GnbRegisterWriteKB (GnbHandle, 0x12, 0x2878, &v3, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize C6 aperture location
*
@@ -271,7 +271,7 @@ GfxGmcInitializeC6LocationKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GMC
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c
index 8f1bfe4..c16f917 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c
@@ -106,7 +106,7 @@ CONST UINT8 DdiLaneConfigArrayKB [][4] = {
{19, 16, 6, 6}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize display path for given engine
*
@@ -182,7 +182,7 @@ GfxMapEngineToDisplayPathKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init KB Nb p-State MemclkFreq
*
@@ -257,7 +257,7 @@ GfxFillNbPstateMemclkFreqKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Calculate ulGMCRestoreResetTime
*
@@ -298,7 +298,7 @@ GfxCalculateRestoreResetTimeKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init KB HTC Data
*
@@ -337,7 +337,7 @@ GfxFillHtcDataKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Init Sclk <-> VID table
*
@@ -395,7 +395,7 @@ GfxIntInfoTableInitSclkTableKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
*
@@ -488,7 +488,7 @@ GfxIntInfoTableInitKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build integrated info table
* GMC FB access requred
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
index 949f65e..4efd42b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
@@ -89,7 +89,7 @@ GfxIsVbiosPostedKB (
IN GFX_PLATFORM_CONFIG *Gfx
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable GFX controller
*
@@ -112,7 +112,7 @@ GfxDisableControllerKB (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get system PLL COF
*
@@ -131,7 +131,7 @@ GfxLibGetSystemPllCofKB (
return 100 * (((v0 >> 1) & 0x3F) + 0x10);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Calculate COF for DFS out of Main PLL
*
@@ -167,7 +167,7 @@ GfxCalculateClockKB (
return (((SystemPllCof * 100) + (Divider - 1)) / Divider);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if Video BIOS has posted or not
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
index 8064964..b43e29b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
@@ -88,7 +88,7 @@ GfxMidInterfaceKB (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Mid Post.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c
index 2bf0949..7e6dcef 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c
@@ -81,7 +81,7 @@ GfxPostInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init GFX at Post.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
index f39d730..4303615 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
@@ -99,7 +99,7 @@ typedef struct {
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GMC
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c
index 68f07a9..c84ff19 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c
@@ -145,7 +145,7 @@ GnbEarlyInitKB129_fun (
}
-/*----------------------------------------------------------------------------------------*/
+
STATIC VOID
GnbEarlyInitKB180_fun (
IN AMD_CONFIG_PARAMS *StdHeader
@@ -165,7 +165,7 @@ GnbEarlyInitKB180_fun (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Package Power Support
*
@@ -203,7 +203,7 @@ GnbInitPkgPowerKB (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request VDDB Pmin
*
@@ -253,7 +253,7 @@ GnbRequestVddNbPminKB (
return;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize GFX straps.
*
@@ -299,7 +299,7 @@ GfxStrapsEarlyInitKB (
IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Gfx gBIF
*
@@ -336,7 +336,7 @@ GfxGBifEnableKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* GNB init at early post
*
@@ -389,7 +389,7 @@ GnbEarlyInterfaceKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* GNB init at earlier post
*
@@ -431,7 +431,7 @@ GnbEarlierInterfaceKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
OptionGnbInstall581 (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c
index 5842afc..ec71be6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c
@@ -85,7 +85,7 @@ GnbEnvInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Dynamic Wake
* ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
@@ -132,7 +132,7 @@ GnbOrbDynamicWakeKB (
StdHeader
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* HTC Data
*
@@ -181,7 +181,7 @@ GnbFillHtcData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* LHTC Data
*
@@ -229,7 +229,7 @@ GnbUpdateLhtcData (
IDS_HDT_CONSOLE (GNB_TRACE, "GnbUpdateLhtcData Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* GNB init at env
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
index 89202ae..faae400 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
@@ -929,7 +929,7 @@ F1_TABLE_KB PPTableKB = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load F1 Table KB
*
@@ -971,7 +971,7 @@ NbF1LoadF1TableKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb load f1 table
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c
index 6eef700..aec7e9e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c
@@ -88,7 +88,7 @@ GnbMidInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
*
*
@@ -115,7 +115,7 @@ GnbIsF1dStateValid (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* LCLK DPM Initialization
*
@@ -352,7 +352,7 @@ GnbLclkDpmInitKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Post Init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
index 62ad1a3..2ed29c5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
@@ -77,7 +77,7 @@ GnbPostInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c
index 6b2b7a2..f20416e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c
@@ -84,7 +84,7 @@ GnbRegisterWriteKBDump (
);
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to read all register spaces.
*
@@ -305,7 +305,7 @@ GnbRegisterReadKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to write all register spaces.
*
@@ -528,7 +528,7 @@ GnbRegisterWriteKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Routine to dump all write register spaces.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
index cc3a741..3f25ac2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
@@ -94,7 +94,7 @@ GnbUraStreamSetKB (
IN UINT32 CombinedCount
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
@@ -145,7 +145,7 @@ GnbUraGetKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
@@ -205,7 +205,7 @@ GnbUraSetKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
index 94c731a..500dc7c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
@@ -98,7 +98,7 @@ REG_FIELD_TABLE_STRUCT UraTableKB = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method to locate register table.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c
index 96a2378..3cb04e9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c
@@ -379,7 +379,7 @@ PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get length of data block for complex
*
@@ -402,7 +402,7 @@ PcieGetComplexDataLengthKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build configuration
*
@@ -424,7 +424,7 @@ PcieBuildComplexConfigurationKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* get native PHY lane bitmap
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
index 67fc836..18c7dae 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
@@ -153,7 +153,7 @@ APIC_DEVICE_INFO ROMDATA DefaultIoapicConfig [] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -192,7 +192,7 @@ PcieConfigurePcieEnginesLaneAllocation (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -229,7 +229,7 @@ PcieConfigureDdiEnginesLaneAllocation (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -274,7 +274,7 @@ PcieConfigureEnginesLaneAllocationKB (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration value
*
@@ -323,7 +323,7 @@ PcieGetCoreConfigurationValueKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if engine can be remapped to Device/function number requested by user
* defined engine descriptor
@@ -356,7 +356,7 @@ PcieCheckPortPciDeviceMappingKB (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get core configuration string
*
@@ -388,7 +388,7 @@ PcieDebugGetCoreConfigurationStringKB (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get wrapper name
*
@@ -414,7 +414,7 @@ PcieDebugGetWrapperNameStringKB (
return " !!! Something Wrong !!!";
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get register address name
*
@@ -446,7 +446,7 @@ PcieDebugGetHostRegAddressSpaceStringKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if the lane can be muxed by link width requested by user
* defined engine descriptor
@@ -496,7 +496,7 @@ PcieCheckPortPcieLaneCanBeMuxedKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -553,7 +553,7 @@ PcieMapPortPciAddressKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Map engine to specific PCI device address
*
@@ -600,7 +600,7 @@ PcieSetPortPciAddressMapKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build default SB configuration descriptor
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
index b8a2d0d..5be4998 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
@@ -89,7 +89,7 @@ PcieEarlyInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set port device/function mapping
*
@@ -110,7 +110,7 @@ PciePortMapInitCallbackKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Static init for various registers.
*
@@ -138,7 +138,7 @@ PcieEarlyStaticInitKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init core registers.
*
@@ -180,7 +180,7 @@ PcieEarlyCoreInitKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Pcie Phy Isolation
*
@@ -267,7 +267,7 @@ PciePhyIsolationKB (
UINT8 LaneMuxSelectorArrayKB[] = { 7, 6, 5, 4, 3, 2, 1, 0 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate mux array index
*
@@ -292,7 +292,7 @@ PcieTopologyLocateMuxIndexKB (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply lane mux
*
@@ -378,7 +378,7 @@ PcieTopologyApplyLaneMuxKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -449,7 +449,7 @@ PcieTopologyExecuteReconfigKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply Misc settings for given wrapper
*
@@ -562,7 +562,7 @@ PcieMiscInitKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMiscInitKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Switch to PCIe Native Gen1 PLL.
*
@@ -594,7 +594,7 @@ PcieNativeGen1PLLSwitchKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Init prior training.
*
@@ -646,7 +646,7 @@ PcieEarlyInitCallbackKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -688,7 +688,7 @@ PcieEarlyInitKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set misc slot capability
*
@@ -745,7 +745,7 @@ PcieLinkSetSlotCapKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -802,7 +802,7 @@ PcieEarlyPortInitCallbackKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -850,7 +850,7 @@ DdiEarlyPortInitCallbackKB (
IDS_HDT_CONSOLE (GNB_TRACE, "DdiEarlyPortInitCallbackKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -889,7 +889,7 @@ PcieEarlyPortInitKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Early Post Init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
index 380484df..82434cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
@@ -71,7 +71,7 @@ PcieEnvInterfaceKB (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Env Init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
index 154621e..6f8707c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
@@ -95,7 +95,7 @@ UINT8
PcieMaxPayloadKB (
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -154,7 +154,7 @@ PciePifPllConfigureKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down unused lanes and plls
*
@@ -183,7 +183,7 @@ PciePwrPowerDownUnusedLanesKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanesKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request boot up voltage
*
@@ -251,7 +251,7 @@ PcieSetVoltageKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL power up latency
*
@@ -270,7 +270,7 @@ PciePifGetPllPowerUpLatencyKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get max link speed capability supported by this port
*
@@ -316,7 +316,7 @@ PcieGetLinkSpeedCapKB (
return LinkSpeedCapability;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Family specific time stamp function
*
@@ -346,7 +346,7 @@ GnbTimeStampKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Limit MaxPayload to 256 for x1 ports
*
@@ -370,7 +370,7 @@ PcieMaxPayloadKB (
return MaxPayload;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Select master PLL
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c
index e1bc450..937634f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c
@@ -83,7 +83,7 @@ PcieMidInterfaceKB (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -117,7 +117,7 @@ PcieMidPortInitCallbackKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init ASPM on all active ports
*
@@ -180,7 +180,7 @@ PcieMidAspmInitCallbackKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidAspmInitCallbackKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -229,7 +229,7 @@ PcieMidPortInitKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clock gating
*
@@ -364,7 +364,7 @@ PciePwrClockGatingKB (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingKB Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Per wrapper Pcie Late Init.
*
@@ -387,7 +387,7 @@ PcieMidInitCallbackKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Late Init
*
@@ -416,7 +416,7 @@ PcieMidInitKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Mid Init
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c
index a56d7cb..ff4824d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c
@@ -91,7 +91,7 @@ PcieLateRestoreInitKBS3Script (
IN VOID* Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -129,7 +129,7 @@ PciePostPortInitCallbackKB (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all ports
*
@@ -203,7 +203,7 @@ PciePostS3PortInitCallbackKB (
PcieTrainingSetPortState (Engine, State, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -230,7 +230,7 @@ PciePostEarlyPortInitKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -259,7 +259,7 @@ PciePostPortInitKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Master procedure to init various features on all active ports
*
@@ -288,7 +288,7 @@ PciePostS3PortInitKB (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Init
*
@@ -317,7 +317,7 @@ PciePostInitKB (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -356,7 +356,7 @@ PciePostEarlyInterfaceKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -400,7 +400,7 @@ PciePostInterfaceKB (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe Post Init
*
@@ -446,7 +446,7 @@ PciePostS3InterfaceKB (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIe S3 restore
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
index ee0c506..1e298ce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
@@ -75,7 +75,7 @@ GnbNbIoapicInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init IOAPIC on GNB port
*
@@ -121,7 +121,7 @@ IoapicInitCallbackV5 (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to Enable IOAPIC on GNB
*
@@ -185,7 +185,7 @@ IoapicEnableCallbackV5 (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB IOAPIC
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index 81faddf..887c314 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -86,7 +86,7 @@ GnbSmuServiceRequestV4S3Script (
IN VOID *Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check a PCIE device to see if it supports phantom functions
*
@@ -111,7 +111,7 @@ GnbCheckPhantomFuncSupport (
return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -167,7 +167,7 @@ GnbTopologyInfoScanCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOMMU topology info
*
@@ -199,8 +199,8 @@ GnbGetTopologyInfoV4 (
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* SMU firmware download
*
@@ -211,7 +211,7 @@ GnbGetTopologyInfoV4 (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get IOMMU PCI address
*
@@ -233,7 +233,7 @@ GnbGetIommuPciAddressV4 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnitID Clumping
*
@@ -287,7 +287,7 @@ GnbClumpUnitIdV4 (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Config GNB to prevent LPC deadlock scenario
*
@@ -332,7 +332,7 @@ GnbLpcDmaDeadlockPreventionV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable IOMMU base address. (MMIO space )
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c
index 7a55ef2..ef9616c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c
@@ -97,7 +97,7 @@ UINT8
GnbLocateHighestVidIndexV5 (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init NB set top of memory
*
@@ -197,7 +197,7 @@ GnbSetTomV5 (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of highest SCLK VID
*
@@ -233,7 +233,7 @@ GnbLocateHighestVidIndexV5 (
return MaxVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the index of lowest SCLK VID
*
@@ -267,7 +267,7 @@ GnbLocateLowestVidIndexV5 (
return MinVidIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the highest SCLK VID (high voltage)
*
@@ -291,7 +291,7 @@ GnbLocateHighestVidCodeV5 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the lowest SCLK VID (low voltage)
*
@@ -313,7 +313,7 @@ GnbLocateLowestVidCodeV5 (
return PpF1Array->PP_FUSE_ARRAY_V2_fld32[MinVidIndex];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Translate VID code to millivolt with two fraction bits
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
index 870f55c..d4aad14 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
@@ -119,7 +119,7 @@ PcieAlibUpdatePcieData (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create ACPI ALIB SSDT table
*
@@ -139,7 +139,7 @@ PcieAlibV2Feature (
return PcieAlibBuildAcpiTableV2 (StdHeader, &LateParamsPtr->AcpiAlib);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Build ALIB ACPI table
*
@@ -231,7 +231,7 @@ PcieAlibBuildAcpiTableV2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update MMIO info
*
@@ -283,7 +283,7 @@ PcieAlibUpdateGnbData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update MMIO info
*
@@ -339,7 +339,7 @@ PcieAlibUpdateVoltageData (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update PCIe info
*
@@ -394,7 +394,7 @@ PcieAlibUpdatePcieData (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to update PCIe port data
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
index f9c5c79..c439d8f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
@@ -119,7 +119,7 @@ PcieAspmInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -305,7 +305,7 @@ excel950_fun1 (
return (Value >> 10) & 3;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -338,7 +338,7 @@ PcieAspmPortInitCallback (
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Interface to enable Clock Power Managment
*
@@ -348,7 +348,7 @@ PcieAspmPortInitCallback (
*
* @retval AGESA_STATUS
*/
- /*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieAspmInterface (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
index 82f97ac..48c8831 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
@@ -69,7 +69,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Clock Power Managment on function of the device
*
@@ -79,7 +79,7 @@
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC VOID
PcieClkPmEnableOnFunction (
IN PCI_ADDR Function,
@@ -100,7 +100,7 @@ PcieClkPmEnableOnFunction (
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* check capability of intire device including its functions
*
@@ -111,7 +111,7 @@ PcieClkPmEnableOnFunction (
*
* @retval TRUE - Device support Clock Power Managment
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC BOOLEAN
PcieClkPmCheckDeviceCapability (
IN PCI_ADDR Device,
@@ -148,7 +148,7 @@ PcieClkPmCheckDeviceCapability (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Clock power managment on device
*
@@ -158,7 +158,7 @@ PcieClkPmCheckDeviceCapability (
* @param[in] StdHeader Standard configuration header
*
*/
- /*----------------------------------------------------------------------------------------*/
+
STATIC VOID
PcieClkPmEnableOnDevice (
IN PCI_ADDR Device,
@@ -183,7 +183,7 @@ PcieClkPmEnableOnDevice (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device
*
@@ -233,7 +233,7 @@ PcieClkPmCallback (
return ScanStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Confiugure Clock Power Managment
*
@@ -259,7 +259,7 @@ PcieClkPmPortInitConfigure (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -290,7 +290,7 @@ PcieClkPmPortInitCallback (
}
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Interface to enable Clock Power Managment
*
@@ -300,7 +300,7 @@ PcieClkPmPortInitCallback (
*
* @retval AGESA_STATUS
*/
- /*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieClkPmInterface (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
index e245837..15c48c9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -71,7 +71,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GNB handle
*
@@ -96,7 +96,7 @@ GnbGetHandle (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get GNB socket ID
*
@@ -111,7 +111,7 @@ GnbGetSocketId (
return PcieConfigGetParentComplex (GnbHandle)->SocketId;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Get PCI_ADDR of GNB
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index d8b1c00..0ffce95 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -109,7 +109,7 @@ AGESA_STATUS
PcieConfigurationMap (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration topology
*
@@ -183,7 +183,7 @@ PcieConfigurationInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Create internal PCIe configuration topology
*
@@ -254,7 +254,7 @@ PcieConfigurationMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -406,7 +406,7 @@ PcieConfigProcessUserConfig (
return ResultComplexConfig;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate global PCIe configuration data
*
@@ -433,7 +433,7 @@ PcieLocateConfigurationData (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attache descriptors
*
@@ -461,7 +461,7 @@ PcieConfigAttachDescriptors (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Attach configurations of two GNB to each other.
*
@@ -489,7 +489,7 @@ PcieConfigAttachComplexes (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update configuration data
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 5d2af03..7f93c0d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* get Master Lane of PCIe port engine
*
@@ -100,7 +100,7 @@ PcieConfigGetPcieEngineMasterLane (
return MasterLane;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of core lanes
*
@@ -120,7 +120,7 @@ PcieConfigGetNumberOfCoreLane (
return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable engine
*
@@ -140,7 +140,7 @@ PcieConfigDisableEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable all engines on wrapper
*
@@ -166,7 +166,7 @@ PcieConfigDisableAllEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get engine PHY lanes bitmap
*
@@ -188,7 +188,7 @@ PcieConfigGetEnginePhyLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of phy lanes
*
@@ -212,7 +212,7 @@ PcieConfigGetNumberOfPhyLane (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get port configuration signature for given wrapper and core
*
@@ -241,7 +241,7 @@ PcieConfigGetConfigurationSignature (
return ConfigurationSignature;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check Port Status
*
@@ -260,7 +260,7 @@ PcieConfigCheckPortStatus (
return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set/Reset port status
*
@@ -283,7 +283,7 @@ PcieConfigUpdatePortStatus (
return Engine->InitStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all descriptor of specific type
*
@@ -322,7 +322,7 @@ PcieConfigRunProcForAllDescriptors (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all wrappers in topology
*
@@ -360,7 +360,7 @@ PcieConfigRunProcForAllWrappers (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute callback on all engine in topology
*
@@ -394,7 +394,7 @@ PcieConfigRunProcForAllEngines (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get parent descriptor of specific type
*
@@ -418,7 +418,7 @@ PcieConfigGetParent (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get child descriptor of specific type
*
@@ -442,7 +442,7 @@ PcieConfigGetChild (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get peer descriptor of specific type
*
@@ -467,7 +467,7 @@ PcieConfigGetPeer (
return Descriptor;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check is engine is active or potentially active
*
@@ -494,7 +494,7 @@ PcieConfigIsActivePcieEngine (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate SB engine on wrapper
*
@@ -520,7 +520,7 @@ PcieConfigLocateSbEngine (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump engine configuration
*
@@ -600,7 +600,7 @@ PcieConfigEngineDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump wrapper configuration
*
@@ -640,7 +640,7 @@ PcieConfigWrapperDebugDump (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump configuration to debug out
*
@@ -710,7 +710,7 @@ PcieConfigDebugDump (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to user engine descriptor
*
@@ -756,7 +756,7 @@ PcieUserDescriptorConfigDump (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Helper function to dump input configuration to debug out
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 2f35947..cb28f22 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -100,7 +100,7 @@ PcieInputParserGetLengthOfPcieEnginesList (
IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of complexes in platform topology configuration
*
@@ -124,7 +124,7 @@ PcieInputParserGetNumberOfComplexes (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of PCIe engines in given complex
*
@@ -149,7 +149,7 @@ PcieInputParserGetLengthOfPcieEnginesList (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of DDI engines in given complex
*
@@ -175,7 +175,7 @@ PcieInputParserGetLengthOfDdiEnginesList (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get number of engines in given complex
*
@@ -197,7 +197,7 @@ PcieInputParserGetNumberOfEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -217,7 +217,7 @@ PcieInputParserGetComplexDescriptor (
return &ComplexList[Index];
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Complex descriptor by index from given Platform configuration
*
@@ -246,7 +246,7 @@ PcieInputParserGetComplexDescriptorOfSocket (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Engine descriptor from given complex by index
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index 59099e7..a871db9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -123,7 +123,7 @@ PcieAllocateEngine (
IN UINT8 DescriptorIndex,
IN PCIe_ENGINE_CONFIG *Engine
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -173,7 +173,7 @@ PcieMapTopologyOnComplex (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -252,7 +252,7 @@ PcieEnginesToWrapper (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
*
@@ -285,7 +285,7 @@ PcieCheckDescriptorMapsToWrapper (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Engine to be allocated.
*
@@ -303,7 +303,7 @@ PcieAllocateEngine (
Engine->Scratch = DescriptorIndex;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure engine list to support lane allocation according to configuration ID.
*
@@ -415,7 +415,7 @@ PcieMapTopologyOnWrapper (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize engine data
*
@@ -453,7 +453,7 @@ PcieMapInitializeEngineData (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -484,7 +484,7 @@ PcieCheckPortPciDeviceMapping (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate PCI addresses for all PCIe engines on silicon
*
@@ -546,7 +546,7 @@ PcieMapPortsPciAddresses (
return AgesaStatus;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* If link width from user descriptor less or equal to link width of engine
*
@@ -592,7 +592,7 @@ PcieCheckLanesMatch (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
index cea2e73..05397a5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -110,7 +110,7 @@ UINT16 Aspm168cL0sEnabled[] = {
0x0032
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie ASPM Black List
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
index a70d04e..b4b087c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -85,7 +85,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply PIF ganging for all lanes for given wrapper
*
@@ -178,7 +178,7 @@ PciePifApplyGanging (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -224,7 +224,7 @@ PciePifPllPowerDown (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL init for DDI
*
@@ -268,7 +268,7 @@ PciePifPllInitForDdi (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for on PIF to indicate action completion
*
@@ -296,7 +296,7 @@ PciePollPifForCompeletion (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable fifo reset
*
@@ -327,7 +327,7 @@ PciePifDisableFifoReset (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program LS2 exit time
*
@@ -359,7 +359,7 @@ PciePifSetLs2ExitTime (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PLL mode for L1
*
@@ -401,7 +401,7 @@ PciePifSetPllModeForL1 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program receiver detection power mode
*
@@ -434,7 +434,7 @@ PciePifSetRxDetectPowerMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pll ramp up time
*
@@ -507,7 +507,7 @@ PciePifSetPllRampTime (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
@@ -550,7 +550,7 @@ PciePifPllPowerControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power down PIFs
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index b80e6a7..a8e11b0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -115,7 +115,7 @@ PciePortRegisterRMW (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe port indirect register.
*
@@ -140,7 +140,7 @@ PciePortRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register.
*
@@ -174,7 +174,7 @@ PciePortRegisterWrite (
GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -209,7 +209,7 @@ PciePortRegisterWriteField (
PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe Port Indirect register field.
*
@@ -238,7 +238,7 @@ PciePortRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe port register.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
index 108e709..ce7290b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -74,7 +74,7 @@ UINT8 L1State = 0x1b;
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set completion timeout
*
@@ -111,7 +111,7 @@ PcieCompletionTimeout (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init hotplug port
*
@@ -189,7 +189,7 @@ PcieLinkInitHotplug (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set misc slot capability
*
@@ -222,7 +222,7 @@ PcieLinkSetSlotCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Safe mode to force link advertize Gen1 only capability in TS
*
@@ -251,7 +251,7 @@ PcieLinkSafeMode (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -276,7 +276,7 @@ PcieSetLinkWidthCap (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -287,7 +287,7 @@ PcieSetLinkWidthCap (
*
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Force compliance
*
@@ -326,7 +326,7 @@ PcieForceCompliance (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on SB link
*
@@ -350,7 +350,7 @@ PcieEnableAspm (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L1
*
@@ -371,7 +371,7 @@ PciePollLinkForL1Entry (
} while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Poll for link to get into L0
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
index 8c328ed..dde78a8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -73,7 +73,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe timer timestamp
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index efcbde3..4e77880 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -74,7 +74,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Cleanup reconfig
*
@@ -102,7 +102,7 @@ PcieTopologyCleanUpReconfig (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare for reconfiguration
*
@@ -153,7 +153,7 @@ PcieTopologyPrepareForReconfig (
UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Locate mux array index
*
@@ -178,7 +178,7 @@ PcieTopologyLocateMuxIndex (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply lane mux
*
@@ -270,7 +270,7 @@ PcieTopologyApplyLaneMux (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Select master PLL
*
@@ -364,7 +364,7 @@ PcieTopologySelectMasterPll (
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
@@ -435,7 +435,7 @@ PcieTopologyExecuteReconfig (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
@@ -474,7 +474,7 @@ PcieTopologySetLinkReversal (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reduce link width
*
@@ -508,7 +508,7 @@ PcieTopologyReduceLinkWidth (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lanes enable/disable control
*
@@ -583,7 +583,7 @@ PcieTopologyServices136_fun (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set core configuration according to PCIe port topology
*
@@ -652,7 +652,7 @@ PcieTopologySetCoreConfig (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for PCIe lanes
*
@@ -694,7 +694,7 @@ PcieWrapSetTxS1CtrlForLaneMux (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set TX control for lane muxes
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 2cb3882..726bc6a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -89,7 +89,7 @@ typedef struct {
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link state history from HW state machine
*
@@ -128,7 +128,7 @@ PcieUtilGetLinkHwStateHistory (
LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Search array for specific pattern
*
@@ -168,7 +168,7 @@ PcieUtilSearchArray (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link reversed
*
@@ -201,7 +201,7 @@ PcieUtilIsLinkReversed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link width detected during training
*
@@ -249,7 +249,7 @@ PcieUtilGetLinkWidth (
return LinkWidth;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -316,7 +316,7 @@ PcieUtilGetPcieEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of PCIE engine lane of requested type
*
@@ -357,7 +357,7 @@ PcieUtilGetDdiEngineLaneBitMap (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of engine lane of requested type
*
@@ -439,7 +439,7 @@ PcieUtilGetEngineLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of phy lane confugred for master pll
*
@@ -459,7 +459,7 @@ PcieUtilGetMasterPllLaneBitMap (
return 0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of Wrapper lane of requested type
*
@@ -503,7 +503,7 @@ PcieUtilGetWrapperLaneBitMap (
return LaneBitmap;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program port register table
*
@@ -547,7 +547,7 @@ PciePortProgramRegisterTable (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lock registers
*
@@ -581,7 +581,7 @@ PcieLockRegisters (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -625,7 +625,7 @@ PcieUtilGlobalGenCapabilityCallback (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine global GEN capability
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
index eed1d2f..22fdc74 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -53,7 +53,7 @@
#include "GnbPcieInitLibV1.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -77,7 +77,7 @@ PcieRegisterRead (
return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register value.
*
@@ -102,7 +102,7 @@ PcieSiliconRegisterRead (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -135,7 +135,7 @@ PcieRegisterWrite (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register value.
*
@@ -167,7 +167,7 @@ PcieSiliconRegisterWrite (
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCIe register field.
*
@@ -196,7 +196,7 @@ PcieRegisterReadField (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCIe register field.
*
@@ -232,7 +232,7 @@ PcieRegisterWriteField (
PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
@@ -269,7 +269,7 @@ PcieRegisterRMW (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCIe register.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
index 0409c85..e50fffc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
@@ -82,7 +82,7 @@ PcieSetLinkSpeedCapV4 (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set current link speed
*
@@ -173,7 +173,7 @@ PcieSetLinkSpeedCapV4 (
GnbLibGetHeader (Pcie)
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable passing TLP prefix to IOMMU if IOMMU enabled
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
index f49576b..435b003 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
@@ -98,7 +98,7 @@ PcieTopologyExecuteReconfigV4 (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Relinquish control to DDI for specific lanes
*
@@ -135,7 +135,7 @@ PcieSetDdiOwnPhyV4 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set SSID
*
@@ -162,7 +162,7 @@ PcieSetSsidV4 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable lane reversal
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c
index 2e65cd3..c8a16b1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c
@@ -88,7 +88,7 @@ PciePhyChannelCharacteristicV5 (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set PHY channel characteristic
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c
index 1a8d642..daf69c3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c
@@ -94,7 +94,7 @@ PciePifSetLs2ExitTimeV5 (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Apply PIF ganging for all lanes for given wrapper
*
@@ -184,7 +184,7 @@ PciePifApplyGangingV5 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PLL powerdown
*
@@ -232,7 +232,7 @@ PciePifPllPowerDownV5 (
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDownV5 Exit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program LS2 exit time
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c
index 2559168..206acc1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c
@@ -74,7 +74,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init hotplug port
*
@@ -111,7 +111,7 @@ PcieLinkInitHotplugV5 (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set slot power limit
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
index 898d50b..7bb3630 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
@@ -84,7 +84,7 @@ PcieSiliconEnablePortsV5 (
IN PCIe_PLATFORM_CONFIG *Pcie
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control port visibility in PCI config space
*
@@ -117,7 +117,7 @@ PciePortsVisibilityControlV5 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide/Unhide all ports
*
@@ -154,7 +154,7 @@ PcieSiliconControlPortsV5 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide unused ports
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c
index 3a421d0..326b307 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c
@@ -75,7 +75,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Lanes enable/disable control
*
@@ -114,7 +114,7 @@ PcieTopologyLaneControlV5 (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reduce link width
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c
index 78985ab..b6db800 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c
@@ -81,7 +81,7 @@ UINT8 LaneMuxSelectorArrayV5[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if lane topology supports Gen3
*
@@ -119,7 +119,7 @@ PcieTopologyIsGen3SupportedV5 (
return TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Execute/clean up reconfiguration
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
index e385676..f8580ce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
@@ -104,7 +104,7 @@ PcieMaxPayloadInterface (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Determine maximum payload size for PCIe segment
*
@@ -139,7 +139,7 @@ PcieSetMaxPayload (
IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadExit\n");
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment
*
@@ -201,7 +201,7 @@ PcieGetMaxPayloadCallback (
return SCAN_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure the Max Payload setting to all devices in the PCIe Segment
*
@@ -261,7 +261,7 @@ UINT16 PayloadBlacklistDeviceTable[] = {
0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Pcie Max_Payload_Size Black List
*
@@ -298,7 +298,7 @@ PciePayloadBlackListFeature (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Callback to init various features on all active ports
*
@@ -339,7 +339,7 @@ PcieMaxPayloadInitCallback (
}
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Interface to configure MaxPayloadSize on PCIE interface
*
@@ -349,7 +349,7 @@ PcieMaxPayloadInitCallback (
*
* @retval AGESA_STATUS
*/
- /*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieMaxPayloadInterface (
IN AMD_CONFIG_PARAMS *StdHeader
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
index a4bd3de..0fb76e7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set link State
*
@@ -103,7 +103,7 @@ PcieTrainingSetPortState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set state for all engines connected to same reset ID
*
@@ -136,7 +136,7 @@ PcieSetResetStateOnEngines (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Assert GPIO port reset.
*
@@ -167,7 +167,7 @@ PcieTrainingAssertReset (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for reset duration
*
@@ -190,7 +190,7 @@ PcieTrainingCheckResetDuration (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Deassert GPIO port reset.
*
@@ -221,7 +221,7 @@ PcieTrainingDeassertReset (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check for after reset deassertion timeout
*
@@ -245,7 +245,7 @@ PcieTrainingCheckResetTimeout (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Release training
*
@@ -279,7 +279,7 @@ PcieTrainingRelease (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect presence of any EP on the link
*
@@ -313,7 +313,7 @@ UINT8 FailPattern1 [] = {0x2a, 0x6};
UINT8 FailPattern2 [] = {0x2a, 0x9};
UINT8 FailPattern3 [] = {0x2a, 0xb};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Detect Link State
*
@@ -355,7 +355,7 @@ PcieTrainingDetectLinkState (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Broken Lane
*
@@ -393,7 +393,7 @@ PcieTrainingBrokenLineV2 (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen2
*
@@ -429,7 +429,7 @@ PcieTrainingGen2Fail (
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Link in L0
*
@@ -447,7 +447,7 @@ PcieCheckLinkL0 (
{
PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if link fail because device does not support Gen X
*
@@ -483,7 +483,7 @@ PcieTrainingCheckVcoNegotiation (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if for GFX workaround condition
*
@@ -526,7 +526,7 @@ PcieTrainingGfxWorkaround (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Retrain link
*
@@ -552,7 +552,7 @@ PcieTrainingRetrainLink (
PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training fail on this port
*
@@ -572,7 +572,7 @@ PcieTrainingFail (
PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links training success
*
@@ -600,7 +600,7 @@ PcieTrainingSuccess (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Links in compliance
*
@@ -620,7 +620,7 @@ PcieTrainingCompliance (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCie EP not present
*
@@ -651,7 +651,7 @@ PcieTrainingNotPresent (
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Final state. Port training completed.
*
@@ -670,7 +670,7 @@ PcieTrainingCompleted (
{
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Training state handling
*
@@ -759,7 +759,7 @@ PcieTrainingPortCallback (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Main link training procedure
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
index a6150bf..ae624f7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
@@ -112,7 +112,7 @@ PcieIsDeskewCardDetected (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
*
*
@@ -163,7 +163,7 @@ PcieGfxCardWorkaroundV2 (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RV370/RV380 Deskew workaround
*
@@ -206,7 +206,7 @@ PcieDeskewWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NV43 card workaround (lost SSID)
*
@@ -241,7 +241,7 @@ PcieNvWorkaround (
return GFX_WORKAROUND_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate temporary resources for Pcie P2P bridge
*
@@ -274,7 +274,7 @@ PcieConfigureBridgeResources (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Free temporary resources for Pcie P2P bridge
*
@@ -300,7 +300,7 @@ PcieFreeBridgeResources (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Save CPU MMIO register
*
@@ -326,7 +326,7 @@ PcieProgramCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Restore CPU MMIO register
*
@@ -347,7 +347,7 @@ PcieRestoreCpuMmio (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if card required test for deskew workaround
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
index 69bfdd1..90da05c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
@@ -92,7 +92,7 @@ GnbFmGetLinkId (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Host bridge PCI Address
*
@@ -115,7 +115,7 @@ GnbFmGetPciAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bus range decoded by GNB
*
@@ -142,7 +142,7 @@ GnbFmGetBusDecodeRange (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get link to which GNB connected to
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
index 5cec1a3..0c0c4a2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
@@ -82,7 +82,7 @@ SbGetAlinkIoAddress (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB IOAPIC Base Address
*
@@ -100,7 +100,7 @@ SbGetSbIoApicBaseAddress (
return ApicBaseAddress & 0xffffffe0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
*Get SB MMIO Base Address
*
@@ -119,14 +119,14 @@ SbGetSbMmioBaseAddress (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Alink config address
*
* @param[in] StdHeader Standard configuration header
* @retval AlinkPortAddress
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT16
SbGetAlinkIoAddress (
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index b7f2879..e427a28 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -72,7 +72,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable/Disable ASPM on GNB-SB link
*
@@ -103,7 +103,7 @@ SbPcieLinkAspmControl (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SB ASPM.
* Enable ASPM states on SB
@@ -112,7 +112,7 @@ SbPcieLinkAspmControl (
* @param[in] Aspm ASPM bitmap.
* @param[in] StdHeader Standard configuration header
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
SbPcieInitAspm (
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
index cbd455e..5ec2650 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
@@ -83,7 +83,7 @@ GnbSmuServiceRequestV7S3Script (
IN VOID *Context
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU service request
*
@@ -153,7 +153,7 @@ GnbSmuServiceRequestV7 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU service request for S3 script
*
@@ -181,7 +181,7 @@ GnbSmuServiceRequestV7S3Script (
GnbSmuServiceRequestV7 (&DevObject, SmuMsgContext->RequestId, SmuMsgContext->RequestArgument, 0);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SMU firmware download
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c
index c7dbe35..49a331d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c
@@ -78,7 +78,7 @@ GfxInitSview (
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SVIEW configuration
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c
index 5d865d4..c3ec1d7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c
@@ -83,7 +83,7 @@ GnbProcessTableRegisterRmw (
IN AMD_CONFIG_PARAMS *StdHeader
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Process table
*
@@ -311,7 +311,7 @@ GnbProcessTable (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Supporting function for register read modify write
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c
index eeaf64f..eb355a9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c
@@ -82,7 +82,7 @@ UINT8 RegisterDomainMap[] = {
0xFD ///< End
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Convert URA Token to register address and field location
*
@@ -192,7 +192,7 @@ UraTranslateToken (
return Token.Encode;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
@@ -228,7 +228,7 @@ GnbUraGet (
GnbUraProtocol->GnbUraGet (Device, &TokenInfo, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
@@ -263,7 +263,7 @@ GnbUraSet (
GnbUraProtocol->GnbUraSet (Device, &TokenInfo, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
@@ -321,7 +321,7 @@ GnbUraCombinedGet (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gnb Unified Register Access method
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c
index 5d761d4..1e0f27f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c
@@ -70,7 +70,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write the total number of cores to the Node
*
@@ -102,7 +102,7 @@ Fam16SetTotalCores (
LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return the number of cores (1 based count) on Node.
*
@@ -152,7 +152,7 @@ Fam16GetNumCoresOnNode (
return (UINT8) (Result + 1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Count (1 based) of Nodes in the system.
*
@@ -175,7 +175,7 @@ Fam16GetNodeCount (
return (1);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the enable compute unit status for this node.
*
@@ -206,7 +206,7 @@ Fam16GetEnabledComputeUnits (
return ((UINT8) Enabled);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the dual core compute unit status for this node.
*
@@ -237,7 +237,7 @@ Fam16GetDualcoreComputeUnits (
return ((UINT8) Dual);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the triple core compute unit status for this node.
*
@@ -268,7 +268,7 @@ Fam16GetTriplecoreComputeUnits (
return ((UINT8) Triple);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the quad core compute unit status for this node.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c
index 0807a41..8e4f6b5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c
@@ -88,7 +88,7 @@ CONST HT_FEATURES ROMDATA HtFeaturesNone =
(PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Provide the current Feature set implementation.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c
index 7959665..696b7e1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c
@@ -208,7 +208,7 @@ CONST HT_INTERFACE ROMDATA HtInterfaceNone =
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* A constructor for the internal Ht Interface.
*
@@ -233,7 +233,7 @@ NewHtInterface (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* A "constructor" for the HyperTransport external interface.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c
index 189fbb9..6bd5dd7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c
@@ -96,8 +96,8 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
+
+
/**
* Get limits for CPU to CPU Links.
*
@@ -167,7 +167,7 @@ GetCpu2CpuPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Skip reganging of subLinks.
*
@@ -233,7 +233,7 @@ GetSkipRegang (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new, empty Hop Count Table, to make one for the installed topology.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c
index ab0ef1c..66c1576 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c
@@ -101,7 +101,7 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is PackageLink an Internal Link?
*
@@ -121,7 +121,7 @@ IsPackageLinkInternal (
return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Ignore a Link.
*
@@ -201,7 +201,7 @@ GetIgnoreLink (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the Socket number for a given Node number.
*
@@ -229,7 +229,7 @@ GetSocketFromMap (
return Socket;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get a new Socket Die to Node Map.
*
@@ -280,7 +280,7 @@ NewNodeAndSocketTables (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get the minimum Northbridge frequency for the system.
*
@@ -343,7 +343,7 @@ GetMinNbCoreFreq (
* There are no strict assumptions about the ordering of the socket structures.
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps between Sockets and Nodes for a specific newly discovered node.
*
@@ -443,7 +443,7 @@ SetNodeToSocketMap (
(*State->NodeToSocketDieMap)[NewNode].Die = Module;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Clean up the map structures after severe event has caused a fall back to 1 node.
*
@@ -481,7 +481,7 @@ CleanMapsAfterError (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Post Node id and other context info to AP cores via mailbox.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
index 1c124d3..011a3fb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Manual BUID assignment list.
*
@@ -152,7 +152,7 @@ GetManualBuidSwapList (
return result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Override capabilities of a device.
*
@@ -269,7 +269,7 @@ GetDeviceCapOverride (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get limits for non-coherent Links.
*
@@ -328,7 +328,7 @@ GetIoPcbLimits (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Manually control bus number assignment.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c
index bbad241..0326f4b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c
@@ -87,7 +87,7 @@ IsBootCore (
IN STATE_DATA *State
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update maps with the core range for each module.
*
@@ -201,7 +201,7 @@ UpdateCoreRanges (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Complete the coherent init with any system level initialization.
*
@@ -236,7 +236,7 @@ FinalizeCoherentInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the coherent fabric.
*
@@ -306,7 +306,7 @@ CoherentInit (
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the non-coherent fabric.
*
@@ -356,7 +356,7 @@ NcInit (
*** Link Optimization ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Optimize Link Features.
*
@@ -395,7 +395,7 @@ LinkOptimization (
State->HtFeatures->SetLinkData (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Handle system and performance tunings.
*
@@ -426,7 +426,7 @@ Tuning (
State->HtFeatures->TrafficDistribution (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize the Node and Socket maps for an AP Core.
*
@@ -460,7 +460,7 @@ InitApMaps (
UpdateCoreRanges (State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Is the currently running core the BSC?
*
@@ -488,7 +488,7 @@ IsBootCore (
*** HT Initialize ***
***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
+
/**
* The top level external interface for Hypertransport Initialization.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
index 293274a..1cc95a4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
@@ -156,7 +156,7 @@ CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
NULL
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Make a compatibility key.
*
@@ -194,7 +194,7 @@ MakeKey (
return LogicalId.Family;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Construct a new northbridge.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c
index 22c3eb8..b04bbfc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c
@@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Log an event.
*
@@ -126,7 +126,7 @@ setEventNotify (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_SYNCFLOOD
*
@@ -159,7 +159,7 @@ NotifyAlertHwSyncFlood (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_HW_HTCRC
*
@@ -195,7 +195,7 @@ NotifyAlertHwHtCrc (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUS_MAX_EXCEED
*
@@ -230,7 +230,7 @@ NotifyErrorNcohBusMaxExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_CFG_MAP_EXCEED
*
@@ -262,7 +262,7 @@ NotifyErrorNcohCfgMapExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
@@ -303,7 +303,7 @@ NotifyErrorNcohBuidExceed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
@@ -341,7 +341,7 @@ NotifyErrorNcohDeviceFailed (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_NCOH_AUTO_DEPTH
*
@@ -376,7 +376,7 @@ NotifyInfoNcohAutoDepth (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
*
@@ -411,7 +411,7 @@ NotifyWarningOptRequiredCapRetry (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
*
@@ -446,7 +446,7 @@ NotifyWarningOptRequiredCapGen3 (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
@@ -485,7 +485,7 @@ NotifyWarningOptUnusedLinks (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
@@ -524,7 +524,7 @@ NotifyWarningOptLinkPairExceed (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NO_TOPOLOGY
*
@@ -554,7 +554,7 @@ NotifyErrorCohNoTopology (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
@@ -590,7 +590,7 @@ NotifyFatalCohProcessorTypeMix (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
@@ -629,7 +629,7 @@ NotifyInfoCohNodeDiscovered (
(UINT8 *)&Evt, State);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
index 58d0cbe..007d0d2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
@@ -47,7 +47,7 @@
#ifndef _HT_NOTIFY_H_
#define _HT_NOTIFY_H_
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific event data definitions.
* All structures must be 4 UINT32's in size, no more, no less.
*/
@@ -167,7 +167,7 @@ typedef struct {
UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-/*----------------------------------------------------------------------------------------*/
+
/* Event specific Notify functions.
*/
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
index d75bf3e..bf8a496 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
@@ -65,7 +65,7 @@ AmdIdsDebugPrintAssert (
);
-/*--------------------------------------------------------------------------------------*/
+
/**
* IDS back-end code for AGESA_TESTPOINT
*
@@ -73,7 +73,7 @@ AmdIdsDebugPrintAssert (
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
-/*--------------------------------------------------------------------------------------*/
+
VOID
IdsAgesaTestPoint (
IN AGESA_TP TestPoint,
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
index 50306bb..4731e2d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
@@ -434,7 +434,7 @@ IdsGetNumPstatesFamCommon (
return pstatesnum;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c
index 664409e..921581a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the ARDK block. The function always
@@ -105,7 +105,7 @@ MemAGetPsCfgDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 8baba27..1772d64 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -105,7 +105,7 @@ MemFUndoInterleaveBanks (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -141,7 +141,7 @@ MemFInterleaveBanks (
return RetFlag;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -200,7 +200,7 @@ MemFUndoInterleaveBanks (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -310,7 +310,7 @@ MemFDctInterleaveBanks (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This supporting function swaps Chip selects
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
index 57cc491..ac0ec05 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
@@ -116,7 +116,7 @@ MemFDMISupport3 (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -614,7 +614,7 @@ MemFGetNodeMemBase (
return NodeMemBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -645,7 +645,7 @@ MemFGetDctMemBase (
return DctMemBase;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -676,7 +676,7 @@ MemFGetDctInterleavedMemSize (
return DctInterleavedMemSize;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c
index 7ff3960..3b609f5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c
@@ -94,7 +94,7 @@ MemFCheckECC (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -160,7 +160,7 @@ MemFCheckECC (
return FALSE;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c
index 54487d2..b329ff2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c
@@ -92,7 +92,7 @@ MemFInitEMP (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -156,7 +156,7 @@ MemFInitEMP (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 475b04f..471bce0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -90,7 +90,7 @@ MemFRASExcludeDIMM (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training for each node.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 5d98494..c608ec3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -113,7 +113,7 @@ MemFUnaryXOR (
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function identifies the dimm on which the given memory address locates.
@@ -206,7 +206,7 @@ AmdIdentifyDimm (
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function translates the given physical system address to
@@ -480,7 +480,7 @@ MemFTransSysAddrToCS (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function is the interface to call the PCI register access function
@@ -522,7 +522,7 @@ MemFGetPCI (
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns an even parity bit (making the total # of 1's even)
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c
index 9407f45..0f56c99 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function calculate the common lowest voltage supported by all DDR3
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 5a0c675..8364348 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -81,7 +81,7 @@ RDATA_GROUP (G2_PEI)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -114,7 +114,7 @@ MemFMctMemClr_Init (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
index 41a14ae..4d4d658 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G2_PEI)
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function does On-Dimm thermal management.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
index 2fd10c5..235506a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -69,7 +69,7 @@ RDATA_GROUP (G2_PEI)
*/
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
index 654af0e..533e814 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -61,7 +61,7 @@ RDATA_GROUP (G1_PEICC)
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
index b355d6b..92916aa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
@@ -117,7 +117,7 @@ MemFRdWr2DProgramDataPatternKB (
IN VOID* PatternIndexPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the 2D Read/Write Training Feature Hooks for KB
@@ -152,7 +152,7 @@ MemFRdWr2DTrainingInitKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref for 2D Read/Write Training
@@ -230,7 +230,7 @@ MemFRdWr2DProgramVrefKB (
return (Status == AGESA_SUCCESS) ? TRUE : FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function scales Vref from the range used in Data Collection to
@@ -254,7 +254,7 @@ MemFRdWr2DScaleVrefKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref to internal or external control for 2D Read
@@ -281,7 +281,7 @@ MemFRdWr2DProgramIntExtVrefSelectKB (
return NBPtr->RefPtr->ExternalVrefCtl;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the Data Pattern that will be sent and compared
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c
index 62bfb82..85b7164 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes 2D training for Read DQS
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c
index 090a937..c36d4f1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c
@@ -190,7 +190,7 @@ StartAggressors (
IN BOOLEAN TurnOn
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize Eye Rim Search
@@ -257,7 +257,7 @@ MemFInitializeEyeRimSearch (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* This function collects data for Eye Rim Search
*
@@ -623,7 +623,7 @@ MemFRdWr2DEyeRimSearch (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Fill the data eye
*
@@ -712,7 +712,7 @@ MemTEyeFill (
} //x Loop
} // Lane Loop
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get the 1D trained center
@@ -746,7 +746,7 @@ Get1DTrainedEyeCenter (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine if a Byte Lane result has been saved
@@ -780,7 +780,7 @@ DetermineSavedState (
return (UINT8) (SavedData->LaneSaved[lane].Vref[xlateY (y)].NegRdWrDly >> (SavedData->xMax - (x & SavedData->xMax)) & 0x1);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine if a failure has occured
@@ -838,7 +838,7 @@ CheckForFail (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get pass fail state of lane
@@ -889,7 +889,7 @@ GetPassFailValue (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set the Pass/Fail state of lane
@@ -926,7 +926,7 @@ SetPassFailValue (
RdWr2DData->Lane[lane].Vref[xlateY (y)].NegRdWrDly |= (result == 0) ? (1 << (SavedData->xMax - (x & SavedData->xMax))) : 0;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set the save state of lane
@@ -959,7 +959,7 @@ SetSavedState (
SavedData->LaneSaved[lane].Vref[xlateY (y)].NegRdWrDly |= (1 << (SavedData->xMax - (x & SavedData->xMax)));
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Translate Vref into a positive, linear value that can be used as an
@@ -980,7 +980,7 @@ xlateY (
return (y + 0xF) & 0x1F;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Re-walk the eye rim for each aggressor combination, which invalidates
@@ -1020,7 +1020,7 @@ ClearSampledPassResults (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform in-phase comparison
@@ -1044,7 +1044,7 @@ CompareInPhase (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Perform 180 Degree out-of-phase comparison
@@ -1068,7 +1068,7 @@ Compare180Phase (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Program Vref after scaling to accomodate the register definition
@@ -1091,7 +1091,7 @@ ProgramVref (
NBPtr->FamilySpecificHook[RdWr2DProgramVref] (NBPtr, &ScaledVref);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Turn Aggressor Channels On or Off
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c
index b8d8429..46fe5c8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim for 2D RdDqs Training
@@ -199,7 +199,7 @@ MemFRdWr2DInitVictim (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim chipSelects for 2D Read or Write
@@ -225,7 +225,7 @@ MemFRdWr2DInitVictimChipSel (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the In Phase Error status bits for comparison
@@ -248,7 +248,7 @@ MemFRdWr2DCompareInPhase (
return TRUE;
}
- /*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the 180 Error status bits for RD/WR 2D training
@@ -270,7 +270,7 @@ MemFRdWr2DCompare180Phase (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function starts the Victim for 2D RdDqs Training Continuous Writes
@@ -342,7 +342,7 @@ MemFRdWr2DStartVictim (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the Victim for 2D RdDqs Training
@@ -377,7 +377,7 @@ MemFRdWr2DFinalizeVictim (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the Data Pattern that will be sent and compared
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
index 6a9e873..5d033fa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
@@ -100,7 +100,7 @@ MemFRdWr2DScaleVref (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the 2D Read/Write Training Feature Hooks.
@@ -134,7 +134,7 @@ MemFRdWr2DTrainingInit (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes 2D training for Read DQS or Write DQ
@@ -313,7 +313,7 @@ MemFAmdRdWr2DTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines whether the current configuration is a valid
@@ -346,7 +346,7 @@ MemFCheckRdWr2DTrainingPerConfig (
}
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of lanes for puposes of 2D
@@ -375,7 +375,7 @@ MemFRdWr2DGetMaxLanes (
}
return MaxLanes;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref to internal or external control for 2D Read
@@ -401,7 +401,7 @@ MemFRdWr2DProgramIntExtVrefSelect (
return NBPtr->RefPtr->ExternalVrefCtl;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function scales Vref from the range used in Data Collection to
@@ -425,7 +425,7 @@ MemFRdWr2DScaleVref (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref for 2D Read/Write Training
@@ -501,7 +501,7 @@ MemFRdWr2DProgramVref (
return (Status == AGESA_SUCCESS) ? TRUE : FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Read DQS or Write DQ Delay values for Read/Write
@@ -548,7 +548,7 @@ MemFRdWr2DProgramDelays (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function stores data for 2D Read DQS and Write DQ Training
@@ -595,7 +595,7 @@ MemFRdWr2DStoreResult (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the height of data for 2D Read and Write training
@@ -631,7 +631,7 @@ MemFRdWr2DHeight (
);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the width for 2D RdDQS and WrDat training
@@ -653,7 +653,7 @@ MemFGetRdWr2DWidth (
return NBPtr->DiamondWidthWr;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the step height for the diamond mask for 2D RdDQS or
@@ -702,7 +702,7 @@ MemFCheckRdWr2DDiamondMaskStep (
return status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function applies a mask for 2D RdDQS or WrDat training
@@ -998,7 +998,7 @@ MemFRdWr2DApplyMask (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Examines the convolution function and determines the Max Delay
@@ -1102,7 +1102,7 @@ MemFRdWr2DProcessConvolution (
}
return status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the Max Rd Dqs or Max Wr DQ for 2D training from
@@ -1165,7 +1165,7 @@ MemFRdWr2DProgramMaxDelays (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the Positive and negative Vref Margin for the current CS
@@ -1250,7 +1250,7 @@ MemFRdWr2DFindCsVrefMargin (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the final Vref Margin for 2D RdDQS or WrDat training
@@ -1322,7 +1322,7 @@ MemFRdWr2DFinalVrefMargin (
((OffsetFromVref != 0) ? ((SmallestMaxPosVref > SmallestMaxNegVref) ? " + ":" - "):" "), OffsetFromVref);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function displays ther results of the 2D search
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c
index e6914a7..aae140d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c
@@ -94,7 +94,7 @@ extern MEM_NB_SUPPORT memNBInstalled[];
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -151,7 +151,7 @@ AmdMemS3Resume (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -198,7 +198,7 @@ MemS3Deallocate (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -296,7 +296,7 @@ MemFS3GetDeviceList (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -358,7 +358,7 @@ MemS3ResumeInitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -408,7 +408,7 @@ MemFS3GetPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemFS3GetCPciDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -508,7 +508,7 @@ MemFS3GetMsrDeviceRegisterList (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -565,7 +565,7 @@ MemFS3GetCMsrDeviceRegisterList (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -689,7 +689,7 @@ MemS3InitNB (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c
index 558bc62..6aebe33 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c
@@ -101,7 +101,7 @@ MemMFlowKB (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c
index 9d62c88..472953f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c
@@ -94,7 +94,7 @@ memDefFalse ( VOID );
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function
@@ -105,7 +105,7 @@ memDefRet ( VOID )
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return function that returns TRUE
@@ -117,7 +117,7 @@ memDefTrue ( VOID )
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns FALSE.
@@ -128,7 +128,7 @@ memDefFalse ( VOID )
{
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function for flow control
@@ -142,7 +142,7 @@ MemMFlowDef (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used in place of an un-supported function that returns AGESA_SUCCESS.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
index 426ce58..3a2828c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
@@ -89,7 +89,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function handle errors occur in memory code.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c
index 318165a..bd4f805 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c
@@ -90,7 +90,7 @@ extern UINT8 SizeOfNBInstalledTable;
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c
index a355741..b4b8dc6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c
@@ -93,7 +93,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -127,7 +127,7 @@ MemAmdFinalize (
return AGESA_SUCCESS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -216,7 +216,7 @@ MemSocketScan (
return AgesaStatus;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -237,7 +237,7 @@ SetMemError (
MCTPtr->ErrCode = Errorval;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c
index 56a769f..4b3a404 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c
@@ -155,7 +155,7 @@ MemCheckRankType (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Process Conditional Platform Specific Overrides
@@ -428,7 +428,7 @@ MemProcessConditionalOverrides (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
* Perform ODT Platform Override
*
@@ -477,7 +477,7 @@ MemPSODoActionODT (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Address Timing Platform Override
*
@@ -516,7 +516,7 @@ MemPSODoActionAddrTmg (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Drive Strength Platform Override
*
@@ -555,7 +555,7 @@ MemPSODoActionODCControl (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
* Perform Slew Rate Platform Override
*
@@ -599,7 +599,7 @@ MemPSODoActionSlewRate (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the POR supported speed for a specific config
@@ -657,7 +657,7 @@ MemPSODoActionGetFreqLimit (
return Result;
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function matches a particular Rank Type Mask to the installed
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c
index acff719..651ba24 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c
@@ -81,7 +81,7 @@ MemMEcc (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -133,7 +133,7 @@ MemMEcc (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disable DRAM scrubber
@@ -159,7 +159,7 @@ MemMDisableScrubber (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function restore the settings of DRAM scrubber
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c
index ca599bd..1b3fea0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c
@@ -81,7 +81,7 @@ MemMRASExcludeDIMM (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and disable Chip selects that fail training on all nodes.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
index ee3eec7..b96c1f4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
@@ -79,7 +79,7 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes.
@@ -139,7 +139,7 @@ MemMLvDdr3 (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the common supported voltage on all nodes, taken into account of the
@@ -217,7 +217,7 @@ MemMLvDdr3PerformanceEnhPre (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Finalize the VDDIO for the board for performance enhancement.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c
index bd04ed2..814340d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c
@@ -78,7 +78,7 @@ MemMMctMemClr (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
index 3d80baf..015263c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
@@ -133,7 +133,7 @@ MemMS3Save (
extern MEM_NB_SUPPORT memNBInstalled[];
extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determines the maximum amount of space required to store all reduced NB block
@@ -176,7 +176,7 @@ GetReducedMemBlockSize (
return MemBlockSize;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Save all the required reduced NB blocks and DCT blocks.
@@ -237,7 +237,7 @@ MemMReducedMemBlockSave (
*ActualBufferSize += (UINT32) ((UINT8 *)ReducedDCTPtr - (UINT8 *)Storage);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Restore all the required reduced NB blocks and DCT blocks.
@@ -300,7 +300,7 @@ MemMReducedMemBlockRestore (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and save memory context if possible.
@@ -424,7 +424,7 @@ MemMContextSave (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and restore memory context if possible.
@@ -538,7 +538,7 @@ MemMContextRestore (
return RefPtr->MemRestoreCtl;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Save all memory related data for S3.
@@ -604,7 +604,7 @@ MemMS3Save (
*----------------------------------------------------------------------------
*/
-/*---------------------------------------------------------------------------------------*/
+
/**
* This function does dram init based on register value
*
@@ -706,7 +706,7 @@ MemMDramInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Create S3 NB Block.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c
index b474d64..035f723 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c
@@ -79,7 +79,7 @@ MemMInterleaveNodes (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable node interleaving on all nodes.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c
index 91b38b4..2debc83 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c
@@ -76,7 +76,7 @@ MemMOnlineSpare (
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check and enable online spare on all nodes.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c
index 375344e..c311416 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c
@@ -91,7 +91,7 @@ MemMParallelTraining (
*
*-----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
index bb8bccb..d9bb072 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
@@ -96,7 +96,7 @@ MemMStandardTrainingUsingAdjacentDies (
*/
extern BUILD_OPT_CFG UserOptions;
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTraining
@@ -141,7 +141,7 @@ MemMStandardTraining (
return (BOOLEAN) (Die == mmPtr->DieCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemMStandardTrainingUsingAdjacentDies
@@ -259,7 +259,7 @@ MemMStandardTrainingUsingAdjacentDies (
return (BOOLEAN) (Die == mmPtr->DieCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemM2DTrainingWithAggressor
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
index 163fecd..0b170dc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
@@ -92,7 +92,7 @@ MemMUmaAlloc (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
index d497aec..6e45331 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
@@ -104,7 +104,7 @@ MemSPDDataProcess (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -315,7 +315,7 @@ AmdMemAuto (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
index 8d81773..54fb958 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
@@ -162,7 +162,7 @@ CONST UINT8 PatternJD_256[256] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the (index)th UINT8
@@ -254,7 +254,7 @@ MemUFillTrainPattern (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function flushes cache lines
@@ -284,7 +284,7 @@ MemUProcIOClFlush (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
@@ -310,7 +310,7 @@ MemUSetUpperFSbase (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function resets the target address space to Write Through IO by disabling IORRs
@@ -331,7 +331,7 @@ MemUResetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the target range to WT IO (using an IORR overlapping
@@ -359,7 +359,7 @@ MemUSetTargetWTIO (
LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of 10ns cycles
@@ -391,7 +391,7 @@ MemUWait10ns (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Find the entry of platform specific overriding table.
@@ -481,7 +481,7 @@ FindPSOverrideEntry (
return NULL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -519,7 +519,7 @@ GetMaxDimmsPerChannel (
return MaxDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -557,7 +557,7 @@ GetMaxSolderedDownDimmsPerChannel (
return MaxSolderedDownDimmPerCH;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -598,7 +598,7 @@ GetMaxChannelsPerSocket (
return MaxChannelsPerSocket;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -636,7 +636,7 @@ GetMaxCSPerChannel (
return MaxCSPerChannel;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -675,7 +675,7 @@ GetSpdSocketIndex (
return SpdSocketIndex;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -713,7 +713,7 @@ GetSpdChannelIndex (
return SpdChannelIndex;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns the upper 32 bits mask for variable MTRR based on
@@ -740,7 +740,7 @@ GetVarMtrrHiMsk (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function returns number of memclk converted from ns
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c
index 819fb20..819f7d6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c
@@ -110,7 +110,7 @@ MemNTotalSyncComponentsKB (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -244,7 +244,7 @@ MemNAutoConfigKB (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -323,7 +323,7 @@ MemNCapSpeedBatteryLifeKB (
NBPtr->NbPsCtlReg = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -378,7 +378,7 @@ MemNGetMaxLatParamsKB (
*DlyBiasPtr = (UINT16) N;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -496,7 +496,7 @@ MemNExitPhyAssistedTrainingKB (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -535,7 +535,7 @@ MemNTotalSyncComponentsKB (
return P;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function obtains the memory frequency in the current context
@@ -568,7 +568,7 @@ MemNGetMemClkFreqInCurrentContextKB (
return MemClkSpeed;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates and programs NB P-state dependent registers
@@ -636,7 +636,7 @@ MemNProgramNbPstateDependentRegistersKB (
MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -657,7 +657,7 @@ MemNBeforeDramInitKB (
MemNProgramNonSeqDependentRegistersKB (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller for training
@@ -700,7 +700,7 @@ MemNConfigureDctTrainingKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the remaining DCT registers not covered by
@@ -728,7 +728,7 @@ MemNProgramNonSeqDependentRegistersKB (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the memory controller for normal operation
@@ -778,7 +778,7 @@ MemNConfigureDctNormalKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function modifies CS interleaving low address according to several conditions for KB.
@@ -813,7 +813,7 @@ MemNCSIntLvLowAddrAdjKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -852,7 +852,7 @@ MemNReleaseNbPstateKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -957,7 +957,7 @@ MemNMemPstateStageChangeKB (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1032,7 +1032,7 @@ MemNPowerDownCtlKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1049,7 +1049,7 @@ MemNBeforePlatformSpecKB (
MemNSetBitFieldNb (NBPtr, BFCSMapCKE, 0x08040201);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1081,7 +1081,7 @@ MemNSetMaxRdLatBasedOnSeededRxEnDlyKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
index 29aebe3..921014c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G3_DXE)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function selects appropriate Tech functions for the NB.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c
index aa240d0..5861320 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c
@@ -99,7 +99,7 @@ MemNIdentifyDimmConstructorKB (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
index b76d9e8..9b3c9c6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
@@ -111,7 +111,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -252,7 +252,7 @@ MemConstructNBBlockKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -456,7 +456,7 @@ MemNInitNBDataKB (
IEM_INSERT_CODE (IEM_NBBLOCK_INIT, IemInitNBDataOverrideKB, (NBPtr));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -488,7 +488,7 @@ MemNInitDefaultsKB (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function writes training pattern
@@ -511,7 +511,7 @@ MemNWritePatternKB (
MemUWriteCachelines (Address, Pattern, ClCount);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function reads training pattern
@@ -534,7 +534,7 @@ MemNReadPatternKB (
MemUReadCachelines (Buffer, Address, ClCount);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for KB
@@ -556,7 +556,7 @@ memNEnableTrainSequenceKB (
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function obtains PSC table entry pointer by mother board layer design for KB
@@ -600,7 +600,7 @@ memNRelocatePscTableEntryByMotherBoardLayerKB (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c
index e1ffb28..3290221 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c
@@ -97,7 +97,7 @@ RDATA_GROUP (G3_DXE)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -124,7 +124,7 @@ MemNInitializeMctKB (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -215,7 +215,7 @@ MemNFinalizeMctKB (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function create the HT memory map for KB
@@ -305,7 +305,7 @@ MemNHtMemMapInitKB (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -340,7 +340,7 @@ MemNGetUmaSizeKB (
return SizeOfUma;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates 16MB of memory for C6 storage when it is requested to be enabled
@@ -386,7 +386,7 @@ MemNAllocateC6StorageKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -431,7 +431,7 @@ MemNPowerSavingKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function force the ECC symbol size
@@ -453,7 +453,7 @@ MemNForceEccSymbolSizeKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables scrubber temporarily for write access to
@@ -473,7 +473,7 @@ MemNDisableScrubberKB (
NBPtr->GetBitField (NBPtr, BFDisDramScrub);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function restores scrubber settings
@@ -490,7 +490,7 @@ MemNRestoreScrubberKB (
NBPtr->SetBitField (NBPtr, BFDisDramScrub, NBPtr->DisDramScrub);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disable memory hole mappings
@@ -518,7 +518,7 @@ MemNDisableMemHoleMappingKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function restore memory hole mappings
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
index 1b5350a..5bd9e36 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G3_DXE)
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -126,7 +126,7 @@ MemNOtherTimingKB (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
index be956bc..65310a2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
@@ -122,10 +122,10 @@ MemNRdPosTrnKB (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -343,7 +343,7 @@ MemNInitPhyCompKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -373,7 +373,7 @@ MemNBeforeDQSTrainingKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -417,7 +417,7 @@ MemNAfterDQSTrainingKB (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based RcvEn training of KB.
@@ -461,7 +461,7 @@ MemNOverrideRcvEnSeedKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function choose the correct PllLockTime for KB
@@ -484,7 +484,7 @@ MemNAdjustPllLockTimeKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the seed for hardware based WL for KB.
@@ -525,7 +525,7 @@ MemNOverrideWLSeedKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -554,7 +554,7 @@ MemNPFenceAdjustKB (
MULTI_MPSTATE_COPY_TSEFO (NBPtr->NBRegTable, BFPhyFence);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -592,7 +592,7 @@ MemNProgramFence2RxDllKB (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if RdDqsDly needs to be restarted for Kabini
@@ -654,7 +654,7 @@ MemNRdDqsDlyRestartChkKB (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training
@@ -684,7 +684,7 @@ MemNRdPosTrnKB (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips WrDatDly training when a retrain condition is just detected
@@ -730,7 +730,7 @@ MemNHookBfWrDatTrnKB (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets up output driver and write leveling mode in MR1 during WL
@@ -765,7 +765,7 @@ MemNWLMR1KB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs POdtOff to disable/enable receiver pad termination
@@ -788,7 +788,7 @@ MemNProgramPOdtOffKB (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjust the SeedGross value for hardware Receiver Enable Training
@@ -904,7 +904,7 @@ MemNCalcWrDqDqsEarlyKB (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1058,7 +1058,7 @@ MemNPhyPowerSavingMPstateKB (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref according to platform requirements
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
index 724af40..40c7335 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
@@ -99,7 +99,7 @@ STATIC CONST UINT8 InstancesPerTypeKB[8] = {9, 3, 1, 2, 2, 0, 1, 1};
*
*----------------------------------------------------------------------------
*/
-/*-----------------------------------------------------------------------------*/
+
/**
* MemNIsIdSupportedKB
* This function matches the CPU_LOGICAL_ID with certain criteria to
@@ -129,7 +129,7 @@ MemNIsIdSupportedKB (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -317,7 +317,7 @@ MemNCmnGetSetFieldKB (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
index 6ca3859..1b462ba 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
@@ -659,7 +659,7 @@ VOID *MemS3RegListKB[] = {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -753,7 +753,7 @@ MemS3ResumeConstructNBBlockKB (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -804,7 +804,7 @@ MemNS3GetRegLstPtrKB (
return Size;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -835,7 +835,7 @@ MemNS3GetDeviceRegLstKB (
return AGESA_FATAL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -874,7 +874,7 @@ MemNS3SetDfltPhyRegKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -907,7 +907,7 @@ MemNS3SetDynModeChangeKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -936,7 +936,7 @@ MemNS3SetPhyStatusRegKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -984,7 +984,7 @@ MemNS3DisableChannelKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1031,7 +1031,7 @@ MemNS3ChangeMemPStateContextAndFlowNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1108,7 +1108,7 @@ MemNS3GetConPCIMaskKB (
DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1157,7 +1157,7 @@ MemNS3GetCSRKB (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1222,7 +1222,7 @@ MemNS3SetCSRKB (
IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1289,7 +1289,7 @@ MemNS3SetPhyFenceKB (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
index f9e62d0..c09899e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
@@ -94,7 +94,7 @@ extern BUILD_OPT_CFG UserOptions;
extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -195,7 +195,7 @@ MemNCmnInitDefaultsNb (
RefPtr->DramDoubleRefreshRate = UserOptions.CfgDramDoubleRefreshRateEn;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions and variables of NB block.
@@ -237,7 +237,7 @@ MemNInitNBDataNb (
NBPtr->GetBitField = MemNGetBitFieldNb;
NBPtr->SetBitField = MemNSetBitFieldNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -319,7 +319,7 @@ MemNGetMCTSysAddrNb (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if a Rank is enabled.
@@ -345,7 +345,7 @@ MemNRankEnabledNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -390,7 +390,7 @@ MemNSetEccSymbolSizeNb (
MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function flushes the training pattern
@@ -412,7 +412,7 @@ MemNFlushPatternNb (
MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and
@@ -563,7 +563,7 @@ MemNInsDlyCompareTestPatternNb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the training control flow for UNB
@@ -580,7 +580,7 @@ MemNTrainingFlowUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the ECC exclusion range for UNB
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c
index 9ffde28..a37e0f5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c
@@ -105,7 +105,7 @@ MemNS3GetMemClkFreqUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -159,7 +159,7 @@ MemNS3ResumeUNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -182,7 +182,7 @@ MemNS3GetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -205,7 +205,7 @@ MemNS3SetBitFieldNb (
MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -229,7 +229,7 @@ MemNS3RestoreScrubNb (
MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -256,7 +256,7 @@ MemNS3SetPreDriverCalUnb (
MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -282,7 +282,7 @@ MemNS3DctCfgSelectUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -330,7 +330,7 @@ MemNS3GetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -378,7 +378,7 @@ MemNS3SetNBPStateDepRegUnb (
LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -418,7 +418,7 @@ MemNS3SaveNBRegisterUnb (
LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -458,7 +458,7 @@ MemNS3RestoreNBRegisterUnb (
LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -492,7 +492,7 @@ MemNS3SetMemClkFreqValUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -534,7 +534,7 @@ MemNS3ChangeMemPStateContextNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -619,7 +619,7 @@ MemNS3ForceNBP0Unb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -663,7 +663,7 @@ MemNS3ReleaseNBPSUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -727,7 +727,7 @@ MemNSaveHobDataUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -800,7 +800,7 @@ MemNRestoreHobDataUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -836,7 +836,7 @@ MemNModdifyMtrrFixDramModEn (
*
*----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -919,7 +919,7 @@ MemNS3GetSetBitField (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
index 9499278..7cc4f61 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
@@ -103,7 +103,7 @@ MemNAfterStitchMemNb (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -206,7 +206,7 @@ MemNStitchMemoryNb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -286,7 +286,7 @@ MemNPlatformSpecUnb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -326,7 +326,7 @@ MemNDisableDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -407,7 +407,7 @@ MemNStartupDCTUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function ramp up frequency to target frequency
@@ -446,7 +446,7 @@ MemNRampUpFrequencyUnb (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -562,7 +562,7 @@ MemNProgramCycTimingsUnb (
MemNDramPowerMngTimingNb (NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -590,7 +590,7 @@ MemNGetPlatformCfgNb (
return (p < MAX_PLATFORM_TYPES);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -625,7 +625,7 @@ MemNSendZQCmdNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -654,7 +654,7 @@ MemNAfterStitchMemNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -703,7 +703,7 @@ MemNSwapBitsUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Programs Address/command timings, driver strengths, and tri-state fields.
@@ -791,7 +791,7 @@ MemNProgramPlatformSpecNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -832,7 +832,7 @@ MemNEnableSwapIntlvRgnNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -852,7 +852,7 @@ MemNGetMemClkFreqIdUnb (
return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -880,7 +880,7 @@ MemNGetMemClkFreqUnb (
return MemClkFreq;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
@@ -1109,7 +1109,7 @@ MemNSetASRSRTNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function changes NB frequency foras below:
@@ -1176,7 +1176,7 @@ MemNChangeNbFrequencyUnb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1199,7 +1199,7 @@ MemNGetDramTermTblDrvNb (
return RttNom;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1222,7 +1222,7 @@ MemNGetDynDramTermTblDrvNb (
return RttWr;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1240,7 +1240,7 @@ MemNGetMR0WRTblDrvNb (
return (UINT32) (((NBPtr->PsPtr->MR0WR & 0x7) << 9) | ((NBPtr->PsPtr->MR0WR & 0x8) << (13 - 3)));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns MR2[CWL] value for UNB
@@ -1261,7 +1261,7 @@ MemNGetMR2CWLUnb (
return Value32;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets Txp and Txpdll
@@ -1306,7 +1306,7 @@ MemNSetTxpNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is a wrapper to handle or switch NB Pstate for UNB
@@ -1465,7 +1465,7 @@ MemNChangeNbFrequencyWrapUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1517,7 +1517,7 @@ MemNSendMrsCmdUnb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1535,7 +1535,7 @@ MemNGetMR0CLTblDrvNb (
return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1578,7 +1578,7 @@ MemNDramPowerMngTimingNb (
MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 2] - 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets Rcv Fifo
@@ -1598,7 +1598,7 @@ MemTResetRcvFifoUnb (
MemNSetBitFieldNb (TechPtr->NBPtr, BFRstRcvFifo, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
index e52c216..c71a705 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
@@ -122,7 +122,7 @@ MemNInitCPGUnb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes member functions of HW Rx En Training.
@@ -138,7 +138,7 @@ MemNInitDqsTrainRcvrEnHwNb (
{
NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables member functions of Hw Rx En Training.
@@ -161,7 +161,7 @@ MemNDisableDqsTrainRcvrEnHwNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates RcvEn seed value for each rank
@@ -282,7 +282,7 @@ MemNPrepareRcvrEnDlySeedNb (
NBPtr->FamilySpecificHook[RegAccessFence] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Waits specified number of MEMCLKs
@@ -300,7 +300,7 @@ MemNWaitXMemClksNb (
MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Activate command
@@ -334,7 +334,7 @@ MemNRrwActivateCmd (
NBPtr->WaitXMemClks (NBPtr, 75);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function uses the PRBS generator in the DCT to send a DDR Precharge
@@ -375,7 +375,7 @@ MemNRrwPrechargeCmd (
NBPtr->WaitXMemClks (NBPtr, 25);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -401,7 +401,7 @@ MemNGenHwRcvEnReadsUnb (
NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of reads from DRAM using the
@@ -515,7 +515,7 @@ MemNContReadPatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes to DRAM using the
@@ -614,7 +614,7 @@ MemNContWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for comparison results
@@ -672,7 +672,7 @@ MemNCompareTestPatternUnb (
return Pass;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the Error status bits for offset comparison results
@@ -714,7 +714,7 @@ MemNInsDlyCompareTestPatternUnb (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function assigns read/write function pointers to CPG read/write modules.
@@ -741,7 +741,7 @@ MemNInitCPGUnb (
NBPtr->CPGInit = 0;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function generates a continuous stream of writes infinite writes to DRAM using the
@@ -840,7 +840,7 @@ MemNEnableInfiniteWritePatternUnb (
NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function disables the infinite stream of writes to DRAM using the
@@ -891,7 +891,7 @@ MemNDisableInfiniteWritePatternUnb (
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function checks the 180 Error status bits for RD DQS 2D training
@@ -914,7 +914,7 @@ MemN180CompareRdDqs2DPatternUnb (
return NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks the In Phase Error status bits for comparison results for RDDQS 2D training
@@ -938,7 +938,7 @@ MemNInPhaseCompareRdDqs2DPatternUnb (
return NBPtr->GetBitField (NBPtr, BFNibbleErrSts);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function starts the Victim for 2D RdDqs Training Continuous Writes
@@ -988,7 +988,7 @@ MemNStartRdDqs2dVictimContinuousWritesUnb (
NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim chipSelects for 2D RdDqs Training Continuous Writes
@@ -1005,7 +1005,7 @@ MemNInitializeRdDqs2dVictimChipSelContinuousWritesUnb (
NBPtr->SetBitField (NBPtr, BFResetAllErr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the Victim for 2D RdDqs Training
@@ -1034,7 +1034,7 @@ MemNFinalizeRdDqs2dVictimContinuousWritesUnb (
NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Initializes the Victim for 2D RdDqs Training
@@ -1134,7 +1134,7 @@ MemNInitializeRdDqs2dVictimContinuousWritesUnb (
NBPtr->SetBitField (NBPtr, BFLfsrRollOver, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables continuous writes on unused channels
@@ -1161,7 +1161,7 @@ MemNGetPrbs2dRdDqsSeedUnb (
return PrbsSeed;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables/disables continuous writes on unused agressor channels
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnflow.c
index 2c5cb8d..08c399d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnflow.c
@@ -109,7 +109,7 @@ MemNGetPORFreqLimitTblDrvNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -173,7 +173,7 @@ MemNInitMCTNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -209,7 +209,7 @@ MemNPlatformSpecificFormFactorInitTblDrvNb (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -258,7 +258,7 @@ MemNInitDCTNb (
return FALSE;
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* This function clears DCT registers
@@ -279,7 +279,7 @@ MemNCleanupDctRegsNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c
index 5111754..522e212 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c
@@ -103,7 +103,7 @@ MemNSetMTRRrangeNb (
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get max frequency from OEM platform definition, from
@@ -241,7 +241,7 @@ MemNSyncTargetSpeedNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -287,7 +287,7 @@ MemNSyncAddrMapToAllNodesNb (
NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the critical delay difference (CDD)
@@ -351,7 +351,7 @@ MemNCalcCDDNb (
return CDD;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -426,7 +426,7 @@ GetTrainDlyFromHeapNb (
return TrainDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -542,7 +542,7 @@ MemNCPUMemTypingNb (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -603,7 +603,7 @@ MemNUMAMemTypingNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -698,7 +698,7 @@ MemNSetMTRRrangeNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -758,7 +758,7 @@ MemNSetMTRRUmaRegionUCNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function readjusts TOPMEM and MTRRs after allocating storage for C6
@@ -809,7 +809,7 @@ MemNC6AdjustMSRs (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Family-specific hook to override the DdrMaxRate value for families with a
@@ -839,7 +839,7 @@ MemNGetMaxDdrRateUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
index 356d4e3..e6e47c0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
@@ -101,7 +101,7 @@ typedef struct {
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -125,7 +125,7 @@ MemNGetTrainDlyNb (
return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -150,7 +150,7 @@ MemNSetTrainDlyNb (
NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -256,7 +256,7 @@ MemNPhyFenceTrainingUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -335,7 +335,7 @@ MemNTrainPhyFenceNb (
MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
}
-/*-----------------------------------------------------------------------------*/
+
/**
*
* Returns the parameters for a requested delay value to be used in training
@@ -367,8 +367,8 @@ MemNGetTrainDlyParmsUnb (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
+
+
/**
*
*
@@ -540,7 +540,7 @@ MemNcmnGetSetTrainDlyUnb (
}
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the training pattern.
@@ -627,7 +627,7 @@ MemNTrainingPatternInitNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determined the settings for the Reliable Read/Write engine
@@ -692,7 +692,7 @@ MemNSetupHwTrainingEngineUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -720,7 +720,7 @@ MemNGetApproximateWriteDatDelayNb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finalizes the training pattern.
@@ -746,7 +746,7 @@ MemNTrainingPatternFinalizeNb (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the number of Chipselects controlled by each set
@@ -769,7 +769,7 @@ MemNCSPerDelayNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the minimum data eye width in 32nds of a UI for
@@ -812,7 +812,7 @@ MemNMinDataEyeWidthNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the phy registers according to the desired phy VDDIO voltage level
@@ -1010,7 +1010,7 @@ MemNSetSkewMemClkUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function masks the RdDqsDly Bit 0 before writing to register for UNB.
@@ -1030,7 +1030,7 @@ MemNAdjustRdDqsDlyOffsetUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1122,7 +1122,7 @@ MemNInitialzeRxEnSeedlessByteLaneErrorUnb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -1262,7 +1262,7 @@ MemNPhyPowerSavingMPstateUnb (
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
}
-/* -----------------------------------------------------------------------------*/
+
/**
* This function adjusts the Phase Mask based on ECC.
*
@@ -1283,7 +1283,7 @@ MemNAdjust2DPhaseMaskBasedOnEccUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts WrDqsBias before seed scaling
@@ -1306,7 +1306,7 @@ MemNAdjustWrDqsBeforeSeedScalingUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjust RdDqsDly used for MaxRdLatency calculation
@@ -1329,7 +1329,7 @@ MemNAdjustRdDqsDlyForMaxRdLatUnb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* This function collects data for Eye Rim Search
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c
index c8fa9f4..6d96adf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -123,7 +123,7 @@ MemNSwitchDCTNb (
MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is used by families that use a separate DctCfgSel bit to
@@ -155,7 +155,7 @@ MemNDctCfgSelectUnb (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -178,7 +178,7 @@ MemNSwitchChannelNb (
NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -202,7 +202,7 @@ MemNGetBitFieldNb (
return Value;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -224,7 +224,7 @@ MemNSetBitFieldNb (
NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
@@ -261,7 +261,7 @@ MemNBrdcstCheckNb (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all enabled DCTs on a die to a value. Ignore
@@ -291,7 +291,7 @@ MemNBrdcstSetNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set bitfields of all DCTs regardless of if they are being enabled or not on a
@@ -319,7 +319,7 @@ MemNBrdcstSetUnConditionalNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/*-----------------------------------------------------------------------------*/
+
/**
* This function calculates the memory channel index relative to the
* socket, taking the Die number, the Dct, and the channel.
@@ -339,7 +339,7 @@ MemNGetSocketRelativeChannelNb (
return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Poll a bitfield. If the bitfield does not get set to the target value within
@@ -500,7 +500,7 @@ MemNPollBitFieldNb (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
*
@@ -540,7 +540,7 @@ MemNChangeMemPStateContextNb (
MemNSwitchDCTNb (NBPtr, Dct);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function allocates buffer for NB register table
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c
index f1b53d7..4dd6a65 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c
@@ -94,7 +94,7 @@ MemNHwWlPart2Nb (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training
@@ -127,7 +127,7 @@ MemNDQSTiming3Nb (
}
return Retval;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates DQS training for Server NB
@@ -200,7 +200,7 @@ memNSequenceDDR3Nb (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes HW WL at multiple speeds
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
index 348f704..e6a45f9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
@@ -167,7 +167,7 @@ MemPTblDrvOverrideMR10OpSpeed (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This is the default return function of the Platform Specific block. The function always
@@ -191,7 +191,7 @@ MemPConstructPsUDef (
return AGESA_UNSUPPORTED;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function will set the DramTerm and DramTermDyn in the structure of a channel.
@@ -239,7 +239,7 @@ MemPGetDramTerm (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the highest POR supported speed.
@@ -295,7 +295,7 @@ MemPGetPorFreqLimit (
return SpeedLimit;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default function for getting POR speed limit. When a
@@ -312,7 +312,7 @@ MemPGetPORFreqLimitDef (
{
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the seed value of WL and HW RxEn pass 1 training.
@@ -346,7 +346,7 @@ MemPGetPSCPass1Seed (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
@@ -404,7 +404,7 @@ MemPPSCFlow (
return Result;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
@@ -456,7 +456,7 @@ MemPConstructRankTypeMap (
}
}
-/*-----------------------------------------------------------------------------*/
+
/**
* MemPIsIdSupported
* This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
@@ -492,7 +492,7 @@ MemPIsIdSupported (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the rank type map of a channel.
@@ -537,7 +537,7 @@ MemPGetPsRankType (
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs the action for the rest of platform specific configuration such as
@@ -635,7 +635,7 @@ MemPPSCGen (
}
- /* -----------------------------------------------------------------------------*/
+
/**
*
* This function proceeds Table Driven Overriding.
@@ -867,7 +867,7 @@ MemPProceedTblDrvOverride (
return RetVal16;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the speed limit.
@@ -895,7 +895,7 @@ MemPTblDrvOverrideSpeedLimit (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODTs (RttNom and RttWr).
@@ -943,7 +943,7 @@ MemPTblDrvOverrideODT (
return TgtCS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the ODT patterns.
@@ -983,7 +983,7 @@ MemPTblDrvOverrideODTPattern (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides the Ctrl Word 2 and 8.
@@ -1027,7 +1027,7 @@ MemPTblDrvOverrideRC2IBT (
return TgtDimm;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1057,7 +1057,7 @@ MemPTblDrvOverrideMR0WR (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR0[WR].
@@ -1085,7 +1085,7 @@ MemPTblDrvOverrideMR0CL (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function overrides MR10[OperatingSpeed].
@@ -1118,7 +1118,7 @@ MemPTblDrvOverrideMR10OpSpeed (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
@@ -1160,7 +1160,7 @@ MemPCheckTblDrvOverrideConfig (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function checks if platform configuration is matched or not.
@@ -1225,7 +1225,7 @@ MemPCheckTblDrvOverrideConfigSpeedLimit (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Prepare PS table look-up conditions (ie. DIMM type, rank type,...)
@@ -1281,7 +1281,7 @@ MemPPreparePsTabLookupConditions (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Select and return the pointer to the table that supports currently populated
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c
index 1302396..3b73710 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c
@@ -107,7 +107,7 @@ MemPGetMaxFreqSupported (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts the value of max frequency supported from a input table and
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c
index feb3807..91846b5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c
@@ -92,7 +92,7 @@ MemPGetMR0WrCL (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c
index b763cd4..d223a73 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c
@@ -96,7 +96,7 @@ MemPGetODTPattern (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts ODT Pattern value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c
index aef8e98..29a5d1b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c
@@ -98,7 +98,7 @@ MemPGetRttNomWr (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c
index 328ab6a..f03fa10 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c
@@ -98,7 +98,7 @@ MemPGetS2D (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which determine if 2D should be run
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c
index aa9c1cb..53e0887 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c
@@ -97,7 +97,7 @@ MemPGetSAO (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* A sub-function which extracts Slow mode, Address timing and Output driver compensation value
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c
index 113386e..e4508de 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c
@@ -91,7 +91,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Constructs the technology block
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c
index 41834f1..013745e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrwr value for DDR3.
@@ -112,7 +112,7 @@ MemTAdjustTwrwr3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function adjusts the Twrrd value for DDR3.
@@ -138,7 +138,7 @@ MemTAdjustTwrrd3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the LD value for DDR3.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
index bc7a5a0..71138b7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -90,7 +90,7 @@ RDATA_GROUP (G1_PEICC)
*/
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control words
@@ -148,7 +148,7 @@ MemTDramControlRegInit3 (
MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the ControlRC value
@@ -223,7 +223,7 @@ MemTGetCtlWord3 (
return (Data & 0x0F);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends control word command
@@ -260,7 +260,7 @@ MemTSendCtlWord3 (
NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sends specific control words commands before frequency change for certain DRAM buffers.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c
index a023705..738af49 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -92,7 +92,7 @@ RDATA_GROUP (G1_PEICC)
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates software DRAM init for both DCTs
@@ -203,7 +203,7 @@ MemTDramInitSw3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS1 value
@@ -328,7 +328,7 @@ MemTEMRS13 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS2 value
@@ -381,7 +381,7 @@ MemTEMRS23 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the EMRS3 value
@@ -409,7 +409,7 @@ MemTEMRS33 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This sets MRS value
@@ -460,7 +460,7 @@ MemTMRS3 (
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This send all MR commands to a rank in sequence 2-3-1-0
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
index 5e20a3f..36c56d2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -113,7 +113,7 @@ MemTCheckBankAddr3 (
extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DRAM mode
@@ -133,7 +133,7 @@ MemTSetDramMode3 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
@@ -454,7 +454,7 @@ MemTDIMMPresence3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the maximum frequency that each channel is capable to run at.
@@ -534,7 +534,7 @@ MemTSPDGetTargetSpeed3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
@@ -612,7 +612,7 @@ MemTSPDCalcWidth3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize DCT Timing registers as per DIMM SPD.
@@ -781,7 +781,7 @@ MemTAutoCycTiming3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the bank addressing, program Mask values and build a chip-select population map.
@@ -928,7 +928,7 @@ MemTSPDSetBanks3 (
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the low bit that will be swapped to enable CS interleaving
@@ -961,7 +961,7 @@ MemTGetCSIntLvAddr3 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the checksum is correct
@@ -1004,7 +1004,7 @@ MemTCRCCheck3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
@@ -1123,7 +1123,7 @@ MemTSPDGetTCL3 (
return DCTPtr->Timings.CasL;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns the encoded value of bank address.
@@ -1158,7 +1158,7 @@ MemTCheckBankAddr3 (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function returns a pointer to the SPD Buffer of a specific dimm on
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c
index abd7965..24ea21c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -83,7 +83,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings for registered DDR3
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c
index 361b56a..d7ee7a8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -133,7 +133,7 @@ MemTBeginWLTrain3 (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted write levelization
@@ -153,7 +153,7 @@ MemTWriteLevelizationHw3Pass1 (
return MemTWriteLevelizationHw3 (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted write levelization
@@ -177,7 +177,7 @@ MemTWriteLevelizationHw3Pass2 (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares for Phy assisted training.
@@ -205,7 +205,7 @@ MemTPreparePhyAssistedTraining (
return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function revert to normal settings when exiting from Phy assisted training.
@@ -239,7 +239,7 @@ MemTExitPhyAssistedTraining (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executed hardware based write levelization for a specific die
@@ -293,7 +293,7 @@ MemTWriteLevelizationHw3 (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes per DIMM write levelization
@@ -345,7 +345,7 @@ MemTWLPerDimmHw3 (
MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function prepares the DIMMS for Write Levelization
@@ -392,7 +392,7 @@ MemTPrepareDIMMs3 (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs seed values for Write Levelization
@@ -541,7 +541,7 @@ MemTProcConfig3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function begins WL training for a specific DIMM
@@ -671,7 +671,7 @@ MemTBeginWLTrain3 (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs register after Phy assisted training is finish.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c
index 45e00d3..a56f0b7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c
@@ -90,7 +90,7 @@ MemTDefaultTechnologyHook (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function is the default return for non-training technology features
@@ -105,7 +105,7 @@ MemTFeatDef (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the TestFail bit for all CS that fail training.
@@ -133,7 +133,7 @@ MemTMarkTrainFail (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the initial controller environment before training.
@@ -167,7 +167,7 @@ MemTBeginTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the final controller environment after training.
@@ -197,7 +197,7 @@ MemTEndTraining (
NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets all the bytelanes/nibbles to the same delay value
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c
index 3831b16..b284981 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c
@@ -85,7 +85,7 @@ RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initiates Hardware based dram initialization for both DCTs
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
index 01e63f8..d236958 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
@@ -170,7 +170,7 @@ MemTDataEyeSave (
*----------------------------------------------------------------------------
*/
extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for all a Memory channel using
@@ -217,7 +217,7 @@ MemTTrainDQSEdgeDetectSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This Executes Read DQS and Write Data Position training on a chip select pair
@@ -367,7 +367,7 @@ MemTTrainDQSRdWrEdgeDetect (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes DQS position training for both read and write, using
@@ -618,7 +618,7 @@ MemTTrainDQSEdgeDetect (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize the Test Pattern Address for two chip selects and, if this
@@ -681,7 +681,7 @@ MemTInitTestPatternAddress (
return BanksPresent;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Test Conditions for exiting the training loop, set the next delay value,
* and return status
@@ -710,7 +710,7 @@ MemTContinueSweep (
return Status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the next delay value for each bytelane that needs to
@@ -780,7 +780,7 @@ MemTSetNextDelay (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function accepts a delay value in 32nd of a UI and converts it to an
@@ -824,7 +824,7 @@ MemTScaleDelayVal (
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the Center of the Data eye for the specified byte lane
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
index a568f9e..b4d93ae 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
@@ -167,7 +167,7 @@ ClearSampledPassResults (
IN OUT MEM_TECH_BLOCK *TechPtr
);
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Initialize Eye Rim Search
@@ -218,7 +218,7 @@ MemTInitializeEyeRimSearch (
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
* This function collects data for Eye Rim Search
*
@@ -567,7 +567,7 @@ MemT2DRdDQSEyeRimSearch (
}
-/* -----------------------------------------------------------------------------*/
+
/**
* Fill the data eye
*
@@ -652,7 +652,7 @@ MemTEyeFill (
} //x Loop
} // Lane Loop
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get the 1D trained center
@@ -676,7 +676,7 @@ MemTGet1DTrainedEyeCenter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine if the saved value is at or close to the edge
@@ -737,7 +737,7 @@ CheckSaveResAtEdge (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* determine if a BL has been saved
@@ -763,7 +763,7 @@ DetermineSavedState (
return (UINT8) (TechPtr->SavedData->LaneSaved[lane].Vref[xlateY (y)].NegRdDqsDly >> (TechPtr->SavedData->xMax - (x & TechPtr->SavedData->xMax)) & 0x1);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Determine if a failure has occured
@@ -813,7 +813,7 @@ CheckForFail (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Get pass fail state of lane
@@ -851,7 +851,7 @@ GetPassFailValue (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set the Pass/Fail state of lane
@@ -879,7 +879,7 @@ SetPassFailValue (
TechPtr->Local2DData->Lane[lane].Vref[xlateY (y)].NegRdDqsDly |= (result == 0) ? (1 << (TechPtr->SavedData->xMax - (x & TechPtr->SavedData->xMax))) : 0;
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Set the save state of lane
@@ -907,7 +907,7 @@ SetSavedState (
TechPtr->SavedData->LaneSaved[lane].Vref[xlateY (y)].NegRdDqsDly |= (1 << (TechPtr->SavedData->xMax - (x & TechPtr->SavedData->xMax)));
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Allocate data storage
@@ -942,7 +942,7 @@ AllocateSaveLaneStorage (
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Translate Vref into a positive, linear value that can be used as an
@@ -962,7 +962,7 @@ xlateY (
return (y + 0xF) & 0x1F;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* Re-walking the eye rim for each aggressor combination, which invalidates previous Passes
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
index 0fc13f9..e583951 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
@@ -101,7 +101,7 @@ MemT2DRdDQSProcessConvolution (
*/
extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes 2D training for Rd DQS
@@ -285,7 +285,7 @@ MemTAmdRdDqs2DTraining (
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of lanes to program 2D RdDQS training
@@ -312,7 +312,7 @@ MemTCheck2DTrainingPerConfig (
}
return FALSE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of lanes to program 2D RdDQS training
@@ -337,7 +337,7 @@ MemT2DGetMaxLanes (
MaxLanes = 8;
return MaxLanes;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref to internal or external control for 2D RdDQS training
@@ -352,7 +352,7 @@ MemT2DProgramIntExtVrefSelect (
{
TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFVrefSel, (TechPtr->NBPtr->RefPtr->ExternalVrefCtl ? 0x0000 : 0x0001));
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs Vref for 2D RdDQS training
@@ -397,7 +397,7 @@ MemT2DProgramVref (
AGESA_TESTPOINT (TpProcMemAfter2dTrainExtVrefChange, &(TechPtr->NBPtr->MemPtr->StdHeader));
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs RdDQS for 2D RdDQS training
@@ -427,7 +427,7 @@ MemT2DPrograRdDQSDly (
TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDataByteRxDqsDLLDimm3Broadcast, RdDqsTime);
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function stores data for 2D RdDQS training
@@ -472,7 +472,7 @@ StoreResult (
}
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the height of data for 2D RdDQS training
@@ -508,7 +508,7 @@ MemT2DRdDQSHeight (
);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the width for 2D RdDQS training
@@ -526,7 +526,7 @@ MemGet2dRdDQSWidth (
{
return TechPtr->NBPtr->DiamondWidthRd;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function gets the step height for the dimond mask for 2D RdDQS training
@@ -571,7 +571,7 @@ MemCheck2dRdDQSDiamondMaskStep (
}
return status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function applies a mask fo 2D RdDQS training
@@ -861,7 +861,7 @@ MemT2DRdDQSApplyMask (
);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function Examines the convolution function and determines the Max RDqs for
@@ -952,7 +952,7 @@ MemT2DRdDQSProcessConvolution (
}
return status;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the Max RDqs for 2D RdDQS training from convolution
@@ -997,7 +997,7 @@ MemT2DRdDQSPrograMaxRdDQSDly (
}
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the Positive and negative Vref Margin for the current CS
@@ -1080,7 +1080,7 @@ MemT2DRdDQSFindCsVrefMargin (
);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the final Vref Margin for 2D RdDQS training
@@ -1142,7 +1142,7 @@ MemT2DRdDQSFinalVrefMargin (
IDS_HDT_CONSOLE (MEM_FLOW, "Actual Max Vref programmed = %02x \n", MaxRegVref);
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function displays ther results of the 2D search
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c
index 97ca08d..f653a98 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c
@@ -221,7 +221,7 @@ MemTFindMinMaxGrossDlyByte (
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function enables byte based training if called
@@ -346,7 +346,7 @@ MemTDimmByteTrainInit (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function initializes the DQS Positions in preparation for Receiver Enable Training.
@@ -375,7 +375,7 @@ MemTInitDqsPos4RcvrEnByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -401,7 +401,7 @@ MemTSetRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -438,7 +438,7 @@ MemTLoadRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function saves passing DqsRcvEnDly values to the stack
@@ -497,7 +497,7 @@ MemTSaveRcvrEnDlyByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function performs a filtering functionality and saves passing DqsRcvEnDly
@@ -575,7 +575,7 @@ MemTSaveRcvrEnDlyByteFilter (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -634,7 +634,7 @@ MemTCompare1ClPatternByte (
return Pass;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* The function resets the DCT input buffer write pointer.
@@ -661,7 +661,7 @@ MemTResetDctWrPtrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function skips odd chip select if training at 800MT or above.
@@ -693,7 +693,7 @@ MemTSkipChipSelPass1Byte (
(*ChipSelPtr)++;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* MemTSkipChipSelPass2Byte:
@@ -717,7 +717,7 @@ MemTSkipChipSelPass2Byte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the maximum number of byte lanes
@@ -732,7 +732,7 @@ MemTMaxByteLanesByte ( VOID )
return MAX_BYTELANES;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
@@ -747,7 +747,7 @@ MemTDlyTableWidthByte ( VOID )
return MAX_DELAYS;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function writes the Delay value to a certain byte lane
@@ -785,7 +785,7 @@ MemTSetDqsDelayCsrByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs the trained DQS delay for the specified byte lane
@@ -837,7 +837,7 @@ MemTDqsWindowSaveByte (
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay.
@@ -909,7 +909,7 @@ MemTFindMaxRcvrEnDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
@@ -970,7 +970,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByte (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay for UNB
@@ -1039,7 +1039,7 @@ MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb (
return RetVal;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the minimum or maximum gross dly among all the bytes.
@@ -1083,7 +1083,7 @@ MemTFindMinMaxGrossDlyByte (
return MinMaxGrossDly;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function compares test pattern with data in buffer and return a pass/fail bitmap
@@ -1239,7 +1239,7 @@ MemTInitializeVariablesOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function loads the DqsRcvEnDly from saved data and program to additional index
@@ -1273,7 +1273,7 @@ MemTLoadRcvrEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
@@ -1407,7 +1407,7 @@ MemTCheckRcvrEnDlyLimitOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function load the result of write levelization training into RcvrEnDlyOpt,
@@ -1432,7 +1432,7 @@ MemTLoadInitialRcvEnDlyOptByte (
}
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function finds the DIMM that has the largest receiver enable delay that are trained by PMU
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c
index 054a274..40d0fad 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c
@@ -93,7 +93,7 @@ MemTCalcDQSEccTmg (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the DQS ECC timings
@@ -142,7 +142,7 @@ MemTSetDQSEccTmgs (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates the DQS ECC timings
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c
index 58ba34a..1dab627 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c
@@ -105,7 +105,7 @@ MemTDqsTrainRcvrEnHw (
*/
extern UINT16 T1minToFreq[];
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of Phy assisted receiver enable training
@@ -126,7 +126,7 @@ MemTDqsTrainRcvrEnHwPass1 (
return MemTDqsTrainRcvrEnHw (TechPtr, 1);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes second pass of Phy assisted receiver enable training
@@ -157,7 +157,7 @@ MemTDqsTrainRcvrEnHwPass2 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes Phy assisted receiver enable training for current node.
@@ -244,7 +244,7 @@ MemTDqsTrainRcvrEnHw (
return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function calculates final RcvrEnDly for each rank
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index ce295ac..252fa02 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -162,7 +162,7 @@ MemTTrackRxEnSeedlessRdWrSmallWindBLError (
TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE;
return TRUE;
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function sets the RxEn delay
@@ -184,7 +184,7 @@ MemTRdPosRxEnSeedSetDly3 (
TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel / TechPtr->NBPtr->CsPerDelay), ByteLane), RcvEnDly);
TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function determines if the currert RxEn delay settings have failed
@@ -204,7 +204,7 @@ MemTRdPosRxEnSeedCheckRxEndly3 (
TechPtr->DqsRdWrPosSaved = 0;
MemTTrainDQSEdgeDetect (TechPtr);
}
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes RdDQS training and if fails adjusts the RxEn Gross results for
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c
index 450d03f..68e8163 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c
@@ -86,7 +86,7 @@ RDATA_GROUP (G1_PEICC)
*
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function trains Max latency for all dies
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c
index 8114730..a484574 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c
@@ -103,7 +103,7 @@ MemTNewRevTrainingSupport (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -128,7 +128,7 @@ MemTTrainOptRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
index 7fcf6d0..228c985 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
@@ -96,7 +96,7 @@ MemTDqsTrainRcvrEnSw (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes first pass of receiver enable training for all dies
@@ -127,7 +127,7 @@ MemTTrainRcvrEnSwPass1 (
*----------------------------------------------------------------------------
*/
-/* -----------------------------------------------------------------------------*/
+
/**
*
* This function executes receiver enable training for a specific die
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
index feddf9f..a6acaf0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
@@ -162,7 +162,7 @@ TableName[BitFieldIndex] = ( \
#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1))
#define _NOT_USED_ 0
-/* */
+
#define B0_DLY 0
#define B1_DLY 1
#define B2_DLY 2
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c
index bb3ee7b..7cc72ee 100644
--- a/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c
@@ -68,7 +68,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get first block entry in an IVRS (IOMMU) table
*
@@ -102,7 +102,7 @@ LibAmdGetFirstIvrsBlockEntry (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get next block entry in an IVRS (IOMMU) table
*
@@ -141,7 +141,7 @@ LibAmdGetNextIvrsBlockEntry (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get pointer to first Device Entry of an IVHD
*
@@ -182,7 +182,7 @@ LibAmdGetFirstDeviceEntry (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get pointer to Next Device Entry of an IVHD
*
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c
index 2ffeb31..6a20f8e 100644
--- a/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c
@@ -66,7 +66,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get ACPI table.
*
@@ -111,7 +111,7 @@ LibAmdGetAcpiTable (
return AGESA_UNSUPPORTED;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ACPI table.
*
@@ -133,7 +133,7 @@ LibAmdSetAcpiTable (
}
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get ACPI table checksum
*
@@ -159,7 +159,7 @@ LibAmdGetAcpiTableChecksum (
return Checksum;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Update ACPI table checksum
*
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c
index b60f2a3..c2ce33e 100644
--- a/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c
@@ -66,7 +66,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get first block entry in an IVRS (IOMMU) table
*
@@ -104,7 +104,7 @@ LibAmdGetFirstMadtStructure (
return NULL;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get next block entry in an IVRS (IOMMU) table
*
diff --git a/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c
index e241b17..474c216 100644
--- a/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c
+++ b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c
@@ -127,7 +127,7 @@ InitSerialOut (VOID);
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Send format string to debug out
*
@@ -181,7 +181,7 @@ LibAmdTraceDebug (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write string to message buffer
*
@@ -203,7 +203,7 @@ SendStringToBuffer (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write byte to message buffer
*
@@ -228,7 +228,7 @@ SendByteToBuffer (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Integer To String
*
@@ -277,7 +277,7 @@ ItoA (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init debug Output
*
@@ -296,7 +296,7 @@ InitDebugOut (
#endif
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Serial Output
*
@@ -324,7 +324,7 @@ InitSerialOut (
LibAmdIoWrite (AccessWidth8, COM_BASE_ADDRESS + 0x3, &Data, NULL);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init HDT Output
*
@@ -335,7 +335,7 @@ InitSerialOut (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Send Buffer to debug Output
*
@@ -359,7 +359,7 @@ SendBufferToDebugOut (
}
#ifdef HDT_OUT_SUPPORT
-/*----------------------------------------------------------------------------------------*/
+
/**
* Send Buffer to debug Output
*
@@ -402,7 +402,7 @@ SendBufferToHdtOut (
LibAmdMsrWrite (0xC001100A, &MsrCurrentValue, NULL);
}
#endif
-/*----------------------------------------------------------------------------------------*/
+
/**
* Send Buffer to debug Output
*
diff --git a/src/vendorcode/amd/cimx/rd890/amdSbLib.c b/src/vendorcode/amd/cimx/rd890/amdSbLib.c
index 2167029..34582bc 100644
--- a/src/vendorcode/amd/cimx/rd890/amdSbLib.c
+++ b/src/vendorcode/amd/cimx/rd890/amdSbLib.c
@@ -68,7 +68,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Stall
*
@@ -114,7 +114,7 @@ LibAmdSbStall (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -143,7 +143,7 @@ LibAmdSbPmioRead (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -173,7 +173,7 @@ LibAmdSbPmioWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SB Type
*
@@ -182,7 +182,7 @@ LibAmdSbPmioWrite (
*
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
SB_INFO
LibAmdSbGetRevisionInfo (
IN VOID *ConfigPtr
diff --git a/src/vendorcode/amd/cimx/rd890/nbEventLog.c b/src/vendorcode/amd/cimx/rd890/nbEventLog.c
index a57aa44..53ab212 100644
--- a/src/vendorcode/amd/cimx/rd890/nbEventLog.c
+++ b/src/vendorcode/amd/cimx/rd890/nbEventLog.c
@@ -62,7 +62,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* This function logs NB events into a callback.
*
@@ -77,7 +77,7 @@
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbEventLog (
IN UINTN EventClass,
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInit.c b/src/vendorcode/amd/cimx/rd890/nbHtInit.c
index 9b8b2f2..241fd2f 100644
--- a/src/vendorcode/amd/cimx/rd890/nbHtInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInit.c
@@ -87,7 +87,7 @@ UINT8 IBIASCodeTable[] = {
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Init at early post.
*
@@ -293,7 +293,7 @@ HtLibEarlyInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set NB transmitter deemphasis level.
*
@@ -311,7 +311,7 @@ LibHtSetNbTransmitterDeemphasis (
LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REGA7, AccessWidth8, (UINT32)~0x07, NbDeemphasisLevel + BIT7, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable LSx state
*
@@ -362,7 +362,7 @@ LibHtEnableLxState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB validate HY Input parameters
*
@@ -454,7 +454,7 @@ UINT8 SmuWaDelay1us[] = {
0x4 //HT 2600Mhz
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get SMU wa data
*
@@ -494,7 +494,7 @@ LibHtGetSmuWaData (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init RAS macro
*
@@ -565,7 +565,7 @@ NbInitRasParityMacro (
LibAmdMsrWrite (0xC001001a, &SaveTom, (AMD_CONFIG_PARAMS *)NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for all NB.
*
@@ -584,7 +584,7 @@ AmdHtInitializer (
Status = LibNbApiCall (HtLibInitializer, ConfigPtr);
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* HT config structure initializer
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInterface.c b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
index 68f84da..c06cc3c 100644
--- a/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
@@ -65,7 +65,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Early system wide HT init
*
@@ -74,7 +74,7 @@
* @param[in] ConfigPtr Northbridges configuration block pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
AmdHtInit (
@@ -89,7 +89,7 @@ AmdHtInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Early Nb HT init.
*
@@ -98,7 +98,7 @@ AmdHtInit (
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
NbHtInit (
diff --git a/src/vendorcode/amd/cimx/rd890/nbInit.c b/src/vendorcode/amd/cimx/rd890/nbInit.c
index 0d263d5..aa9ffe1 100644
--- a/src/vendorcode/amd/cimx/rd890/nbInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbInit.c
@@ -64,7 +64,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Early post validate input parameters
*
@@ -99,7 +99,7 @@ NbLibEarlyPostInitValidateInput (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Mid/Late post validate input parameters
*
@@ -134,7 +134,7 @@ NbLibPostInitValidateInput (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Prepare NB to boot to OS.
*
@@ -154,7 +154,7 @@ NbLibPrepareToOS (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Multiple NB support
*
@@ -187,7 +187,7 @@ NbMultiNbIocInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set NB SSID/SVID.
*
@@ -214,7 +214,7 @@ NbLibSetSSID (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Setup UnitId clamping
*
@@ -257,7 +257,7 @@ NbLibSetupClumping (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set top of memory in NB.
* NB will not pass to CPU any upstream DMA request to address above TOM and TOM2
@@ -299,7 +299,7 @@ NbLibSetTopOfMemory (
}
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Loget COre APic ID and dtore to scratch
*
@@ -324,7 +324,7 @@ NbLibGetCore0ApicId (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Direct NMI message to Core 0
*
@@ -350,7 +350,7 @@ NbLibSetNmiRouting (
pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for all NB.
*
@@ -370,7 +370,7 @@ AmdNbInitializer (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB config structure initializer
*
@@ -379,7 +379,7 @@ AmdNbInitializer (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
NbLibInitializer (
IN OUT AMD_NB_CONFIG *pConfig
diff --git a/src/vendorcode/amd/cimx/rd890/nbInitializer.c b/src/vendorcode/amd/cimx/rd890/nbInitializer.c
index db3aca7..883c593 100644
--- a/src/vendorcode/amd/cimx/rd890/nbInitializer.c
+++ b/src/vendorcode/amd/cimx/rd890/nbInitializer.c
@@ -74,7 +74,7 @@ NbInitializer (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for all NB.
*
@@ -94,7 +94,7 @@ AmdInitializer (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB structure initializer.
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbInterface.c b/src/vendorcode/amd/cimx/rd890/nbInterface.c
index f833a16..17b2a36 100644
--- a/src/vendorcode/amd/cimx/rd890/nbInterface.c
+++ b/src/vendorcode/amd/cimx/rd890/nbInterface.c
@@ -65,7 +65,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Init all NB at early POST.
*
@@ -87,7 +87,7 @@ AmdEarlyPostInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Init at early post.
*
@@ -121,7 +121,7 @@ NbEarlyPostInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Init all NB at mid POST.
*
@@ -144,7 +144,7 @@ AmdMidPostInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Init at mid POST.
*
@@ -173,7 +173,7 @@ NbMidPostInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Init all NB at late POST.
*
@@ -195,7 +195,7 @@ AmdLatePostInit (
#endif
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Init at late post.
*
@@ -228,7 +228,7 @@ NbLatePostInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Init all NB at S3 Resume.
*
@@ -251,7 +251,7 @@ AmdS3InitIommu (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Init all NB at S3 Resume.
*
@@ -273,7 +273,7 @@ AmdS3Init (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Init at S3
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbIoApic.c b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
index d67a35b..2f3c6f0 100644
--- a/src/vendorcode/amd/cimx/rd890/nbIoApic.c
+++ b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
@@ -109,7 +109,7 @@ CONST APIC_REGISTER_INFO gApicRegisterInfoTable[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Configure IO APIC
* Enable IO APIC base address decoding. Enable default forwarding interrupt to SB
@@ -118,7 +118,7 @@ CONST APIC_REGISTER_INFO gApicRegisterInfoTable[] = {
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
NbLibSetIOAPIC (
IN AMD_NB_CONFIG *pConfig
diff --git a/src/vendorcode/amd/cimx/rd890/nbIommu.c b/src/vendorcode/amd/cimx/rd890/nbIommu.c
index 31e4a89..b736eb8 100644
--- a/src/vendorcode/amd/cimx/rd890/nbIommu.c
+++ b/src/vendorcode/amd/cimx/rd890/nbIommu.c
@@ -338,7 +338,7 @@ IommuTopologyInit (
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if IOMMU enable on platform
*
@@ -365,7 +365,7 @@ NbIommuEnabled (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu Initialization for all NB in system.
*
@@ -401,7 +401,7 @@ NbIommuInit (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu Initialization for all NB in system.
*
@@ -434,7 +434,7 @@ NbIommuInitS3 (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu HW Initialization for all NB in system.
*
@@ -459,7 +459,7 @@ NbIommuHwInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu HW Initialization for all NB in system.
*
@@ -484,7 +484,7 @@ NbIommuHwTopologyInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu Initialization for all NB in system.
*
@@ -549,7 +549,7 @@ NbIommuAcpiInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Iommu IVRS fixup for APICS
*
@@ -665,7 +665,7 @@ UINT32 IommuMmioInitTable[] = {
0x2008, 0x0
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Nb Iommu Initialization.
*
@@ -753,7 +753,7 @@ IommuInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Iommu Initialization of topology specific data.
*
@@ -789,7 +789,7 @@ L2_HASH_CONTROL HashControls[] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set L2 Cache Hash Control based on maximum Bus, Dev, Function found
*
@@ -841,7 +841,7 @@ IommuInitL2CacheControl (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check to see if current PCI Address is an IOMMU
*
@@ -868,7 +868,7 @@ IommuCheckEnable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check an RD890 PCIE bridge to see if hot plug is enabled
*
@@ -898,7 +898,7 @@ IommuCheckHp (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check a PCIE device to see if it supports phantom functions
*
@@ -930,7 +930,7 @@ IommuCheckPhantom (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check to see if current PCI Address is a multi-port PCIE core
*
@@ -972,7 +972,7 @@ IommuGetL1 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD Device Entries
*
@@ -1005,7 +1005,7 @@ IommuGetLog2 (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVRS Header for IOMMU ACPI table
*
@@ -1023,7 +1023,7 @@ IommuPlaceHeader (
LibAmdMemCopy (HeaderPtr, &RD890S_DfltHeader, sizeof (IOMMU_IVRS_HEADER), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVMD (memory device) Create all IVMD entries for a single exclusion table
*
@@ -1065,7 +1065,7 @@ IommuPlaceIvmdAndExclusions (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD (hardware device) Entry for IOMMU ACPI table
*
@@ -1115,7 +1115,7 @@ IommuPlaceIvhdAndScanDevices (
HeaderPtr->Length += IvhdPtr->Length;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD Device Entries
*
@@ -1165,7 +1165,7 @@ IommuIvhdNorthbridgeDevices (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD Device Entries
*
@@ -1212,7 +1212,7 @@ IommuIvhdSouthbridgeDevices (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD Device Entries
*
@@ -1241,7 +1241,7 @@ IommuIvhdApicsAndHpets (
#endif
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD device entry (type 2 for single function or 3/4 for multifunction) at end of IVHD entry
*
@@ -1476,7 +1476,7 @@ IommuCreateDeviceEntry (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Place IVHD device entry (type 2 for single function or 3/4 for multifunction) at end of IVHD entry
*
@@ -1516,7 +1516,7 @@ IommuRecordBusDevFuncInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Append data entry to IVRS
*
@@ -1551,7 +1551,7 @@ IommuCreate4ByteEntry (
CIMX_TRACE ((TRACE_DATA (NULL, CIMX_NB_TRACE), "[NBIOMMU]Added entry - [0x%x]\n", Buffer));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Append data entry to IVRS
*
@@ -1593,7 +1593,7 @@ IommuCreate8ByteEntry (
CIMX_TRACE ((TRACE_DATA (NULL, CIMX_NB_TRACE), "[NBIOMMU]Added entry - [0x%llx]\n", Buffer));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set checksum, IvInfo, finish IVRS table
*
@@ -1627,7 +1627,7 @@ IommuFinalizeIvrs (
//LibAmdUpdateAcpiTableChecksum (HeaderPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Nb Iommu Fixup of IVRS APIC entries
*
@@ -1683,7 +1683,7 @@ IommuGetApicBaseAddress (
return ((UINT64) (Data & 0xFFFFFF00));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Nb Iommu Fixup of IVRS APIC entries
*
@@ -1713,7 +1713,7 @@ IommuGetApicId (
return 0xFF;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disconnect unused PCIe core from IOMMU block.
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbLib.c b/src/vendorcode/amd/cimx/rd890/nbLib.c
index 184683a..5b70ae0 100644
--- a/src/vendorcode/amd/cimx/rd890/nbLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbLib.c
@@ -65,7 +65,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get silicon type and revision info.
*
@@ -74,7 +74,7 @@
* @param[in] NbConfigPtr configuration structure pointer.
* @retval NB_INFO Northbrige Info Structure.
*/
-/*----------------------------------------------------------------------------------------*/
+
NB_INFO
LibNbGetRevisionInfo (
IN AMD_NB_CONFIG *NbConfigPtr
@@ -130,7 +130,7 @@ LibNbGetRevisionInfo (
return RevisionInfo;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Call Back routine.
*
@@ -140,7 +140,7 @@ LibNbGetRevisionInfo (
* @param[in] Data Callback specific data.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
LibNbCallBack (
IN UINT32 CallBackId,
@@ -161,7 +161,7 @@ LibNbCallBack (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Call Back routine.
*
@@ -170,7 +170,7 @@ LibNbCallBack (
* @param[in] SystemApi Pointer to System API
* @param[in] ConfigPtr Northbridge block configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
LibSystemApiCall (
IN SYSTEM_API SystemApi,
@@ -192,7 +192,7 @@ LibSystemApiCall (
return Workspace.Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Call Back routine.
*
@@ -201,7 +201,7 @@ LibSystemApiCall (
* @param[in] NbApi Pointer to NB API
* @param[in] ConfigPtr Northbridge block configuration structure pointer
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
LibNbApiCall (
IN NB_API NbApi,
@@ -229,7 +229,7 @@ LibNbApiCall (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI register.
*
@@ -240,7 +240,7 @@ LibNbApiCall (
* @param[in] Value Pointer to new register value.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciWrite (
@@ -256,7 +256,7 @@ LibNbPciWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI register
*
@@ -268,7 +268,7 @@ LibNbPciWrite (
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciRead (
IN UINT32 Address,
@@ -282,7 +282,7 @@ LibNbPciRead (
LibAmdPciRead (Width, DeviceAddress, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI register
*
@@ -294,7 +294,7 @@ LibNbPciRead (
* @param[in] Data OR Mask.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciRMW (
IN UINT32 Address,
@@ -310,7 +310,7 @@ LibNbPciRMW (
LibNbPciWrite (Address, Width, &Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PCI Index/Data Address space
*
@@ -322,7 +322,7 @@ LibNbPciRMW (
* @param[in] Value Pointer to save register value.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciIndexRead (
@@ -339,7 +339,7 @@ LibNbPciIndexRead (
LibNbPciRead (Address + IndexOffset, Width, Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PCI Index/Data Address space
*
@@ -351,7 +351,7 @@ LibNbPciIndexRead (
* @param[in] Value Pointer to save register value.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciIndexWrite (
@@ -368,7 +368,7 @@ LibNbPciIndexWrite (
LibNbPciWrite (Address + IndexOffset , Width, Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write PCI Index/Data Address space
*
@@ -381,7 +381,7 @@ LibNbPciIndexWrite (
* @param[in] Data OR Mask.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbPciIndexRMW (
@@ -399,7 +399,7 @@ LibNbPciIndexRMW (
LibNbPciIndexWrite (Address, Index, Width, &Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Program table of indirect register.
*
@@ -411,7 +411,7 @@ LibNbPciIndexRMW (
* @param[in] Length Number of entry in indirect register table.
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbIndirectTableInit (
IN UINT32 Address,
@@ -427,7 +427,7 @@ LibNbIndirectTableInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCI capability pointer
*
@@ -436,7 +436,7 @@ LibNbIndirectTableInit (
*
*
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT8
LibNbFindPciCapability (
@@ -463,7 +463,7 @@ LibNbFindPciCapability (
}
return CapabilityPtr;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Find PCIe extended capability pointer
*
@@ -472,7 +472,7 @@ LibNbFindPciCapability (
*
*
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT16
LibNbFindPcieExtendedCapability (
@@ -500,7 +500,7 @@ LibNbFindPcieExtendedCapability (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read IO space
*
@@ -511,7 +511,7 @@ LibNbFindPcieExtendedCapability (
* @param[in] Value Pointer to save IO port value;
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbIoRead (
@@ -524,7 +524,7 @@ LibNbIoRead (
LibAmdIoRead (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write IO space
*
@@ -547,7 +547,7 @@ LibNbIoWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write IO space
*
@@ -559,7 +559,7 @@ LibNbIoWrite (
* @param[in] Data OR Mask
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbIoRMW (
@@ -577,7 +577,7 @@ LibNbIoRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU HT link Phy register
*
@@ -589,7 +589,7 @@ LibNbIoRMW (
* @param[in] Value Pointer to save register value
* @param[in] NbConfigPtr Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbCpuHTLinkPhyRead (
@@ -612,7 +612,7 @@ LibNbCpuHTLinkPhyRead (
LibNbPciRead (CpuPciAddress.AddressValue | (LinkId * 8 + 0x184), AccessWidth32, Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write CPU HT link Phy register
*
@@ -624,7 +624,7 @@ LibNbCpuHTLinkPhyRead (
* @param[in] Value Pointer to new register value
* @param[in] NbConfigPtr Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbCpuHTLinkPhyWrite (
@@ -648,7 +648,7 @@ LibNbCpuHTLinkPhyWrite (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write CPU HT link Phy register
*
@@ -661,7 +661,7 @@ LibNbCpuHTLinkPhyWrite (
* @param[in] Data OR Mask.
* @param[in] NbConfigPtr Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbCpuHTLinkPhyRMW (
IN UINT8 Node,
@@ -679,7 +679,7 @@ LibNbCpuHTLinkPhyRMW (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Clock Config space access.
* Enable access to Clock Config Space at 0:0:1 PCI address.
@@ -687,7 +687,7 @@ LibNbCpuHTLinkPhyRMW (
*
* @param[in] pConfig Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbEnableClkConfig (
@@ -697,7 +697,7 @@ LibNbEnableClkConfig (
LibNbPciRMW (NB_SBDFO | NB_PCI_REG4C, AccessS3SaveWidth8, (UINT32)~BIT0, BIT0, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Disable Clock Config space access.
* Disable access to Clock Config Space at 0:0:1 PCI address.
@@ -705,7 +705,7 @@ LibNbEnableClkConfig (
*
* @param[in] pConfig Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbDisableClkConfig (
@@ -716,7 +716,7 @@ LibNbDisableClkConfig (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if PCI Device Present
*
@@ -728,7 +728,7 @@ LibNbDisableClkConfig (
* @retval TRUE Device present.
* @retval FALSE Device not present.
*/
-/*----------------------------------------------------------------------------------------*/
+
BOOLEAN
LibNbIsDevicePresent (
@@ -740,7 +740,7 @@ LibNbIsDevicePresent (
LibNbPciRead (Device.AddressValue, AccessWidth32, &VendorId, NbConfigPtr);
return (VendorId == 0xffffffff)?FALSE:TRUE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if IOMMU enabled
*
@@ -751,7 +751,7 @@ LibNbIsDevicePresent (
* @retval TRUE IOMMU not enabled.
* @retval FALSE IOMMU not enabled.
*/
-/*----------------------------------------------------------------------------------------*/
+
BOOLEAN
LibNbIsIommuEnabled (
IN AMD_NB_CONFIG *NbConfigPtr
@@ -770,7 +770,7 @@ LibNbIsIommuEnabled (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reverse bit in DWORD.
* Reverse bits in bitfield inside DWORD.
@@ -781,7 +781,7 @@ LibNbIsIommuEnabled (
* @param[in] StopBit Stop bit.
* @retval Reversed Value.
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT32
LibNbBitReverse (
@@ -805,7 +805,7 @@ LibNbBitReverse (
}
return Data;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read CPU family
*
@@ -825,7 +825,7 @@ LibNbGetCpuFamily (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Load Firmware block
*
@@ -859,7 +859,7 @@ LibNbLoadMcuFirmwareBlock (
LibNbDisableClkConfig (NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read SMU firmware ram
*
@@ -888,7 +888,7 @@ LibNbReadMcuRam (
return Value;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* MCU Control
*
@@ -915,7 +915,7 @@ LibNbMcuControl (
LibNbDisableClkConfig (NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read/Modify/Write memory space
*
@@ -927,7 +927,7 @@ LibNbMcuControl (
* @param[in] Data OR Mask
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbMemRMW (
@@ -944,7 +944,7 @@ LibNbMemRMW (
LibNbMemWrite (Address, Width, &Value, NbConfigPtr);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read memory space
*
@@ -955,7 +955,7 @@ LibNbMemRMW (
* @param[in] Value Pointer to memory to store value
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbMemRead (
@@ -968,7 +968,7 @@ LibNbMemRead (
LibAmdMemRead (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write memory space
*
@@ -979,7 +979,7 @@ LibNbMemRead (
* @param[in] Value Pointer to memory to get value
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbMemWrite (
@@ -992,7 +992,7 @@ LibNbMemWrite (
LibAmdMemWrite (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan Pci Bridge
*
@@ -1032,7 +1032,7 @@ LibNbScanPciBridgeBuses (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan Pci Bus
*
@@ -1041,7 +1041,7 @@ LibNbScanPciBridgeBuses (
* @param[in] This Pointer to PCI topology scan protocol
* @param[in] Device Pci address device to start bus scan from
*/
-/*----------------------------------------------------------------------------------------*/
+
SCAN_STATUS
LibNbScanPciBus (
IN PCI_SCAN_PROTOCOL *This,
@@ -1067,7 +1067,7 @@ LibNbScanPciBus (
return SCAN_FINISHED;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Scan Pci Device
*
@@ -1076,7 +1076,7 @@ LibNbScanPciBus (
* @param[in] This Pointer to PCI topology scan protocol
* @param[in] Device Pci address device to scan
*/
-/*----------------------------------------------------------------------------------------*/
+
SCAN_STATUS
LibNbScanPciDevice (
@@ -1107,14 +1107,14 @@ LibNbScanPciDevice (
return SCAN_FINISHED;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set default Indexes
*
*
* @param[in] NbConfigPtr Northbridge configuration block pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
LibNbSetDefaultIndexes (
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
index baa3b05..dd25045 100644
--- a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
@@ -79,7 +79,7 @@ AmdMaskedMemoryInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Mask Memory
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbMiscInit.c b/src/vendorcode/amd/cimx/rd890/nbMiscInit.c
index 65af807..2a2dcfc 100644
--- a/src/vendorcode/amd/cimx/rd890/nbMiscInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbMiscInit.c
@@ -64,7 +64,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for all NB.
*
@@ -83,7 +83,7 @@ AmdMiscInitializer (
Status = LibNbApiCall (MiscInitializer, ConfigPtr);
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB structure initializer.
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
index 8aa4139..97b67a0 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
@@ -81,7 +81,7 @@ PcieSetDeviceAspm (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Port ASPM.
* Enable ASPM states on RC and EP. Only states supported by both RC and EP
@@ -93,7 +93,7 @@ PcieSetDeviceAspm (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
PcieAsmpEnableOnPort (
IN PORT PortId,
@@ -141,7 +141,7 @@ PcieAsmpEnableOnPort (
return ;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Common Clock on PCIe Link
*
@@ -152,7 +152,7 @@ PcieAsmpEnableOnPort (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableCommonClock (
@@ -195,7 +195,7 @@ PcieAspmEnableCommonClock (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set "Common Clock" enable on function
*
@@ -205,7 +205,7 @@ PcieAspmEnableCommonClock (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmCommonClockOnDevice (
IN PCI_ADDR Device,
@@ -226,7 +226,7 @@ PcieAspmCommonClockOnDevice (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set "Common Clock" enable on function
*
@@ -236,7 +236,7 @@ PcieAspmCommonClockOnDevice (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmCommonClockOnFunction (
IN PCI_ADDR Function,
@@ -249,7 +249,7 @@ PcieAspmCommonClockOnFunction (
LibNbPciRMW (Function.AddressValue | (PcieCapPtr + 0x10) , AccessS3SaveWidth8, (UINT32)~(BIT6), BIT6, pConfig);
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable ASPM on PCIe Link
*
@@ -265,7 +265,7 @@ PcieAspmCommonClockOnFunction (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnLink (
@@ -303,7 +303,7 @@ PcieAspmEnableOnLink (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on all function of PCI device
*
@@ -316,7 +316,7 @@ PcieAspmEnableOnLink (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnDevice (
IN PCI_ADDR Device,
@@ -337,7 +337,7 @@ PcieAspmEnableOnDevice (
}
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set ASMP State on PCIe device function
*
@@ -350,7 +350,7 @@ PcieAspmEnableOnDevice (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmEnableOnFunction (
IN PCI_ADDR Function,
@@ -365,7 +365,7 @@ PcieAspmEnableOnFunction (
}
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Port/Endpoint ASMP capability
*
@@ -376,7 +376,7 @@ PcieAspmEnableOnFunction (
*
* @retval Bitmap of actual supported Lx states
*/
- /*----------------------------------------------------------------------------------------*/
+
UINT8
PcieAspmGetPmCapability (
IN PCI_ADDR Device,
@@ -394,7 +394,7 @@ PcieAspmGetPmCapability (
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Scan PCIe topology
*
@@ -405,7 +405,7 @@ PcieAspmGetPmCapability (
*
* @retval SCAN_FINISHED Scan for device finished.
*/
- /*----------------------------------------------------------------------------------------*/
+
SCAN_STATUS
PcieSetDeviceAspm (
IN PCI_SCAN_PROTOCOL *This,
@@ -463,7 +463,7 @@ PcieSetDeviceAspm (
return SCAN_FINISHED;
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Scan RC PCIe topology to setup ASPM
*
@@ -478,7 +478,7 @@ PcieSetDeviceAspm (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
- /*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmSetOnRc (
IN PCI_ADDR Device,
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c
index 635b960..662596f 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c
@@ -61,7 +61,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate CPL buffers
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c
index 3965147..91dab57 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c
@@ -123,7 +123,7 @@ PcieMiscInitTable[] = {
} //[17][16]Sets Electrical Idle Threshold
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc Initialization prior port training.
*
@@ -267,7 +267,7 @@ INDIRECT_REG_ENTRY PcieRd790CoreInitTable[] = {
},
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Core registers
*
@@ -315,7 +315,7 @@ PcieLibCommonCoreInit (
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Core after training is completed
*
@@ -404,7 +404,7 @@ INDIRECT_REG_ENTRY PciePortInitTable[] = {
BIT16 + BIT18
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init port registers
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c
index 087a7f3..23b3e10 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c
@@ -92,7 +92,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Ports Hotplug capability.
* Initialize hotplug controller init port hotplug capability
@@ -103,7 +103,7 @@
* @retval AGESA_SUCCESS Hotplug controller successfully initialized.
* @retval AGESA_FAIL Failure during initialization of hotplug controller.
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT32
PcieInitHotplug (
IN AMD_NB_CONFIG *pConfig
@@ -164,7 +164,7 @@ PcieInitHotplug (
return ServerHotplugPortMask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Ports Hotplug capability.
* Initialize hotplug controller init port hotplug capability
@@ -175,7 +175,7 @@ PcieInitHotplug (
* @retval AGESA_SUCCESS Hotplug controller successfully initialized.
* @retval AGESA_FAIL Failure during initialization of hotplug controller.
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
PcieCheckHotplug (
IN UINT32 ServerHotplugPortMask,
@@ -217,7 +217,7 @@ PcieCheckHotplug (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init Ports Hotplug capability.
* Initialize hotplug controller init port hotplug capability
@@ -228,7 +228,7 @@ PcieCheckHotplug (
* @retval AGESA_SUCCESS Hotplug controller successfully initialized.
* @retval AGESA_FAIL Failure during initialization of hotplug controller.
*/
-/*----------------------------------------------------------------------------------------*/
+
/*
AGESA_STATUS
PcieInitHotplug (
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
index d725b64..22bcbdc 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
@@ -68,7 +68,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE Init for all NB.
* Basic programming / EP training. After this call EP are fully operational.
@@ -78,7 +78,7 @@
* @param[in] ConfigPtr Northbridges configuration block pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
AmdPcieEarlyInit (
IN OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
@@ -90,7 +90,7 @@ AmdPcieEarlyInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge PCIE Init.
* Basic programming / EP training. After this call EP are fully operational on particular NB.
@@ -100,7 +100,7 @@ AmdPcieEarlyInit (
* @param[in] NbConfigPtr Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieEarlyInit (
IN OUT AMD_NB_CONFIG *NbConfigPtr
@@ -124,7 +124,7 @@ PcieEarlyInit (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc initialization prior port link training started
*
@@ -133,7 +133,7 @@ PcieEarlyInit (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PciePreTrainingInit (
IN OUT AMD_NB_CONFIG *pConfig
@@ -173,7 +173,7 @@ PciePreTrainingInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc initialization after port training complete
*
@@ -182,7 +182,7 @@ PciePreTrainingInit (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieAfterTrainingInit (
IN AMD_NB_CONFIG *pConfig
@@ -203,7 +203,7 @@ PcieAfterTrainingInit (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Train PCIE Ports
*
@@ -212,7 +212,7 @@ PcieAfterTrainingInit (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieInitPorts (
IN OUT AMD_NB_CONFIG *pConfig
@@ -233,7 +233,7 @@ PcieInitPorts (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Train PCIE Ports selected for this stage
*
@@ -242,7 +242,7 @@ PcieInitPorts (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieInitSelectedPorts (
IN UINT16 SelectedPortMask,
@@ -313,7 +313,7 @@ PcieInitSelectedPorts (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check link state on selected ports.
*
@@ -322,7 +322,7 @@ PcieInitSelectedPorts (
* @param[in] SelectedPortMask Bitmap of port ID selected for training.
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieCheckSelectedPorts (
IN UINT16 SelectedPortMask,
@@ -437,7 +437,7 @@ PcieCheckSelectedPorts (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Workaround for broken TX line.
*
@@ -446,7 +446,7 @@ PcieCheckSelectedPorts (
* @param[in] SelectedPortMask Bitmap of port ID selected for training.
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieBrokenLaneWorkaround (
IN UINT16 SelectedPortMask,
@@ -473,7 +473,7 @@ PcieBrokenLaneWorkaround (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Workaround for device violating Gen2 spec.
* Downgrade link speed to Gen1.
@@ -483,7 +483,7 @@ PcieBrokenLaneWorkaround (
* @param[in] SelectedPortMask Bitmap of port ID selected for training.
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieGen2Workaround (
IN UINT16 SelectedPortMask,
@@ -524,7 +524,7 @@ PcieGen2Workaround (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Try to recover system by issuing system wide PCI reset.
*
@@ -533,7 +533,7 @@ PcieGen2Workaround (
* @param[in] PortsLinkStatus Array of link status for every Port
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieMiscWorkaround (
IN PCIE_LINK_STATUS *PortsLinkStatus,
@@ -562,7 +562,7 @@ PcieMiscWorkaround (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check VCO negotiation complete.
* Routine will retry retrain device infinitely if VCO negotiation is failing.
@@ -573,7 +573,7 @@ PcieMiscWorkaround (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieCheckVco (
IN UINT16 SelectedPortMask,
@@ -627,7 +627,7 @@ PcieCheckVco (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bit map of ports with particular link status
*
@@ -637,7 +637,7 @@ PcieCheckVco (
* @param[in] LinkStatus LinkStatus to search for.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
UINT16
PcieFindPortsWithLinkStatus (
IN PCIE_LINK_STATUS *PortLinkStatus,
@@ -653,7 +653,7 @@ PcieFindPortsWithLinkStatus (
}
return PortMask;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Gather link state for selected ports.
*
@@ -664,7 +664,7 @@ PcieFindPortsWithLinkStatus (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
PCIE_LINK_STATUS
PcieGetPortsLinkStatus (
IN UINT16 SelectedPortMask,
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
index 5f0de59..7d46677 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
@@ -67,7 +67,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd PCIE Late Init for all NB.
*
@@ -86,7 +86,7 @@ AmdPcieLateInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd PCIE Late Init for all NB.
*
@@ -106,7 +106,7 @@ AmdPcieLateInitWa (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd PCIE Special Init for all NB.
*
@@ -125,7 +125,7 @@ AmdPcieValidatePortState (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd PCIE S3 Init fro all NB.
*
@@ -144,7 +144,7 @@ AmdPcieS3Init (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB PCIE Late Init.
* Extended programming. Enable power management and misc capability.
@@ -175,7 +175,7 @@ PcieLateInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB PCIE Late Init.
* Extended programming. Enable power management and misc capability.
@@ -205,7 +205,7 @@ PcieLateInitWa (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Late init PCIE Ports
*
@@ -259,7 +259,7 @@ PcieLateInitPorts (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Late init PCIE Cores. Core level feature/power management etc.
*
@@ -302,7 +302,7 @@ PcieLateInitCores (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Set up NB-SB virtual channel for audio traffic
*
@@ -333,7 +333,7 @@ PcieNbSbSetupVc (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Late common Port Init
*
@@ -354,7 +354,7 @@ PcieLateCommonPortInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Initiate SW Gen2 switch
*
@@ -405,7 +405,7 @@ PcieInitiateSoftwareGen2 (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitiateSoftwareGen2 Exit\n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Validate input parameters configuration for PCie Late Init call.
*
@@ -437,7 +437,7 @@ PcieLateValidateConfiguration (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PcieValidatePortState
* Port disable or port visibility control
@@ -462,7 +462,7 @@ PcieValidatePortState (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* PciePortsVisibleOrDisable
* Set ports always visible or disable based on input parameter
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
index 161e148..c09a019 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
@@ -59,7 +59,7 @@
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc Initialization in late init
*
@@ -125,7 +125,7 @@ PcieLibLateInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc Initialization in validate port state
*
@@ -197,7 +197,7 @@ PcieLibValidatePortStateInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable LCLK clock gating or shutdown LCLK clock banch if possible
*
@@ -286,7 +286,7 @@ PcieLibManageLclkClock (
LibNbDisableClkConfig (pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power Off Pll for unused lanes.
*
@@ -356,7 +356,7 @@ PcieLibPowerOffPll (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable TX clock gating or shutdown TX clock if possible
*
@@ -415,7 +415,7 @@ PcieLibManageTxClock (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable Pll Power Down in L1.
*
@@ -457,7 +457,7 @@ PcieLibEnablePllPowerOffInL1 (
LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG02 | CoreAddress, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc. core setting.
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
index 98969a1..e0b2461 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
@@ -242,7 +242,7 @@ CONST PORT_STATIC_INFO PortInfoTable[] = {
-/*----------------------------------------------------------------------------------------*/
+
/**
* Port Training Control
*
@@ -276,7 +276,7 @@ PcieLibPortTrainingControl (
);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCI address of Port.
* Function return pcie Address based on port mapping and core configuration.
@@ -326,7 +326,7 @@ PcieLibGetPortPciAddress (
return Port;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Core register selector.
* Function return selector to access BIFNB register space for selected core
@@ -345,7 +345,7 @@ PcieLibGetCoreAddress (
return PcieLibGetCoreInfo (CoreId, pConfig)->CoreSelector;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Core Id
* Function return PCIE core ID base on Port ID
@@ -424,7 +424,7 @@ PcieMiscInitTable[] = {
UINT8 GppConfigTable[] = {
0x0, 0x1, 0x2, 0xC, 0xA, 0x4, 0xB
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Core Configuration.
*
@@ -572,7 +572,7 @@ PcieLibSetCoreConfiguration (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibSetCoreConfiguration Exit\n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Core Configuration
* Function return GPPSB/GFX/GFX2 core configuration.
@@ -612,7 +612,7 @@ PcieLibGetCoreConfiguration (
return CoreConfiguration;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return link misc information (max link width, current link width, lane 0 map)
*
@@ -646,7 +646,7 @@ PcieLibGetPortLinkInfo (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if port in lane reversed configuration.
*
@@ -677,7 +677,7 @@ PcieLibIsPortReversed (
return Result;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if core id valid for current silicon
*
@@ -713,7 +713,7 @@ PcieLibIsValidCoreId (
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if port Id valid for current core configuration
*
@@ -753,7 +753,7 @@ PcieLibIsValidPortId (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Link mode. Gen1/Gen2/Gen2-Advertize
*
@@ -815,7 +815,7 @@ PcieLibSetLinkMode (
LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2 , AccessWidth32, (UINT32)~(BIT13), RegA2Value , pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Request PCIE reset to be executed
*
@@ -847,7 +847,7 @@ PcieLibRequestPciReset (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Control Core Reset
*
@@ -917,7 +917,7 @@ UINT8 GfxLineMapTable[] = {
UINT8 GppLineMapTable[] = {
0x00, 0x01, 0x03, 0x0F
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Power off port lanes.
*
@@ -965,7 +965,7 @@ PcieLibPowerOffPortLanes (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibPowerOffPortLanes Exit\n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Hide Unused Ports
*
@@ -1019,7 +1019,7 @@ PcieLibHidePorts (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibHidePorts Exit\n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* UnHide all PCIE Ports
*
@@ -1055,7 +1055,7 @@ PCIE_DEFAULT_CONFIG PcieDefaultConfig = {
60,
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for all NB.
*
@@ -1075,7 +1075,7 @@ AmdPcieInitializer (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize default PCIE_CONFIG setting
*
@@ -1129,7 +1129,7 @@ PcieLibInitializer (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Validate Gfx Core Configuration
*
@@ -1166,7 +1166,7 @@ PcieLibValidateGfxConfig (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " CoreConfiguration[%d] = %x\n", CoreId, pPcieConfig->CoreConfiguration[CoreId]));
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Validate input parameters for early PCIE init.
*
@@ -1243,7 +1243,7 @@ PcieLibInitValidateInput (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Enable PCIE Extended configuration MMIO.
*
@@ -1274,7 +1274,7 @@ PcieLibSetPcieMmioBase (
LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG04, AccessWidth8, (UINT32)~BIT1, BIT1, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Assert/Deassert Strap valid enables programming for misc strap features.
*
@@ -1306,7 +1306,7 @@ PcieLibStrapModeControl (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Pcie Port Info.
*
@@ -1360,7 +1360,7 @@ PcieLibGetPortInfo (
return (PORT_INFO*)FIX_PTR_ADDR (pPortInfo, NULL);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Pointer to static port info
*
@@ -1381,7 +1381,7 @@ PcieLibGetStaticPortInfo (
return pPortStaticInfo ;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Native Port Id.
* Native Port Id can be different from Port ID only on GPPSB core ports.
@@ -1410,7 +1410,7 @@ PcieLibNativePortId (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get pointer to Core info structure.
*
@@ -1429,7 +1429,7 @@ PcieLibGetCoreInfo (
return (CORE_INFO*)FIX_PTR_ADDR (&CoreInfoTable[CoreId], NULL);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Reset Device in slot.
* Check if slot has controlled by GPI reset. If support toggle reset for 10us.
@@ -1456,7 +1456,7 @@ PcieLibResetSlot (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Secondary level interface to check if Gen2 disabled.
*
@@ -1481,7 +1481,7 @@ PcieLibCheckGen2Disabled (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Request Gen 2 disabled on next boot.
*
@@ -1504,7 +1504,7 @@ PcieLibSetGen2Disabled (
LibNbPciIndexWrite (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Force link to compliance mode
*
@@ -1531,7 +1531,7 @@ PcieLibSetLinkCompliance (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCIe device type
*
@@ -1542,7 +1542,7 @@ PcieLibSetLinkCompliance (
*
* @retval PCIe device type (see PCIE_DEVICE_TYPE)
*/
- /*----------------------------------------------------------------------------------------*/
+
PCIE_DEVICE_TYPE
PcieGetDeviceType (
@@ -1561,7 +1561,7 @@ PcieGetDeviceType (
return PcieNotPcieDevice;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get bitmap of cores that have active or potentially active ports
*
@@ -1571,7 +1571,7 @@ PcieGetDeviceType (
*
* @retval Bitmap of cores
*/
- /*----------------------------------------------------------------------------------------*/
+
UINT8
PcieLibGetActiveCoreMap (
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c
index 62e6719..ddf5a78 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c
@@ -61,7 +61,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Set Pcie Link Width
*
@@ -122,7 +122,7 @@ PcieLibSetLinkWidth (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Return link with
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
index 7bbdc51..50a9d25 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
@@ -71,7 +71,7 @@ PciePllOffCheckFunction (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if EP allowed exit latency allowed PLL in L1 to be disabled on non hotplug ports.
*
@@ -121,7 +121,7 @@ PciePllOffComatibilityTest (
return Result;
}
-/**----------------------------------------------------------------------------------------*/
+
/**
* Scan PCIe topology
*
@@ -132,7 +132,7 @@ PciePllOffComatibilityTest (
*
* @retval SCAN_FINISHED Scan for device finished.
*/
- /*----------------------------------------------------------------------------------------*/
+
SCAN_STATUS
PciePllOffCheckFunction (
IN PCI_SCAN_PROTOCOL *This,
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
index 20d2244d..ffa3496 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
@@ -70,7 +70,7 @@ PciePortRemapAllocateDeviceId (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Remap PCIe ports device number.
*
@@ -152,7 +152,7 @@ PciePortRemapInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate Device number from unused port array.
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c b/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c
index 852a13d..ba4ed37 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c
@@ -119,7 +119,7 @@ PcieRecoveryNativePortId (
IN OUT AMD_NB_CONFIG *NbConfigPtr
);
-/*----------------------------------------------------------------------------------------*/
+
/**
* PCIE Recovery Init. Basic programming / EP training.
* After this call EP are fully operational.
@@ -212,7 +212,7 @@ PcieRecoveryMiscInitTable[] = {
// 2 3 4 5 6 7 8 9 A B C D
UINT8 PortToCoreMappingTable[] = { 0xff, 0xff, 0, 0, 3, 3, 3, 3, 4, 3, 3, 1, 1, 3 };
-/*----------------------------------------------------------------------------------------*/
+
/**
* Minimum core initialization
*
@@ -256,7 +256,7 @@ PcieRecoveryCoreInit (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Port link training initialization
*
@@ -316,7 +316,7 @@ PcieRecoveryPortTraining (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check link training Status
*
@@ -377,7 +377,7 @@ UINT8 PortTrainingOffset[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check link training Status
*
@@ -467,7 +467,7 @@ INDIRECT_REG_ENTRY PcieRecoveryPortInitTable[] = {
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Port basic register init
*
@@ -535,7 +535,7 @@ INDIRECT_REG_ENTRY PcieRecoveryCoreInitTable[] = {
(4 << 6) + (4 << 1) + 1
}
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Core basic register init
*
@@ -620,7 +620,7 @@ PcieRecoveryCommonCoreInit (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieRecoveryCommonCoreInit Exitr\n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Core register selector.
* Function return selector to access BIFNB register space for selected core
@@ -660,7 +660,7 @@ PcieRecoveryGetCoreAddress (
return CoreAddress;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get PCI address of Port.
* Function return pcie Address based on port mapping and core configuration.
@@ -691,7 +691,7 @@ UINT32 GppNativeIdTable[] = {
0xf9807654
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Native Port Id.
* Native Port Id can be different from Port ID only on GPPSB core ports.
@@ -716,7 +716,7 @@ PcieRecoveryNativePortId (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize default PCIE_CONFIG setting
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieSb.c b/src/vendorcode/amd/cimx/rd890/nbPcieSb.c
index c96b7b9..6b580b6 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieSb.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieSb.c
@@ -66,7 +66,7 @@
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/*
* Set up NB-SB virtual channel for audio traffic
*
@@ -76,7 +76,7 @@
*
*/
-/*----------------------------------------------------------------------------------------*/
+
/*
* Set up NB-SB virtual channel for audio traffic
*
@@ -105,7 +105,7 @@ PcieSbSetupVc (
LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffffff, BIT31, pConfig);
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Set up NB-SB virtual channel for audio traffic
*
@@ -129,7 +129,7 @@ PcieSbEnableVc (
LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffffff, BIT3, pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Init SB ASPM.
* Enable ASPM states on SB
@@ -138,7 +138,7 @@ PcieSbEnableVc (
* @param[in] Lx Lx ASPM bitmap. Lx[0] - L0s enable. Lx[1] - L1 enable.
* @param[in] pConfig Northbridge configuration structure pointer.
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieSbInitAspm (
IN UINT8 Lx,
@@ -161,13 +161,13 @@ PcieSbInitAspm (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Get Alink config address
*
*
*/
-/*----------------------------------------------------------------------------------------*/
+
AGESA_STATUS
PcieSbAgetAlinkIoAddress (
OUT UINT16 *AlinkPort,
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c
index 234291e..5687b49 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c
@@ -93,7 +93,7 @@ PcieIsDeskewCardDetected (
*----------------------------------------------------------------------------------------
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc GFX Card Workaround
* RV3780/RV380 desk workaround. NV43 lost SSID workaround.
@@ -157,7 +157,7 @@ PcieGfxWorkarounds (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RV370/RV380 Deskew workaround
*
@@ -200,7 +200,7 @@ PcieDeskewWorkaround (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NV43 card workaround (lost SSID)
*
@@ -239,7 +239,7 @@ PcieNvWorkaround (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Allocate temporary resources for Pcie P2P bridge
*
@@ -274,7 +274,7 @@ PcieConfigureBridgeResources (
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Free temporary resources for Pcie P2P bridge
*
@@ -299,7 +299,7 @@ PcieFreeBridgeResources (
}
-/*----------------------------------------------------------------------------------------*/
+
/*
* Check if card required test for deskew workaround
*
@@ -322,7 +322,7 @@ PcieIsDeskewCardDetected (
return FALSE;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Check if we can accsee to EP. Wait for up to 1 sec if EP requred extra time to initialize.
*
@@ -330,7 +330,7 @@ PcieIsDeskewCardDetected (
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
PcieEpReadyWorkaround (
IN AMD_NB_CONFIG *pConfig
@@ -391,7 +391,7 @@ UINT16 AspmBrDeviceTable[] = {
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Misc PCIe ASPM workarounds
*
@@ -399,7 +399,7 @@ UINT16 AspmBrDeviceTable[] = {
* @param[in] pConfig Northbridge configuration structure pointer.
*
*/
-/*----------------------------------------------------------------------------------------*/
+
VOID
PcieAspmWorkarounds (
IN OUT ASPM_LINK_INFO *AspmLinkInfoPtr,
diff --git a/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c b/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c
index df61f29..09f754b 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c
@@ -279,7 +279,7 @@ CONST INDIRECT_REG_ENTRY NbPorHtiuTable[] = {
{NB_HTIU_REG2A, 0xfffffffc, 0x00000001 }
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Amd Power on Reset Initialization for all NB.
*
@@ -303,7 +303,7 @@ AmdPowerOnResetInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* NB Power on Reset Initialization.
* Basic registers initialization.
@@ -359,7 +359,7 @@ NbPowerOnResetInit (
return Status;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Validate input parameters
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecovery.c b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
index 6d8d7c5..df11eca 100644
--- a/src/vendorcode/amd/cimx/rd890/nbRecovery.c
+++ b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
@@ -119,7 +119,7 @@ INDIRECT_REG_ENTRY NbRecoveryPorHtiuTable[] = {
{NB_HTIU_REG2A, 0xfffffffc, 0x00000001 }
};
-/*----------------------------------------------------------------------------------------*/
+
/**
* Northbridge Power on Reset Initialization for all NB in system.
*
@@ -168,7 +168,7 @@ AmdPowerOnResetInit (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Initialize misc setting
*
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c b/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c
index e8a145d..e1e7374 100644
--- a/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c
+++ b/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c
@@ -62,7 +62,7 @@
*/
-/*----------------------------------------------------------------------------------------*/
+
/**
* AMD structures initializer for recovery.
*
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
index a5d92ad..bf88e75 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
@@ -46,7 +46,7 @@
#include "SBPLATFORM.h"
#include "cbtypes.h"
-/*----------------------------------------------------------------------------------------*/
+
/**
* SbStall - Delay routine
*
@@ -87,7 +87,7 @@ SbStall (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* SbReset - Generate a reset command
*
@@ -106,7 +106,7 @@ SbReset (
RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* outPort80 - Send data to PORT 80 (debug port)
*
diff --git a/src/vendorcode/amd/cimx/sb800/ECLIB.c b/src/vendorcode/amd/cimx/sb800/ECLIB.c
index 54d87e7..3a571d5 100644
--- a/src/vendorcode/amd/cimx/sb800/ECLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/ECLIB.c
@@ -41,7 +41,7 @@
// #ifndef NO_EC_SUPPORT
-/*----------------------------------------------------------------------------------------*/
+
/**
* EnterEcConfig - Force EC into Config mode
*
@@ -60,7 +60,7 @@ EnterEcConfig (
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ExitEcConfig - Force EC exit Config mode
*
@@ -79,7 +79,7 @@ ExitEcConfig (
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ReadEC8 - Read EC register data
*
@@ -103,7 +103,7 @@ ReadEC8 (
ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* WriteEC8 - Write date into EC register
*
@@ -128,7 +128,7 @@ WriteEC8 (
WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWEC8 - Read/Write EC register
*
diff --git a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c b/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
index 82864e6..66341ae 100644
--- a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
+++ b/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
@@ -40,7 +40,7 @@
#include "cbtypes.h"
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO2
*
@@ -71,7 +71,7 @@ ReadPMIO2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO 2
*
@@ -102,7 +102,7 @@ WritePMIO2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWPMIO2 - Read/Write PMIO2
*
diff --git a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c b/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
index 6cce4f1..de42110 100644
--- a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
@@ -39,7 +39,7 @@
#include "SBPLATFORM.h"
#include "cbtypes.h"
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -70,7 +70,7 @@ ReadPMIO (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO
*
@@ -101,7 +101,7 @@ WritePMIO (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWPMIO - Read/Write PMIO
*
diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
index eb21770..26a1c56 100644
--- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
@@ -48,7 +48,7 @@
#ifndef B1_IMAGE
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
@@ -116,7 +116,7 @@ sbMidPostInit (
sataInitMidPost (pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
@@ -144,7 +144,7 @@ sbLatePost (
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
@@ -170,7 +170,7 @@ sbBeforePciRestoreInit (
abSpecialSetBeforePciEnum (pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
@@ -204,7 +204,7 @@ sbAfterPciRestoreInit (
#endif
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
@@ -230,7 +230,7 @@ sbSmmAcpiOn (
#endif
-/*----------------------------------------------------------------------------------------*/
+
/**
* Call Back routine.
*
diff --git a/src/vendorcode/amd/cimx/sb800/SBPELIB.c b/src/vendorcode/amd/cimx/sb800/SBPELIB.c
index 403f21f..79cf69e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPELIB.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPELIB.c
@@ -63,7 +63,7 @@ getRevisionID (
return dbVar0;
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
@@ -103,7 +103,7 @@ programPciByteTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
@@ -149,7 +149,7 @@ getChipSysMode (
ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Southbridge CIMx configuration structure pointer
*
diff --git a/src/vendorcode/amd/cimx/sb900/EcLib.c b/src/vendorcode/amd/cimx/sb900/EcLib.c
index 44e196b..b26d32f 100644
--- a/src/vendorcode/amd/cimx/sb900/EcLib.c
+++ b/src/vendorcode/amd/cimx/sb900/EcLib.c
@@ -38,7 +38,7 @@
// #ifndef NO_EC_SUPPORT
-/*----------------------------------------------------------------------------------------*/
+
/**
* EnterEcConfig - Force EC into Config mode
*
@@ -57,7 +57,7 @@ EnterEcConfig (
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ExitEcConfig - Force EC exit Config mode
*
@@ -76,7 +76,7 @@ ExitEcConfig (
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* ReadEC8 - Read EC register data
*
@@ -100,7 +100,7 @@ ReadEC8 (
ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* WriteEC8 - Write date into EC register
*
@@ -125,7 +125,7 @@ WriteEC8 (
WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWEC8 - Read/Write EC register
*
diff --git a/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c b/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
index 1c8f8fd..3d81c71 100644
--- a/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
+++ b/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
@@ -37,7 +37,7 @@
#include "cbtypes.h"
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO2
*
@@ -68,7 +68,7 @@ ReadPMIO2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO 2
*
@@ -99,7 +99,7 @@ WritePMIO2 (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWPMIO2 - Read/Write PMIO2
*
diff --git a/src/vendorcode/amd/cimx/sb900/PmioLib.c b/src/vendorcode/amd/cimx/sb900/PmioLib.c
index fdd15a3..57a8441 100644
--- a/src/vendorcode/amd/cimx/sb900/PmioLib.c
+++ b/src/vendorcode/amd/cimx/sb900/PmioLib.c
@@ -36,7 +36,7 @@
#include "SbPlatform.h"
#include "cbtypes.h"
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read PMIO
*
@@ -67,7 +67,7 @@ ReadPMIO (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Write PMIO
*
@@ -98,7 +98,7 @@ WritePMIO (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* RWPMIO - Read/Write PMIO
*
diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c
index 958e44b..6cae23c 100644
--- a/src/vendorcode/amd/cimx/sb900/SbMain.c
+++ b/src/vendorcode/amd/cimx/sb900/SbMain.c
@@ -46,7 +46,7 @@
#ifndef B1_IMAGE
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
@@ -124,7 +124,7 @@ sbMidPostInit (
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
@@ -157,7 +157,7 @@ sbLatePost (
StressResetModeLate (pConfig); //
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
@@ -187,7 +187,7 @@ sbBeforePciRestoreInit (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
@@ -221,7 +221,7 @@ sbAfterPciRestoreInit (
hwmImcInit (pConfig);
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
@@ -265,7 +265,7 @@ sbSmmAcpiOn (
#endif
-/*----------------------------------------------------------------------------------------*/
+
/**
* Call Back routine.
*
diff --git a/src/vendorcode/amd/cimx/sb900/SbPeLib.c b/src/vendorcode/amd/cimx/sb900/SbPeLib.c
index ee6eba9..e01c877 100644
--- a/src/vendorcode/amd/cimx/sb900/SbPeLib.c
+++ b/src/vendorcode/amd/cimx/sb900/SbPeLib.c
@@ -173,7 +173,7 @@ MemoryCopy (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
@@ -214,7 +214,7 @@ programPciByteTable (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
@@ -281,7 +281,7 @@ isImcEnabled (
}
}
-/*----------------------------------------------------------------------------------------*/
+
/**
* Read Southbridge CIMx configuration structure pointer
*
diff --git a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
index 5e85f6b..408e158 100644
--- a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
+++ b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
@@ -498,7 +498,7 @@ LibAmdFinit(
/* TODO: finit */
__asm__ volatile ("finit");
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read IO port
*
@@ -536,7 +536,7 @@ LibAmdIoRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write IO port
*
@@ -574,7 +574,7 @@ LibAmdIoWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* IO read modify write
*
@@ -604,7 +604,7 @@ LibAmdIoRMW (
LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll IO register
*
@@ -637,7 +637,7 @@ LibAmdIoPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read memory/MMIO
*
@@ -675,7 +675,7 @@ LibAmdMemRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write memory/MMIO
*
@@ -713,7 +713,7 @@ LibAmdMemWrite (
break;
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Memory/MMIO read modify write
*
@@ -743,7 +743,7 @@ LibAmdMemRMW (
LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll Mmio
*
@@ -776,7 +776,7 @@ LibAmdMemPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read PCI config space
*
@@ -827,7 +827,7 @@ LibAmdPciRead (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write PCI config space
*
@@ -882,7 +882,7 @@ LibAmdPciWrite (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* PCI read modify write
*
@@ -912,7 +912,7 @@ LibAmdPciRMW (
LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Poll PCI config space register
*
@@ -945,7 +945,7 @@ LibAmdPciPoll (
} while (TempData != (Value & TempMask));
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Get MMIO base address for PCI accesses
*
@@ -980,7 +980,7 @@ GetPciMmioAddress (
return MmioIsEnabled;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Read field of PCI config register.
*
@@ -1013,7 +1013,7 @@ LibAmdPciReadBits (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Write field of PCI config register.
*
@@ -1053,7 +1053,7 @@ LibAmdPciWriteBits (
LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate next capability pointer
*
@@ -1127,7 +1127,7 @@ LibAmdPciFindNextCap (
return;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Set memory with value
*
@@ -1153,7 +1153,7 @@ LibAmdMemFill (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Copy memory
*
@@ -1181,7 +1181,7 @@ LibAmdMemCopy (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Verify checksum of binary image (B1/B2/B3)
*
@@ -1217,7 +1217,7 @@ LibAmdVerifyImageChecksum (
return (Sum == 0)?TRUE:FALSE;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Locate AMD binary image that contain specific module
*
@@ -1264,7 +1264,7 @@ LibAmdLocateImage (
return NULL;
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1286,7 +1286,7 @@ LibAmdGetPackageType (
return (UINT32) (1 << ProcessorPackageType);
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
@@ -1330,7 +1330,7 @@ LibAmdGetDataFromPtr (
}
}
-/*---------------------------------------------------------------------------------------*/
+
/**
* Returns the package type mask for the processor
*
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