[coreboot-gerrit] New patch to review for coreboot: 14ab3d5 google/jecht: add new mainboard
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Jun 5 18:55:15 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10432
-gerrit
commit 14ab3d5ce86b68e55998c96c27a25a5766f2f524
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Fri Jun 5 18:53:43 2015 +0200
google/jecht: add new mainboard
Taken from CrOS, including everything up to commit da4c33913.
Adapted to upstream.
Change-Id: I095e6726a220200ba17719fc05fcdc521da484e8
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
src/mainboard/google/jecht/Kconfig | 50 +++
src/mainboard/google/jecht/Kconfig.name | 2 +
src/mainboard/google/jecht/Makefile.inc | 28 ++
src/mainboard/google/jecht/acpi/chromeos.asl | 23 ++
src/mainboard/google/jecht/acpi/ec.asl | 0
.../google/jecht/acpi/haswell_pci_irqs.asl | 86 ++++++
src/mainboard/google/jecht/acpi/mainboard.asl | 81 +++++
src/mainboard/google/jecht/acpi/platform.asl | 75 +++++
src/mainboard/google/jecht/acpi/superio.asl | 35 +++
src/mainboard/google/jecht/acpi/thermal.asl | 343 +++++++++++++++++++++
src/mainboard/google/jecht/acpi_tables.c | 62 ++++
src/mainboard/google/jecht/chromeos.c | 118 +++++++
src/mainboard/google/jecht/cmos.layout | 139 +++++++++
src/mainboard/google/jecht/devicetree.cb | 122 ++++++++
src/mainboard/google/jecht/dsdt.asl | 62 ++++
src/mainboard/google/jecht/fadt.c | 158 ++++++++++
src/mainboard/google/jecht/gpio.h | 124 ++++++++
src/mainboard/google/jecht/hda_verb.h | 112 +++++++
src/mainboard/google/jecht/lan.c | 195 ++++++++++++
src/mainboard/google/jecht/mainboard.c | 169 ++++++++++
src/mainboard/google/jecht/onboard.h | 40 +++
src/mainboard/google/jecht/pei_data.c | 63 ++++
src/mainboard/google/jecht/romstage.c | 63 ++++
src/mainboard/google/jecht/smihandler.c | 79 +++++
src/mainboard/google/jecht/spd/Makefile.inc | 20 ++
src/mainboard/google/jecht/spd/spd.c | 41 +++
src/mainboard/google/jecht/spd/spd.h | 26 ++
src/mainboard/google/jecht/thermal.h | 59 ++++
28 files changed, 2375 insertions(+)
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
new file mode 100644
index 0000000..fbf61de
--- /dev/null
+++ b/src/mainboard/google/jecht/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_GOOGLE_JECHT
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_INTEL_BROADWELL
+ select BOARD_ROMSIZE_KB_8192
+ select SUPERIO_ITE_IT8772F
+ select VIRTUAL_DEV_SWITCH
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MMCONF_SUPPORT
+ select HAVE_SMI_HANDLER
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+ select EXTERNAL_MRC_BLOB
+ select CHROMEOS_RAMOOPS_DYNAMIC
+ select INTEL_INT15
+ select CHROMEOS_VBNV_CMOS
+ select PHYSICAL_REC_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/jecht
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Jecht"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/google/jecht/Kconfig.name b/src/mainboard/google/jecht/Kconfig.name
new file mode 100644
index 0000000..235ac06
--- /dev/null
+++ b/src/mainboard/google/jecht/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_JECHT
+ bool "Jecht"
diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc
new file mode 100644
index 0000000..cc80453
--- /dev/null
+++ b/src/mainboard/google/jecht/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+subdirs-y += spd
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += lan.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
diff --git a/src/mainboard/google/jecht/acpi/chromeos.asl b/src/mainboard/google/jecht/acpi/chromeos.asl
new file mode 100644
index 0000000..5928678
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/chromeos.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Name(OIPG, Package() {
+ Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
+ Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
+})
diff --git a/src/mainboard/google/jecht/acpi/ec.asl b/src/mainboard/google/jecht/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl b/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl
new file mode 100644
index 0000000..28a7ada
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // Mini-HD Audio 0:3.0
+ Package() { 0x0003ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // EHCI 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // XHCI 0:14.0
+ Package() { 0x0014ffff, 0, 0, 18 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 22 },
+ Package() { 0x001fffff, 1, 0, 18 },
+ Package() { 0x001fffff, 2, 0, 17 },
+ Package() { 0x001fffff, 3, 0, 16 },
+ // Serial IO 0:15.0
+ Package() { 0x0015ffff, 0, 0, 20 },
+ Package() { 0x0015ffff, 1, 0, 21 },
+ Package() { 0x0015ffff, 2, 0, 21 },
+ Package() { 0x0015ffff, 3, 0, 21 },
+ // SDIO 0:17.0
+ Package() { 0x0017ffff, 0, 0, 23 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Mini-HD Audio 0:3.0
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // XHCI 0:14.0
+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Serial IO 0:15.0
+ Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
+ // SDIO 0:17.0
+ Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl
new file mode 100644
index 0000000..236f881
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/mainboard.asl
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mainboard/google/jecht/onboard.h>
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+ }
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/*
+ * LAN connected to Root Port 3, becomes Root Port 1 after coalesce
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { JECHT_NIC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (JECHT_NIC_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+ }
+}
+
+/*
+ * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
+ */
+Scope (\_SB.PCI0.RP02)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { JECHT_WLAN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (JECHT_WLAN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/jecht/acpi/platform.asl b/src/mainboard/google/jecht/acpi/platform.asl
new file mode 100644
index 0000000..145fd2f
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/platform.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Initialize thermal defaults */
+ \_TZ.THRM._INI ()
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl
new file mode 100644
index 0000000..1f83630
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/superio.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
+
+#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
+#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
+#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
+#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
+
+#include "superio/ite/it8772f/acpi/superio.asl"
diff --git a/src/mainboard/google/jecht/acpi/thermal.asl b/src/mainboard/google/jecht/acpi/thermal.asl
new file mode 100644
index 0000000..74211ed
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi/thermal.asl
@@ -0,0 +1,343 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include "../thermal.h"
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ // Start fan at state 4 = lowest temp state
+ Method (_INI)
+ {
+ Store (4, \FLVL)
+ Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+
+ Method (TCHK, 0, Serialized)
+ {
+ // Get CPU Temperature from PECI via SuperIO TMPIN3
+ Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+ // Check for "no reading available
+ If (LEqual (Local0, 0x80)) {
+ Return (CTOK (FAN0_THRESHOLD_ON))
+ }
+
+ // Check for invalid readings
+ If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+ Return (CTOK (FAN0_THRESHOLD_ON))
+ }
+
+ // PECI raw value is an offset from Tj_max
+ Subtract (255, Local0, Local1)
+
+ // Handle values greater than Tj_max
+ If (LGreaterEqual (Local1, \TMAX)) {
+ Return (CTOK (\TMAX))
+ }
+
+ // Subtract from Tj_max to get temperature
+ Subtract (\TMAX, Local1, Local0)
+ Return (CTOK (Local0))
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get temperature from SuperIO in deci-kelvin
+ Store (TCHK (), Local0)
+
+ // Critical temperature in deci-kelvin
+ Store (CTOK (\TMAX), Local1)
+
+ If (LGreaterEqual (Local0, Local1)) {
+ Store ("CRITICAL TEMPERATURE", Debug)
+ Store (Local0, Debug)
+
+ // Wait 1 second for SuperIO to re-poll
+ Sleep (1000)
+
+ // Re-read temperature from SuperIO
+ Store (TCHK (), Local0)
+
+ Store ("RE-READ TEMPERATURE", Debug)
+ Store (Local0, Debug)
+ }
+
+ Return (Local0)
+ }
+
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (FAN0_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN0_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (FAN1_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN1_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC2) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (CTOK (FAN2_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN2_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC3) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (CTOK (FAN3_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN3_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC4) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (CTOK (FAN4_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN4_THRESHOLD_ON))
+ }
+ }
+
+ Name (_AL0, Package () { FAN0 })
+ Name (_AL1, Package () { FAN1 })
+ Name (_AL2, Package () { FAN2 })
+ Name (_AL3, Package () { FAN3 })
+ Name (_AL4, Package () { FAN4 })
+
+ PowerResource (FNP0, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ If (LNot (_STA ())) {
+ Store (0, \FLVL)
+ Store (FAN0_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ Method (_OFF) {
+ If (_STA ()) {
+ Store (1, \FLVL)
+ Store (FAN1_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ }
+
+ PowerResource (FNP1, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ If (LNot (_STA ())) {
+ Store (1, \FLVL)
+ Store (FAN1_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ Method (_OFF) {
+ If (_STA ()) {
+ Store (2, \FLVL)
+ Store (FAN2_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ }
+
+ PowerResource (FNP2, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ If (LNot (_STA ())) {
+ Store (2, \FLVL)
+ Store (FAN2_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ Method (_OFF) {
+ If (_STA ()) {
+ Store (3, \FLVL)
+ Store (FAN3_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ }
+
+ PowerResource (FNP3, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ If (LNot (_STA ())) {
+ Store (3, \FLVL)
+ Store (FAN3_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ Method (_OFF) {
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (FAN4_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ }
+
+ PowerResource (FNP4, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ If (LNot (_STA ())) {
+ Store (4, \FLVL)
+ Store (FAN4_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ Method (_OFF) {
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (FAN4_PWM,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+ }
+
+ Device (FAN0)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 0)
+ Name (_PR0, Package () { FNP0 })
+ }
+
+ Device (FAN1)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 1)
+ Name (_PR0, Package () { FNP1 })
+ }
+
+ Device (FAN2)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 2)
+ Name (_PR0, Package () { FNP2 })
+ }
+
+ Device (FAN3)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 3)
+ Name (_PR0, Package () { FNP3 })
+ }
+
+ Device (FAN4)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 4)
+ Name (_PR0, Package () { FNP4 })
+ }
+ }
+}
diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c
new file mode 100644
index 0000000..4158d2b
--- /dev/null
+++ b/src/mainboard/google/jecht/acpi_tables.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include "thermal.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+
+ gnvs->tmps = TEMPERATURE_SENSOR_ID;
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
new file mode 100644
index 0000000..415db05
--- /dev/null
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <string.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/sata.h>
+
+#define GPIO_SPI_WP 58
+#define GPIO_REC_MODE 12
+
+#define FLAG_SPI_WP 0
+#define FLAG_REC_MODE 1
+#define FLAG_DEV_MODE 2
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+
+static void fill_lb_gpio(struct lb_gpio *gpio, int num,
+ int polarity, const char *name, int force)
+{
+ memset(gpio, 0, sizeof(*gpio));
+ gpio->port = num;
+ gpio->polarity = polarity;
+ if (force >= 0)
+ gpio->value = force;
+ else if (num >= 0)
+ gpio->value = get_gpio(num);
+ strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio *gpio;
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ gpio = gpios->gpios;
+ fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0);
+ fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery",
+ get_recovery_mode_switch());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
+ get_developer_mode_switch());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded);
+}
+#endif
+
+int get_write_protect_state(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 2);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+ return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 2);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+ return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+}
+
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void)
+{
+ u32 flags = 0;
+
+ /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+ if (get_gpio(GPIO_SPI_WP))
+ flags |= (1 << FLAG_SPI_WP);
+
+ /* Recovery: GPIO12 = RECOVERY_L, active low */
+ if (!get_gpio(GPIO_REC_MODE))
+ flags |= (1 << FLAG_REC_MODE);
+
+ /* Developer: Virtual */
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
+}
+#endif
diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout
new file mode 100644
index 0000000..418089b
--- /dev/null
+++ b/src/mainboard/google/jecht/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
new file mode 100644
index 0000000..4d16ed6
--- /dev/null
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -0,0 +1,122 @@
+chip soc/intel/broadwell
+
+ # Disable eDP Hotplug
+ register "gpu_dp_d_hotplug" = "0x00"
+
+ # Enable DisplayPort C Hotplug with 6ms pulse
+ register "gpu_dp_c_hotplug" = "0x06"
+
+ # Enable HDMI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+
+
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # SuperIO range is 0x700-0x73f
+ register "gen2_dec" = "0x003c0701"
+
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpe0_en_1" = "0x00000000"
+ register "gpe0_en_2" = "0x00000000"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
+
+ register "sio_acpi_mode" = "0"
+ register "sio_i2c0_voltage" = "0" # 3.3V
+ register "sio_i2c1_voltage" = "0" # 3.3V
+
+ # Force enable ASPM for PCIe Port 4
+ register "pcie_port_force_aspm" = "0x10"
+
+ # Enable port coalescing
+ register "pcie_port_coalesce" = "1"
+
+ # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x01220000"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip superio/ite/it8772f
+ # Skip keyboard init
+ register "skip_keyboard" = "1"
+ # Enable PECI on TMPIN3
+ register "peci_tmpin" = "3"
+ # Enable FAN2
+ register "fan2_enable" = "1"
+
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x700
+ io 0x62 = 0x710
+ irq 0x70 = 0x09
+ irq 0xf2 = 0x20
+ irq 0xf4 = 0x0
+ irq 0xfa = 0x12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x720
+ io 0x62 = 0x730
+ end
+ device pnp 2e.5 off
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end # Keyboard
+ device pnp 2e.6 off
+ irq 0x70 = 12
+ end # Mouse
+ device pnp 2e.a off end # IR
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 on end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
new file mode 100644
index 0000000..e219538
--- /dev/null
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <soc/intel/broadwell/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // CPU
+ #include <soc/intel/broadwell/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/broadwell/acpi/systemagent.asl>
+ #include <soc/intel/broadwell/acpi/pch.asl>
+ }
+ }
+
+ // Thermal handler
+ #include "acpi/thermal.asl"
+
+ // Chrome OS specific
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chipset specific sleep states
+ #include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c
new file mode 100644
index 0000000..aeb7fd6
--- /dev/null
+++ b/src/mainboard/google/jecht/fadt.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <soc/acpi.h>
+#include <cpu/x86/smm.h>
+#include <soc/pch.h>
+#include <soc/iomap.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = ACPI_BASE_ADDRESS;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x80;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 32;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 0;
+ fadt->x_gpe0_blk.bit_width = 0;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = 0;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/jecht/gpio.h b/src/mainboard/google/jecht/gpio.h
new file mode 100644
index 0000000..0a1e987
--- /dev/null
+++ b/src/mainboard/google/jecht/gpio.h
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef JECHT_GPIO_H
+#define JECHT_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */
+ PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: SMBALERT */
+ PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */
+ PCH_GPIO_UNUSED, /* 13: UNUSED */
+ PCH_GPIO_UNUSED, /* 14: UNUSED */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */
+ PCH_GPIO_UNUSED, /* 18: UNUSED */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */
+ PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */
+ PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */
+ PCH_GPIO_UNUSED, /* 25: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */
+ PCH_GPIO_UNUSED, /* 44: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */
+ PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */
+ PCH_GPIO_UNUSED, /* 51: UNUSED */
+ PCH_GPIO_UNUSED, /* 52: UNUSED */
+ PCH_GPIO_UNUSED, /* 53: UNUSED */
+ PCH_GPIO_UNUSED, /* 54: UNUSED */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */
+ PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_UNUSED, /* 72: UNUSED */
+ PCH_GPIO_UNUSED, /* 73: UNUSED */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/jecht/hda_verb.h b/src/mainboard/google/jecht/hda_verb.h
new file mode 100644
index 0000000..bc7cf1d
--- /dev/null
+++ b/src/mainboard/google/jecht/hda_verb.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
+ 0x10ec0283, // Subsystem ID
+ 0x0000000c, // Number of jacks (NID entries)
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
+ 0x00172083,
+ 0x00172102,
+ 0x001722ec,
+ 0x00172310,
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC */
+ 0x01271cf0,
+ 0x01271d11,
+ 0x01271e11,
+ 0x01271f41,
+
+ /* Pin Complex (NID 0x14) SPKR-OUT PORTD */
+ 0x01471cf0,
+ 0x01471d11,
+ 0x01471e11,
+ 0x01471f40,
+
+ /* Pin Complex (NID 0x17) */
+ 0x01771cf0,
+ 0x01771d11,
+ 0x01771e11,
+ 0x01771f41,
+
+ /* Pin Complex (NID 0x18) MIC1 PORTB */
+ 0x01971c11, // group 1, cap 1
+ 0x01971d10, // black, jack detect
+ 0x01971ea7, // mic in, analog
+ 0x01971f03, // connector, left panel
+
+ /* Pin Complex (NID 0x19) MIC2 PORTF */
+ 0x01871cf0,
+ 0x01871d11,
+ 0x01871e11,
+ 0x01871f41,
+
+ /* Pin Complex (NID 0x1A) LINE1 PORTC */
+ 0x01a71cf0,
+ 0x01a71d11,
+ 0x01a71e11,
+ 0x01a71f41,
+
+ /* Pin Complex (NID 0x1B) LINE2 PORTE */
+ 0x01a71cf0,
+ 0x01a71d11,
+ 0x01a71e11,
+ 0x01a71f41,
+
+ /* Pin Complex (NID 0x1d) PCBeep */
+ 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
+ 0x01d71d81, // mute spkr on hpout
+ 0x01d71e15, // pcbeep en able, checksum
+ 0x01d71f40, // no physical, internal
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT */
+ 0x01e71cf0,
+ 0x01e71d11,
+ 0x01e71e11,
+ 0x01e71f41,
+
+ /* Pin Complex (NID 0x21) HPOUT PORT-I */
+ 0x02171c1f, // group1,
+ 0x02171d10, // black, jack detect
+ 0x02171e21, // HPOut, 1/8 stereo
+ 0x02171f03, // connector, left panel
+
+ /* Undocumented settings from Realtek (needed for beep_gen) */
+ /* Widget node 0x20 */
+ 0x02050010,
+ 0x02040c20,
+ 0x0205001b,
+ 0x0204081b,
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c
new file mode 100644
index 0000000..963322e
--- /dev/null
+++ b/src/mainboard/google/jecht/lan.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <fmap.h>
+#include <types.h>
+#include <string.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "onboard.h"
+
+static unsigned int search(char *p, u8 *a, unsigned int lengthp,
+ unsigned int lengtha)
+{
+ int i, j;
+
+ /* Searching */
+ for (j = 0; j <= lengtha - lengthp; j++) {
+ for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ;
+ if (i >= lengthp)
+ return j;
+ }
+ return lengtha;
+}
+
+static unsigned char get_hex_digit(u8 *offset)
+{
+ unsigned char retval = 0;
+
+ retval = *offset - '0';
+ if (retval > 0x09) {
+ retval = *offset - 'A' + 0x0A;
+ if (retval > 0x0F)
+ retval = *offset - 'a' + 0x0a;
+ }
+ if (retval > 0x0F) {
+ printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
+ *offset, *offset);
+ retval = 0;
+ }
+
+ return retval;
+}
+
+static int get_mac_address(u32 *high_dword, u32 *low_dword,
+ u8 *search_address, u32 search_length)
+{
+ char key[] = "ethernet_mac";
+ unsigned int offset;
+ int i;
+
+ offset = search(key, search_address, sizeof(key) - 1, search_length);
+ if (offset == search_length) {
+ printk(BIOS_DEBUG,
+ "Error: Could not locate '%s' in VPD\n", key);
+ return 0;
+ }
+ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+ offset += sizeof(key); /* move to next character */
+ *high_dword = 0;
+
+ /* Fetch the MAC address and put the octets in the correct order to
+ * be programmed.
+ *
+ * From RTL8105E_Series_EEPROM-Less_App_Note_1.1
+ * If the MAC address is 001122334455h:
+ * Write 33221100h to I/O register offset 0x00 via double word access
+ * Write 00005544h to I/O register offset 0x04 via double word access
+ */
+
+ for (i = 0; i < 4; i++) {
+ *high_dword |= (get_hex_digit(search_address + offset)
+ << (4 + (i * 8)));
+ *high_dword |= (get_hex_digit(search_address + offset + 1)
+ << (i * 8));
+ offset += 3;
+ }
+
+ *low_dword = 0;
+ for (i = 0; i < 2; i++) {
+ *low_dword |= (get_hex_digit(search_address + offset)
+ << (4 + (i * 8)));
+ *low_dword |= (get_hex_digit(search_address + offset + 1)
+ << (i * 8));
+ offset += 3;
+ }
+
+ return *high_dword | *low_dword;
+}
+
+static void program_mac_address(u16 io_base)
+{
+ void *search_address = NULL;
+ size_t search_length = -1;
+
+ /* Default MAC Address of A0:00:BA:D0:0B:AD */
+ u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
+ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
+
+ if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ struct region_device rdev;
+
+ if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
+ search_address = rdev_mmap_full(&rdev);
+
+ if (search_address != NULL)
+ search_length = region_device_sz(&rdev);
+ }
+ } else {
+ search_address = cbfs_boot_map_with_leak("vpd.bin",
+ CBFS_TYPE_RAW,
+ &search_length);
+ }
+
+ if (search_length <= 0)
+ printk(BIOS_ERR, "LAN: VPD not found.\n");
+ else
+ get_mac_address(&high_dword, &low_dword, search_address,
+ search_length);
+
+ if (io_base) {
+ printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
+ printk(BIOS_DEBUG, "Programming MAC Address\n");
+
+ /* Disable register protection */
+ outb(0xc0, io_base + 0x50);
+ outl(high_dword, io_base);
+ outl(low_dword, io_base + 0x04);
+ outb(0x60, io_base + 54);
+ /* Enable register protection again */
+ outb(0x00, io_base + 0x50);
+ }
+}
+
+void lan_init(void)
+{
+ u16 io_base = 0;
+ struct device *ethernet_dev = NULL;
+
+ /* Get NIC's IO base address */
+ ethernet_dev = dev_find_device(JECHT_NIC_VENDOR_ID,
+ JECHT_NIC_DEVICE_ID, 0);
+ if (ethernet_dev != NULL) {
+ io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
+
+ /*
+ * Battery life time - LAN PCIe should enter ASPM L1 to save
+ * power when LAN connection is idle.
+ * enable CLKREQ: LAN pci config space 0x81h=01
+ */
+ pci_write_config8(ethernet_dev, 0x81, 0x01);
+ }
+
+ if (io_base) {
+ /* Program MAC address based on VPD data */
+ program_mac_address(io_base);
+
+ /*
+ * Program NIC LEDS
+ *
+ * RTL8105E Series EEPROM-Less Application Note,
+ * Section 5.6 LED Mode Configuration
+ *
+ * Step1: Write C0h to I/O register 0x50 via byte access to
+ * disable 'register protection'
+ * Step2: Write xx001111b to I/O register 0x52 via byte access
+ * (bit7 is LEDS1 and bit6 is LEDS0)
+ * Step3: Write 0x00 to I/O register 0x50 via byte access to
+ * enable 'register protection'
+ */
+ outb(0xc0, io_base + 0x50); /* Disable protection */
+ outb((JECHT_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
+ outb(0x00, io_base + 0x50); /* Enable register protection */
+ }
+}
diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c
new file mode 100644
index 0000000..8b3363c
--- /dev/null
+++ b/src/mainboard/google/jecht/mainboard.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <smbios.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 0;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+ lan_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h
new file mode 100644
index 0000000..d0f7844
--- /dev/null
+++ b/src/mainboard/google/jecht/onboard.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#ifndef __ACPI__
+void lan_init(void);
+#endif
+
+/* defines for programming the MAC address */
+#define JECHT_NIC_VENDOR_ID 0x10EC
+#define JECHT_NIC_DEVICE_ID 0x8168
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define JECHT_NIC_LED_MODE 0x00
+
+/* NIC wake is GPIO 8 */
+#define JECHT_NIC_WAKE_GPIO 8
+
+/* WLAN wake is GPIO 10 */
+#define JECHT_WLAN_WAKE_GPIO 10
+
+#endif
diff --git a/src/mainboard/google/jecht/pei_data.c b/src/mainboard/google/jecht/pei_data.c
new file mode 100644
index 0000000..46f13de
--- /dev/null
+++ b/src/mainboard/google/jecht/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 0;
+
+ /* P0: VP8 */
+ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
+ USB_PORT_MINI_PCIE);
+ /* P1: Port A, CN22 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+ USB_PORT_INTERNAL);
+ /* P2: Port B, CN23 */
+ pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+ USB_PORT_INTERNAL);
+ /* P3: WLAN */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Port C, CN25 */
+ pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+ USB_PORT_INTERNAL);
+ /* P5: Port D, CN25 */
+ pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+ USB_PORT_INTERNAL);
+ /* P6: Card Reader */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
+ USB_PORT_SKIP);
+
+ /* P1: CN22 */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: CN23 */
+ pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+ /* P3: CN25 */
+ pei_data_usb3_port(pei_data, 2, 1, 2, 0);
+ /* P4: CN25 */
+ pei_data_usb3_port(pei_data, 3, 1, 2, 0);
+}
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
new file mode 100644
index 0000000..756381e
--- /dev/null
+++ b/src/mainboard/google/jecht/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include <mainboard/google/jecht/spd/spd.h>
+#include "gpio.h"
+
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ struct pei_data pei_data;
+
+ post_code(0x32);
+
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
+
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ mainboard_fill_spd_data(&pei_data);
+ rp->pei_data = &pei_data;
+
+ /* Call into the real romstage main with this board's attributes. */
+ romstage_common(rp);
+}
+
+void mainboard_pre_console_init(void)
+{
+ /* Early SuperIO setup */
+ it8772f_ac_resume_southbridge(DUMMY_DEV);
+ ite_kill_watchdog(GPIO_DEV);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c
new file mode 100644
index 0000000..ca8c318
--- /dev/null
+++ b/src/mainboard/google/jecht/smihandler.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+#include <elog.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ return 1;
+}
+
+/* gpi_sts is GPIO 47:32 */
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ /* Disable USB charging if required */
+ switch (slp_typ) {
+ case 3:
+ break;
+ case 5:
+ break;
+ }
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/jecht/spd/Makefile.inc b/src/mainboard/google/jecht/spd/Makefile.inc
new file mode 100644
index 0000000..6531fca
--- /dev/null
+++ b/src/mainboard/google/jecht/spd/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-y += spd.c
diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c
new file mode 100644
index 0000000..37247f5
--- /dev/null
+++ b/src/mainboard/google/jecht/spd/spd.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <mainboard/google/jecht/spd/spd.h>
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[1] = 0x00;
+ pei_data->spd_addresses[2] = 0xa4;
+ pei_data->spd_addresses[3] = 0x00;
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+ // Enable 2x refresh mode
+ pei_data->ddr_refresh_2x = 1;
+ pei_data->dq_pins_interleaved = 1;
+}
diff --git a/src/mainboard/google/jecht/spd/spd.h b/src/mainboard/google/jecht/spd/spd.h
new file mode 100644
index 0000000..ffdd5d8
--- /dev/null
+++ b/src/mainboard/google/jecht/spd/spd.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/jecht/thermal.h b/src/mainboard/google/jecht/thermal.h
new file mode 100644
index 0000000..b5db531
--- /dev/null
+++ b/src/mainboard/google/jecht/thermal.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define TEMPERATURE_SENSOR_ID 0 /* PECI */
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF 0
+#define FAN4_THRESHOLD_ON 0
+#define FAN4_PWM 0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF 50
+#define FAN3_THRESHOLD_ON 55
+#define FAN3_PWM 0x76
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF 59
+#define FAN2_THRESHOLD_ON 65
+#define FAN2_PWM 0x98
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF 68
+#define FAN1_THRESHOLD_ON 75
+#define FAN1_PWM 0xbf
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF 80
+#define FAN0_THRESHOLD_ON 86
+#define FAN0_PWM 0xdc
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 98
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
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