[coreboot-gerrit] Patch set updated for coreboot: f0dd1b7 mips: implement arch_segment_loaded callback

[Ionela Voinescu (ionela.voinescu@imgtec.com)]

Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10456

-gerrit

commit f0dd1b742a7753b49f0d1b7a58821c6d97e47e88
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Wed May 20 17:03:23 2015 +0100

    mips: implement arch_segment_loaded callback
    
    This change adds cache management after loading stages.
    Before jumping to a new stage we should flush the data
    caches to memory and invalidate instruction cache.
    After all segments are loaded CBFS cache is also
    flushed.
    
    With this change all stages of coreboot are now executed
    successfully. This was tested on Pistachio bring up board,
    also known as Urara.
    
    Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/arch/mips/cache.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c
index 7d96426..c7a125f 100644
--- a/src/arch/mips/cache.c
+++ b/src/arch/mips/cache.c
@@ -20,6 +20,7 @@
 #include <arch/cache.h>
 #include <arch/cpu.h>
 #include <console/console.h>
+#include <program_loading.h>
 #include <symbols.h>
 
 /* cache_op: issues cache operation for specified address */
@@ -109,3 +110,10 @@ void cache_invalidate_all(uintptr_t start, size_t size)
 	perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
 	perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
 }
+
+void arch_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+	cache_invalidate_all(start, size);
+	if (flags & SEG_FINAL)
+		cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
+}