[coreboot-gerrit] Patch set updated for coreboot: Port Fam14 northbridge code to 64bit
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Sat Jun 20 01:48:34 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10583
-gerrit
commit e8e67ef2934436dfb7e51aae23bc962f3775c226
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Thu Jun 18 01:18:09 2015 -0700
Port Fam14 northbridge code to 64bit
Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Signed-off-by: Scott Duplichan <scott at notabs.org>
---
src/northbridge/amd/agesa/family14/northbridge.c | 6 +++---
src/northbridge/amd/agesa/oem_s3.c | 8 ++++----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index fcc0d87..691fdf6 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -529,7 +529,7 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
- printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
+ printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
unsigned long mmio_basek;
u32 pci_tolm;
@@ -741,11 +741,11 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2);
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2);
return (unsigned long)current;
}
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index dfc1ebc..2897e39 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -39,7 +39,7 @@ typedef enum {
#error "Please increase the value of S3_DATA_SIZE"
#endif
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
+static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len)
{
/* FIXME: Find file from CBFS. */
u32 s3_data = CONFIG_S3_DATA_POS;
@@ -65,7 +65,7 @@ static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams)
{
AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock;
- u32 pos, size;
+ uintptr_t pos, size;
get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
@@ -120,7 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock;
u8 MTRRStorage[S3_DATA_MTRR_SIZE];
u32 MTRRStorageSize = 0;
- u32 pos, size;
+ uintptr_t pos, size;
if (HIGH_ROMSTAGE_STACK_SIZE)
cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
@@ -151,7 +151,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
const void *OemS3Saved_MTRR_Storage(void)
{
- u32 pos, size;
+ uintptr_t pos, size;
get_s3nv_data(S3DataTypeMTRR, &pos, &size);
if (!size)
return NULL;
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