[coreboot-gerrit] Patch set updated for coreboot: 4f7eebb cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
Alexander Couzens (lynxis@fe80.eu)
gerrit at coreboot.org
Thu Mar 12 14:07:55 CET 2015
Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8658
-gerrit
commit 4f7eebbc195352255c5f8a5c1117c6be1dd732b7
Author: Alexander Couzens <lynxis at fe80.eu>
Date: Tue Feb 24 03:07:02 2015 +0100
cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
BIOS Writer's Guide, rev 1.6.0, June 2012:
This MSR controls whether and FERR message is sent over the system bus
when unmasked x87 exceptions are generated.
This feature is not supported from Sandy Bridge processor onwards.
Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
src/cpu/intel/model_2065x/model_2065x.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 454f7be..702eceb 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -35,6 +35,8 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
+#define IA32_FERR_CAPABILITY 0x1f1
+#define FERR_ENABLE (1 << 0)
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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