[coreboot-gerrit] Patch set updated for coreboot: ed4e5b5 rush: Add support for chromeos_ec
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Wed Mar 18 06:47:31 CET 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8724
-gerrit
commit ed4e5b5340f21ba52b7add3d55c2c295db44ea01
Author: Furquan Shaikh <furquan at google.com>
Date: Tue Jul 29 18:47:16 2014 -0700
rush: Add support for chromeos_ec
BUG=chrome-os-partner:31032
BRANCH=None
TEST=Compiles successfully and ec error fixed while booting.
Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210436
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit 5447adb964276b9e13399ac93140ae763a149aad)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
src/mainboard/google/rush/Makefile.inc
Change-Id: I38764a461b4009c6d722ec6fc64fda84a188169f
---
src/mainboard/google/rush/Kconfig | 8 ++++++++
src/mainboard/google/rush/Makefile.inc | 2 --
src/mainboard/google/rush/mainboard.c | 9 +++++++++
src/mainboard/google/rush/romstage.c | 24 ++++++++++++++++++++++++
src/mainboard/google/rush_ryu/romstage.c | 4 ++++
src/soc/nvidia/tegra132/include/soc/romstage.h | 1 +
src/soc/nvidia/tegra132/romstage.c | 1 +
7 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 8c162ec..49e61a4 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -22,6 +22,10 @@ if BOARD_GOOGLE_RUSH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CHROMEOS
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select EC_SOFTWARE_SYNC
+ select SPI_FLASH
select SOC_NVIDIA_TEGRA132
select MAINBOARD_HAS_BOOTBLOCK_INIT
select VIRTUAL_DEV_SWITCH
@@ -86,4 +90,8 @@ config DRIVER_TPM_I2C_ADDR
hex
default 0x20
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 1
+
endif # BOARD_GOOGLE_RUSH
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index e4520c1..b66cd55 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -36,8 +36,6 @@ romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += ec_dummy.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-y += ec_dummy.c
\ No newline at end of file
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index 6db314f..fd8a469 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -23,6 +23,7 @@
#include <soc/clock.h>
#include <soc/nvidia/tegra132/gpio.h>
#include <soc/nvidia/tegra132/clk_rst.h>
+#include <soc/nvidia/tegra132/spi.h>
#include <soc/addressmap.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -84,11 +85,19 @@ static void init_mmc(void)
}
+static void setup_ec_spi(void)
+{
+ struct tegra_spi_channel *spi;
+
+ spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+}
+
static void mainboard_init(device_t dev)
{
clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
init_mmc();
+ setup_ec_spi();
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index 7c01a30..5e74e71 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -51,6 +51,30 @@ void mainboard_init_tpm_i2c(void)
configure_tpm_i2c_bus();
}
+void mainboard_init_ec_spi(void)
+{
+ clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
+
+ // SPI1 MOSI
+ pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 MISO
+ pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 SCLK
+ pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 CS0
+ pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+
+ clock_configure_source(sbc1, CLK_M, 500);
+}
+
void mainboard_configure_pmc(void)
{
}
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 9a41247..9235a77 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -23,6 +23,10 @@ void mainboard_init_tpm_i2c(void)
{
}
+void mainboard_init_ec_spi(void)
+{
+}
+
void mainboard_configure_pmc(void)
{
}
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index f669121..d5fabd2 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -23,5 +23,6 @@
void mainboard_configure_pmc(void);
void mainboard_enable_vdd_cpu(void);
void mainboard_init_tpm_i2c(void);
+void mainboard_init_ec_spi(void);
#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 69271f0..b9932f2 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -68,6 +68,7 @@ void romstage(void)
printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
mainboard_init_tpm_i2c();
+ mainboard_init_ec_spi();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");
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