[coreboot-gerrit] New patch to review for coreboot: 28cd9c2 mainboard/asus/kfsn4-dre: Add romstage timestamps
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Thu Mar 19 22:45:32 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8776
-gerrit
commit 28cd9c2830a2026d0bd8e2fadb697cb70e3e1675
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Thu Mar 19 16:44:46 2015 -0500
mainboard/asus/kfsn4-dre: Add romstage timestamps
Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/mainboard/asus/kfsn4-dre/romstage.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 44864f6..b6f28c4 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -213,6 +213,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -341,8 +344,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -368,6 +374,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Restore default SuperIO access */
outb(0xaa, port);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
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