[coreboot-gerrit] Patch set updated for coreboot: 5e4d9a0 PCI subsystem: Drop PCI_64BIT_PREF_MEM option
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Mar 24 05:29:41 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8705
-gerrit
commit 5e4d9a0d02e493fda6db4b9b73b1e8187b73905c
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Mar 17 06:42:54 2015 +0200
PCI subsystem: Drop PCI_64BIT_PREF_MEM option
No board in the tree selects this at it looks like the implementation
was done at chipset level while it should be part of PCI subsystem.
Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/asus/kfsn4-dre/Kconfig | 4 --
src/mainboard/asus/m2n-e/Kconfig | 4 --
src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 4 --
src/mainboard/gigabyte/m57sli/Kconfig | 4 --
src/mainboard/msi/ms7260/Kconfig | 4 --
src/mainboard/msi/ms9282/Kconfig | 4 --
src/mainboard/nvidia/l1_2pvv/Kconfig | 4 --
src/mainboard/tyan/s2912/Kconfig | 4 --
src/mainboard/tyan/s2912_fam10/Kconfig | 4 --
src/northbridge/amd/agesa/family10/northbridge.c | 77 --------------------
src/northbridge/amd/agesa/family12/northbridge.c | 81 +--------------------
src/northbridge/amd/agesa/family14/northbridge.c | 82 ----------------------
src/northbridge/amd/agesa/family15/northbridge.c | 77 --------------------
src/northbridge/amd/agesa/family15rl/northbridge.c | 77 --------------------
src/northbridge/amd/agesa/family15tn/northbridge.c | 77 --------------------
src/northbridge/amd/agesa/family16kb/northbridge.c | 77 --------------------
src/northbridge/amd/amdfam10/northbridge.c | 76 --------------------
src/northbridge/amd/amdk8/northbridge.c | 68 ------------------
src/northbridge/amd/pi/00630F01/northbridge.c | 77 +-------------------
src/northbridge/amd/pi/00730F01/northbridge.c | 78 --------------------
20 files changed, 2 insertions(+), 881 deletions(-)
diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig
index a7ac369..5957028 100644
--- a/src/mainboard/asus/kfsn4-dre/Kconfig
+++ b/src/mainboard/asus/kfsn4-dre/Kconfig
@@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 12
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
index 7292bf3..c86de2d 100644
--- a/src/mainboard/asus/m2n-e/Kconfig
+++ b/src/mainboard/asus/m2n-e/Kconfig
@@ -65,10 +65,6 @@ config MAINBOARD_PART_NUMBER
string
default "M2N-E"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 2
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index a79c28f..660ac1c 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -45,10 +45,6 @@ config MAINBOARD_PART_NUMBER
string
default "GA-2761GXDK"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 2
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 6ef94ce..3132d37 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER
string
default "GA-M57SLI-S4"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 2
diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index 0e7e592..60ea9ea 100644
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER
string
default "MS-7260"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 2
diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig
index f109375..e88f36f 100644
--- a/src/mainboard/msi/ms9282/Kconfig
+++ b/src/mainboard/msi/ms9282/Kconfig
@@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER
string
default "MS-9282"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 4
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 57911f7..7694492 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -51,10 +51,6 @@ config MAINBOARD_PART_NUMBER
string
default "l1_2pvv"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 4
diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 26d9a53..8b59eb5 100644
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER
string
default "S2912"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 4
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 1dd74ca..1e0d4d0 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER
string
default "S2912 (Fam10)"
-config PCI_64BIT_PREF_MEM
- bool
- default n
-
config MAX_CPUS
int
default 12
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 8e47c1a..6b2ff63 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void amdfam10_domain_enable_resources(device_t dev)
@@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index a3b3493..4cd9156 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
-//- pci_domain_read_resources(dev);
-
struct resource *resource;
/* Initialize the system-wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev)
resource->limit = 0xdfffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-#else
- struct bus *link;
- struct resource *resource;
- for(link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
+
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}
@@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
-printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
- for(link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for(res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index ff669ef..852780b 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-#else
- struct bus *link;
- struct resource *resource;
- for (link = dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0 | (link->link_num << 2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1 | (link->link_num << 2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2 | (link->link_num << 2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void setup_uma_memory(void)
@@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1 | (link->link_num << 2));
- mem2 = find_resource(dev, 2 | (link->link_num << 2));
-
- printk(BIOS_DEBUG,
- "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- (u32) (mem1->base), (u32) (mem1->limit),
- (u32) (mem1->size), u32) (mem1->align));
- printk(BIOS_DEBUG,
- "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- (u32) (mem2->base), (u32) (mem2->limit),
- (u32) (mem2->size), (u32) (mem2->align));
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff))
- || ((mem1->limit > 0xffffffff)
- && (mem2->limit > 0xffffffff))) {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- } else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG,
- "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG,
- "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next) {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 89e1644..aaa63bb 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -668,30 +668,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(device_t dev)
@@ -792,10 +769,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index f83ff2d..4e77758 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -663,30 +663,7 @@ static void domain_read_resources(struct device *dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(struct device *dev)
@@ -787,10 +764,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(struct device *dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -801,56 +774,6 @@ static void domain_set_resources(struct device *dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index d878b4f..9eb502a 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -661,30 +661,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(device_t dev)
@@ -785,10 +762,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -799,56 +772,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index badec55..5178065 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -677,30 +677,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(device_t dev)
@@ -803,10 +780,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -817,56 +790,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 9206de7..cb129a3 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -632,29 +632,8 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-#else
- struct bus *link;
- struct resource *resource;
- for(link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
#if CONFIG_MMCONF_SUPPORT
struct resource *res = new_resource(dev, 0xc0010058);
res->base = CONFIG_MMCONF_BASE_ADDRESS;
@@ -750,10 +729,6 @@ static void setup_uma_memory(void)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
int i, idx;
@@ -763,57 +738,6 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for(link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for(res = dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index a17aa65..b42b6bf 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -667,13 +667,6 @@ static void amdk8_domain_read_resources(device_t dev)
}
pci_domain_read_resources(dev);
-
-#if CONFIG_PCI_64BIT_PREF_MEM
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 2);
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-#endif
}
static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
@@ -904,10 +897,6 @@ static void setup_uma_memory(void)
static void amdk8_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -917,63 +906,6 @@ static void amdk8_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if 0
- /* Place the IO devices somewhere safe */
- io = find_resource(dev, 0);
- io->base = DEVICE_IO_START;
-#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1);
- mem2 = find_resource(dev, 2);
-
-#if 1
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-#endif
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
-#if 1
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-#endif
-
- for(res = dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = my_find_pci_tolm(dev->link_list);
// FIXME handle interleaved nodes. If you fix this here, please fix
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index f8b3246..e5fa0cb 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -654,29 +654,8 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
- if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM))
pci_domain_read_resources(dev);
- else {
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
- }
+
}
static void domain_enable_resources(device_t dev)
@@ -780,10 +759,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -794,56 +769,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index b10da3d..d33f021 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -663,31 +663,7 @@ static void domain_read_resources(device_t dev)
}
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(device_t dev)
@@ -796,10 +772,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -810,56 +782,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);
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