[coreboot-gerrit] New patch to review for coreboot: 808acf5 ryu: switch to padconfig API in romstage
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Mar 24 12:31:50 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8903
-gerrit
commit 808acf5e59dae9216a85ead09d3d9563f8fd85a2
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Aug 1 17:11:31 2014 -0500
ryu: switch to padconfig API in romstage
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built.
Change-Id: Ib3ee8a14a34d0a2e73f3b912879eb65ac2d97c50
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210900
Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
src/mainboard/google/rush_ryu/romstage.c | 64 +++++++++++++-------------------
1 file changed, 25 insertions(+), 39 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 4ebb8ed..3234252 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -19,59 +19,45 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
+#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
-#include <soc/nvidia/tegra132/pinmux.h>
-#include <soc/nvidia/tegra132/gpio.h>
#include <soc/romstage.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-static void configure_tpm_i2c_bus(void)
-{
- clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
- i2c_init(2);
-}
+static const struct pad_config padcfgs[] = {
+ /* AP_SYS_RESET_L */
+ PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
+ /* TPM on I2C3 */
+ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+ /* EC on I2C2 */
+ PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2),
+ PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2),
+};
-static void configure_ec_i2c_bus(void)
-{
- clock_configure_i2c_scl_freq(i2c2, PLLP, 100);
- i2c_init(1);
-}
-
-static void mainboard_init_tpm_i2c(void)
+static void configure_clocks(void)
{
+ /* TPM on I2C3 */
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
+ clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
- gpio_output(GPIO(I5), 1);
-
- /* I2C3 (cam) clock */
- pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
- PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
- /* I2C3 (cam) data */
- pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
- PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
-
- configure_tpm_i2c_bus();
-}
-
-static void mainboard_init_ec_i2c(void)
-{
+ /* EC on I2C2 */
clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);
-
- /* I2C2 (GEN2) clock */
- pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
- PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
- /* I2C2 (GEN2) data */
- pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
- PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
-
- configure_ec_i2c_bus();
+ clock_configure_i2c_scl_freq(i2c2, PLLP, 100);
}
void romstage_mainboard_init(void)
{
- mainboard_init_tpm_i2c();
- mainboard_init_ec_i2c();
+ configure_clocks();
+
+ /* Bring up controller interfaces for ramstage loading. */
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+
+ /* TPM */
+ i2c_init(2);
+ /* EC */
+ i2c_init(1);
}
void mainboard_configure_pmc(void)
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