[coreboot-gerrit] Patch set updated for coreboot: ee9273e tegra132: add more base addresses to address map
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Mar 24 16:12:25 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8933
-gerrit
commit ee9273e07e9f6e229144c3bf250e34ea8bc7ee51
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Aug 13 15:07:43 2014 -0500
tegra132: add more base addresses to address map
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f
Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212168
Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
src/soc/nvidia/tegra132/include/soc/addressmap.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h
index 2a21c30..732c9e9 100644
--- a/src/soc/nvidia/tegra132/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h
@@ -66,12 +66,23 @@ enum {
TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00,
TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00,
TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00,
+ TEGRA_SBC1_BASE = TEGRA_SPI1_BASE,
+ TEGRA_SBC2_BASE = TEGRA_SPI2_BASE,
+ TEGRA_SBC3_BASE = TEGRA_SPI3_BASE,
+ TEGRA_SBC4_BASE = TEGRA_SPI4_BASE,
+ TEGRA_SBC5_BASE = TEGRA_SPI5_BASE,
+ TEGRA_SBC6_BASE = TEGRA_SPI6_BASE,
TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
TEGRA_MC_BASE = 0x70019000,
TEGRA_EMC_BASE = 0x7001B000,
TEGRA_CLUSTER_CLOCK_BASE = 0x70040000,
TEGRA_CSITE_BASE = 0x70800000,
+ TEGRA_SDMMC_BASE = 0x700b0000,
+ TEGRA_SDMMC1_BASE = TEGRA_SDMMC_BASE + 0x0000,
+ TEGRA_SDMMC2_BASE = TEGRA_SDMMC_BASE + 0x0200,
+ TEGRA_SDMMC3_BASE = TEGRA_SDMMC_BASE + 0x0400,
+ TEGRA_SDMMC4_BASE = TEGRA_SDMMC_BASE + 0x0600,
TEGRA_SYSCTR0_BASE = 0x700F0000,
TEGRA_USBD_BASE = 0x7D000000,
TEGRA_USB2_BASE = 0x7D004000,
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