[coreboot-gerrit] Patch set updated for coreboot: libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12325

-gerrit

commit a5f84f680c7d4d837241a0b1cd6f9a32957f2b54
Author: Rajmohan Mani <rajmohan.mani at intel.com>
Date:   Fri Oct 30 17:00:24 2015 -0700

    libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably
    
    Existing Intel xHCI controllers require a delay of 1 mS,
    after setting the CMD_RESET bit in command register, before
    accessing any HC registers. This allows the HC to complete
    the reset operation and be ready for HC register access.
    Without this delay, the subsequent HC register access,
    may result in a system hang, very rarely.
    
    Verified CherryView / Braswell platforms go through over
    1000 warm reboot cycles (which was not possible without
    this patch), without any xHCI reset hang in depthcharge.
    
    BRANCH=None
    BUG=None
    TEST=Verified CherryView / Braswell platforms go through
    over 1000 warm reboot cycles, without any xHCI reset hang
    in depthcharge.
    
    Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac
    Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460
    Original-Signed-off-by: Rajmohan Mani <rajmohan.mani at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/310022
    Original-Reviewed-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/drivers/usb/xhci.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c
index 71272c7..d223d0f 100644
--- a/payloads/libpayload/drivers/usb/xhci.c
+++ b/payloads/libpayload/drivers/usb/xhci.c
@@ -328,6 +328,17 @@ xhci_reset(hci_t *const controller)
 	xhci_stop(controller);
 
 	xhci->opreg->usbcmd |= USBCMD_HCRST;
+
+	/* Existing Intel xHCI controllers require a delay of 1 ms,
+	 * after setting the CMD_RESET bit, and before accessing any
+	 * HC registers. This allows the HC to complete the
+	 * reset operation and be ready for HC register access.
+	 * Without this delay, the subsequent HC register access,
+	 * may result in a system hang very rarely.
+	 */
+	if (IS_ENABLED(CONFIG_LP_ARCH_X86))
+		mdelay(1);
+
 	xhci_debug("Resetting controller... ");
 	if (!xhci_handshake(&xhci->opreg->usbcmd, USBCMD_HCRST, 0, 1000000L))
 		usb_debug("timeout!\n");