[coreboot-gerrit] New patch to review for coreboot: google/chell: Fix USB port assignment again

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12389

-gerrit

commit 5e9ac38abaeb4d859663f54bc4ad6543ec13ebeb
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Nov 5 07:12:33 2015 -0800

    google/chell: Fix USB port assignment again
    
    The net names are offset by 1.  My board is not stable enough
    to really test all of these yet...
    
    BUG=chrome-os-partner:46289
    BRANCH=none
    TEST=emerge-chell coreboot
    
    Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
    Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/311113
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/chell/devicetree.cb | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 05e37bf..d515068 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -54,11 +54,11 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[4]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
-	register "usb2_ports[3]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[5]" = "USB2_PORT_MID"     # Type-A Port
-	register "usb2_ports[7]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[9]" = "USB2_PORT_MID"     # SD
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
+	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port
+	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
+	register "usb2_ports[8]" = "USB2_PORT_MID"     # SD
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2