[coreboot-gerrit] Patch set updated for coreboot: amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Sun Oct 18 04:29:07 CEST 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12037
-gerrit
commit 8eae9467532da81388748e9a8afe3141fc9813b2
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Sat Aug 8 20:29:55 2015 -0500
amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 45cd8d0..df3ee9f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5564,6 +5564,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */
val |= (0x1 << 8);
val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */
+ val |= (0x1 << 20); /* DblPrefEn = 0x1 */
val |= (0x7 << 22); /* PrefFourConf = 0x7 */
val |= (0x7 << 25); /* PrefFiveConf = 0x7 */
val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */
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